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CLASS="SECTION"
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><H1
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><H1
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CLASS="SECTION"
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CLASS="SECTION"
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><A
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><A
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NAME="HAL-CACHE-CONTROL">Cache Control</H1
|
NAME="HAL-CACHE-CONTROL">Cache Control</H1
|
><P
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><P
|
>This section contains definitions for supporting control
|
>This section contains definitions for supporting control
|
of the caches on the CPU.</P
|
of the caches on the CPU.</P
|
><P
|
><P
|
>These definitions are usually found in the header file
|
>These definitions are usually found in the header file
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>cyg/hal/hal_cache.h</TT
|
>cyg/hal/hal_cache.h</TT
|
>. This file may be defined in
|
>. This file may be defined in
|
the architecture, variant or platform HAL, depending on where the
|
the architecture, variant or platform HAL, depending on where the
|
caches are implemented for the target. Often there will be a generic
|
caches are implemented for the target. Often there will be a generic
|
implementation of the cache control macros in the architecture HAL
|
implementation of the cache control macros in the architecture HAL
|
with the ability to override or undefine them in the variant or
|
with the ability to override or undefine them in the variant or
|
platform HAL. Even when the implementation of the cache macros is in
|
platform HAL. Even when the implementation of the cache macros is in
|
the architecture HAL, the cache dimensions will be defined in the
|
the architecture HAL, the cache dimensions will be defined in the
|
variant or platform HAL. As with other files, the variant or platform
|
variant or platform HAL. As with other files, the variant or platform
|
specific definitions are usually found in
|
specific definitions are usually found in
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>cyg/hal/var_cache.h</TT
|
>cyg/hal/var_cache.h</TT
|
> and
|
> and
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>cyg/hal/plf_cache.h</TT
|
>cyg/hal/plf_cache.h</TT
|
> respectively. These files
|
> respectively. These files
|
are include automatically by this header, so need not be included
|
are include automatically by this header, so need not be included
|
explicitly.</P
|
explicitly.</P
|
><P
|
><P
|
>There are versions of the macros defined here for both the Data and
|
>There are versions of the macros defined here for both the Data and
|
Instruction caches. these are distinguished by the use of either
|
Instruction caches. these are distinguished by the use of either
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>DCACHE</TT
|
>DCACHE</TT
|
> or <TT
|
> or <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>ICACHE</TT
|
>ICACHE</TT
|
> in the macro
|
> in the macro
|
names. Some architectures have a unified cache, where both data and
|
names. Some architectures have a unified cache, where both data and
|
instruction share the same cache. In these cases the control macros
|
instruction share the same cache. In these cases the control macros
|
use <TT
|
use <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>UCACHE</TT
|
>UCACHE</TT
|
> and the <TT
|
> and the <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>DCACHE</TT
|
>DCACHE</TT
|
> and
|
> and
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>ICACHE</TT
|
>ICACHE</TT
|
> macros will just be calls to the
|
> macros will just be calls to the
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>UCACHE</TT
|
>UCACHE</TT
|
> version. In the following descriptions,
|
> version. In the following descriptions,
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>XCACHE</TT
|
>XCACHE</TT
|
> is used to stand for any of these. Where
|
> is used to stand for any of these. Where
|
there are issues specific to a particular cache, this will be
|
there are issues specific to a particular cache, this will be
|
explained in the text.</P
|
explained in the text.</P
|
><P
|
><P
|
>There might be target specific restrictions on the use of some of the
|
>There might be target specific restrictions on the use of some of the
|
macros which it is the user's responsibility to comply with. Such
|
macros which it is the user's responsibility to comply with. Such
|
restrictions are documented in the header file with the macro
|
restrictions are documented in the header file with the macro
|
definition.</P
|
definition.</P
|
><P
|
><P
|
>Note that destructive cache macros should be used with caution.
|
>Note that destructive cache macros should be used with caution.
|
Preceding a cache invalidation with a cache synchronization is not
|
Preceding a cache invalidation with a cache synchronization is not
|
safe in itself since an interrupt may happen after the synchronization
|
safe in itself since an interrupt may happen after the synchronization
|
but before the invalidation. This might cause the state of dirty data
|
but before the invalidation. This might cause the state of dirty data
|
lines created during the interrupt to be lost.</P
|
lines created during the interrupt to be lost.</P
|
><P
|
><P
|
>Depending on the architecture's capabilities, it may be possible to
|
>Depending on the architecture's capabilities, it may be possible to
|
temporarily disable the cache while doing the synchronization and
|
temporarily disable the cache while doing the synchronization and
|
invalidation which solves the problem (no new data would be cached
|
invalidation which solves the problem (no new data would be cached
|
during an interrupt). Otherwise it is necessary to disable interrupts
|
during an interrupt). Otherwise it is necessary to disable interrupts
|
while manipulating the cache which may take a long time.</P
|
while manipulating the cache which may take a long time.</P
|
><P
|
><P
|
>Some platform HALs now support a pair of cache state query
|
>Some platform HALs now support a pair of cache state query
|
macros: <TT
|
macros: <TT
|
CLASS="FUNCTION"
|
CLASS="FUNCTION"
|
>HAL_ICACHE_IS_ENABLED( x )</TT
|
>HAL_ICACHE_IS_ENABLED( x )</TT
|
> and
|
> and
|
<TT
|
<TT
|
CLASS="FUNCTION"
|
CLASS="FUNCTION"
|
>HAL_DCACHE_IS_ENABLED( x )</TT
|
>HAL_DCACHE_IS_ENABLED( x )</TT
|
> which set the argument
|
> which set the argument
|
to true if the instruction or data cache is enabled,
|
to true if the instruction or data cache is enabled,
|
respectively. Like most cache control macros, these are optional,
|
respectively. Like most cache control macros, these are optional,
|
because the capabilities of different targets and boards can vary
|
because the capabilities of different targets and boards can vary
|
considerably. Code which uses them, if it is to be considered
|
considerably. Code which uses them, if it is to be considered
|
portable, should test for their existence first by means of
|
portable, should test for their existence first by means of
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>#ifdef</TT
|
>#ifdef</TT
|
>. Be sure to include
|
>. Be sure to include
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
><cyg/hal/hal_cache.h></TT
|
><cyg/hal/hal_cache.h></TT
|
> in order to do this
|
> in order to do this
|
test and (maybe) use the macros.</P
|
test and (maybe) use the macros.</P
|
><DIV
|
><DIV
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><H2
|
><H2
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><A
|
><A
|
NAME="AEN8115">Cache Dimensions</H2
|
NAME="AEN8115">Cache Dimensions</H2
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>HAL_XCACHE_SIZE
|
>HAL_XCACHE_SIZE
|
HAL_XCACHE_LINE_SIZE
|
HAL_XCACHE_LINE_SIZE
|
HAL_XCACHE_WAYS
|
HAL_XCACHE_WAYS
|
HAL_XCACHE_SETS</PRE
|
HAL_XCACHE_SETS</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>These macros define the size and dimensions of the Instruction
|
>These macros define the size and dimensions of the Instruction
|
and Data caches.</P
|
and Data caches.</P
|
><P
|
><P
|
></P
|
></P
|
><DIV
|
><DIV
|
CLASS="VARIABLELIST"
|
CLASS="VARIABLELIST"
|
><DL
|
><DL
|
><DT
|
><DT
|
>HAL_XCACHE_SIZE</DT
|
>HAL_XCACHE_SIZE</DT
|
><DD
|
><DD
|
><P
|
><P
|
>Defines the total size of the cache in bytes.</P
|
>Defines the total size of the cache in bytes.</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_LINE_SIZE</DT
|
>HAL_XCACHE_LINE_SIZE</DT
|
><DD
|
><DD
|
><P
|
><P
|
>Defines the cache line size in bytes.</P
|
>Defines the cache line size in bytes.</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_WAYS</DT
|
>HAL_XCACHE_WAYS</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Defines the number of ways in each set and defines its level
|
> Defines the number of ways in each set and defines its level
|
of associativity. This would be 1 for a direct mapped
|
of associativity. This would be 1 for a direct mapped
|
cache, 2 for a 2-way cache, 4 for 4-way and so on.
|
cache, 2 for a 2-way cache, 4 for 4-way and so on.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_SETS</DT
|
>HAL_XCACHE_SETS</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Defines the number of sets in the cache, and is calculated from
|
> Defines the number of sets in the cache, and is calculated from
|
the previous values.
|
the previous values.
|
</P
|
</P
|
></DD
|
></DD
|
></DL
|
></DL
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><H2
|
><H2
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><A
|
><A
|
NAME="AEN8136">Global Cache Control</H2
|
NAME="AEN8136">Global Cache Control</H2
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>HAL_XCACHE_ENABLE()
|
>HAL_XCACHE_ENABLE()
|
HAL_XCACHE_DISABLE()
|
HAL_XCACHE_DISABLE()
|
HAL_XCACHE_INVALIDATE_ALL()
|
HAL_XCACHE_INVALIDATE_ALL()
|
HAL_XCACHE_SYNC()
|
HAL_XCACHE_SYNC()
|
HAL_XCACHE_BURST_SIZE( size )
|
HAL_XCACHE_BURST_SIZE( size )
|
HAL_DCACHE_WRITE_MODE( mode )
|
HAL_DCACHE_WRITE_MODE( mode )
|
HAL_XCACHE_LOCK( base, size )
|
HAL_XCACHE_LOCK( base, size )
|
HAL_XCACHE_UNLOCK( base, size )
|
HAL_XCACHE_UNLOCK( base, size )
|
HAL_XCACHE_UNLOCK_ALL()</PRE
|
HAL_XCACHE_UNLOCK_ALL()</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>These macros affect the state of the entire cache, or a large part of
|
>These macros affect the state of the entire cache, or a large part of
|
it.</P
|
it.</P
|
><P
|
><P
|
></P
|
></P
|
><DIV
|
><DIV
|
CLASS="VARIABLELIST"
|
CLASS="VARIABLELIST"
|
><DL
|
><DL
|
><DT
|
><DT
|
>HAL_XCACHE_ENABLE() and HAL_XCACHE_DISABLE()</DT
|
>HAL_XCACHE_ENABLE() and HAL_XCACHE_DISABLE()</DT
|
><DD
|
><DD
|
><P
|
><P
|
>Enable and disable the cache.</P
|
>Enable and disable the cache.</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_INVALIDATE_ALL()</DT
|
>HAL_XCACHE_INVALIDATE_ALL()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Causes the entire contents of the cache to be invalidated.
|
> Causes the entire contents of the cache to be invalidated.
|
Depending on the hardware, this may require the cache to be disabled
|
Depending on the hardware, this may require the cache to be disabled
|
during the invalidation process. If so, the implementation must
|
during the invalidation process. If so, the implementation must
|
use <TT
|
use <TT
|
CLASS="FUNCTION"
|
CLASS="FUNCTION"
|
>HAL_XCACHE_IS_ENABLED()</TT
|
>HAL_XCACHE_IS_ENABLED()</TT
|
> to save and
|
> to save and
|
restore the previous state.
|
restore the previous state.
|
</P
|
</P
|
><DIV
|
><DIV
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><BLOCKQUOTE
|
><BLOCKQUOTE
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><P
|
><P
|
><B
|
><B
|
>Note: </B
|
>Note: </B
|
> If this macro is called after
|
> If this macro is called after
|
<TT
|
<TT
|
CLASS="FUNCTION"
|
CLASS="FUNCTION"
|
>HAL_XCACHE_SYNC()</TT
|
>HAL_XCACHE_SYNC()</TT
|
> with the intention of clearing
|
> with the intention of clearing
|
the cache (invalidating the cache after writing dirty data back to
|
the cache (invalidating the cache after writing dirty data back to
|
memory), you must prevent interrupts from happening between the two
|
memory), you must prevent interrupts from happening between the two
|
calls:
|
calls:
|
</P
|
</P
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
> ...
|
> ...
|
HAL_DISABLE_INTERRUPTS(old);
|
HAL_DISABLE_INTERRUPTS(old);
|
HAL_XCACHE_SYNC();
|
HAL_XCACHE_SYNC();
|
HAL_XCACHE_INVALIDATE_ALL();
|
HAL_XCACHE_INVALIDATE_ALL();
|
HAL_RESTORE_INTERRUPTS(old);
|
HAL_RESTORE_INTERRUPTS(old);
|
...</PRE
|
...</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
> Since the operation may take a very long time, real-time
|
> Since the operation may take a very long time, real-time
|
responsiveness could be affected, so only do this when it is
|
responsiveness could be affected, so only do this when it is
|
absolutely required and you know the delay will not interfere
|
absolutely required and you know the delay will not interfere
|
with the operation of drivers or the application.
|
with the operation of drivers or the application.
|
</P
|
</P
|
></BLOCKQUOTE
|
></BLOCKQUOTE
|
></DIV
|
></DIV
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_SYNC()</DT
|
>HAL_XCACHE_SYNC()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Causes the contents of the cache to be brought into synchronization
|
> Causes the contents of the cache to be brought into synchronization
|
with the contents of memory. In some implementations this may be
|
with the contents of memory. In some implementations this may be
|
equivalent to <TT
|
equivalent to <TT
|
CLASS="FUNCTION"
|
CLASS="FUNCTION"
|
>HAL_XCACHE_INVALIDATE_ALL()</TT
|
>HAL_XCACHE_INVALIDATE_ALL()</TT
|
>.
|
>.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_BURST_SIZE()</DT
|
>HAL_XCACHE_BURST_SIZE()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Allows the size of cache to/from memory bursts to
|
> Allows the size of cache to/from memory bursts to
|
be controlled. This macro will only be defined if this functionality
|
be controlled. This macro will only be defined if this functionality
|
is available.
|
is available.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_DCACHE_WRITE_MODE()</DT
|
>HAL_DCACHE_WRITE_MODE()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Controls the way in which data cache lines are written back to
|
> Controls the way in which data cache lines are written back to
|
memory. There will be definitions for the possible
|
memory. There will be definitions for the possible
|
modes. Typical definitions are
|
modes. Typical definitions are
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>HAL_DCACHE_WRITEBACK_MODE</TT
|
>HAL_DCACHE_WRITEBACK_MODE</TT
|
> and
|
> and
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>HAL_DCACHE_WRITETHRU_MODE</TT
|
>HAL_DCACHE_WRITETHRU_MODE</TT
|
>. This macro will
|
>. This macro will
|
only be defined if this functionality is available.
|
only be defined if this functionality is available.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_LOCK()</DT
|
>HAL_XCACHE_LOCK()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Causes data to be locked into the cache. The base and size
|
> Causes data to be locked into the cache. The base and size
|
arguments define the memory region that will be locked into the
|
arguments define the memory region that will be locked into the
|
cache. It is architecture dependent whether more than one locked
|
cache. It is architecture dependent whether more than one locked
|
region is allowed at any one time, and whether this operation
|
region is allowed at any one time, and whether this operation
|
causes the cache to cease acting as a cache for addresses
|
causes the cache to cease acting as a cache for addresses
|
outside the region during the duration of the lock. This macro
|
outside the region during the duration of the lock. This macro
|
will only be defined if this functionality is available.
|
will only be defined if this functionality is available.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_UNLOCK()</DT
|
>HAL_XCACHE_UNLOCK()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Cancels the locking of the memory region given. This should
|
> Cancels the locking of the memory region given. This should
|
normally correspond to a region supplied in a matching lock
|
normally correspond to a region supplied in a matching lock
|
call. This macro will only be defined if this functionality is
|
call. This macro will only be defined if this functionality is
|
available.
|
available.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_UNLOCK_ALL()</DT
|
>HAL_XCACHE_UNLOCK_ALL()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Cancels all existing locked memory regions. This may be required
|
> Cancels all existing locked memory regions. This may be required
|
as part of the cache initialization on some architectures. This
|
as part of the cache initialization on some architectures. This
|
macro will only be defined if this functionality is available.
|
macro will only be defined if this functionality is available.
|
</P
|
</P
|
></DD
|
></DD
|
></DL
|
></DL
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><H2
|
><H2
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><A
|
><A
|
NAME="AEN8182">Cache Line Control</H2
|
NAME="AEN8182">Cache Line Control</H2
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>HAL_DCACHE_ALLOCATE( base , size )
|
>HAL_DCACHE_ALLOCATE( base , size )
|
HAL_DCACHE_FLUSH( base , size )
|
HAL_DCACHE_FLUSH( base , size )
|
HAL_XCACHE_INVALIDATE( base , size )
|
HAL_XCACHE_INVALIDATE( base , size )
|
HAL_DCACHE_STORE( base , size )
|
HAL_DCACHE_STORE( base , size )
|
HAL_DCACHE_READ_HINT( base , size )
|
HAL_DCACHE_READ_HINT( base , size )
|
HAL_DCACHE_WRITE_HINT( base , size )
|
HAL_DCACHE_WRITE_HINT( base , size )
|
HAL_DCACHE_ZERO( base , size )</PRE
|
HAL_DCACHE_ZERO( base , size )</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>All of these macros apply a cache operation to all cache lines that
|
>All of these macros apply a cache operation to all cache lines that
|
match the memory address region defined by the base and size
|
match the memory address region defined by the base and size
|
arguments. These macros will only be defined if the described
|
arguments. These macros will only be defined if the described
|
functionality is available. Also, it is not guaranteed that the cache
|
functionality is available. Also, it is not guaranteed that the cache
|
function will only be applied to just the described regions, in some
|
function will only be applied to just the described regions, in some
|
architectures it may be applied to the whole cache.</P
|
architectures it may be applied to the whole cache.</P
|
><P
|
><P
|
></P
|
></P
|
><DIV
|
><DIV
|
CLASS="VARIABLELIST"
|
CLASS="VARIABLELIST"
|
><DL
|
><DL
|
><DT
|
><DT
|
>HAL_DCACHE_ALLOCATE()</DT
|
>HAL_DCACHE_ALLOCATE()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Allocates lines in the cache for the given region without
|
> Allocates lines in the cache for the given region without
|
reading their contents from memory, hence the contents of the lines
|
reading their contents from memory, hence the contents of the lines
|
is undefined. This is useful for preallocating lines which are to
|
is undefined. This is useful for preallocating lines which are to
|
be completely overwritten, for example in a block copy
|
be completely overwritten, for example in a block copy
|
operation.
|
operation.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_DCACHE_FLUSH()</DT
|
>HAL_DCACHE_FLUSH()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Invalidates all cache lines in the region after writing any
|
> Invalidates all cache lines in the region after writing any
|
dirty lines to memory.
|
dirty lines to memory.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_XCACHE_INVALIDATE()</DT
|
>HAL_XCACHE_INVALIDATE()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Invalidates all cache lines in the region. Any dirty lines
|
> Invalidates all cache lines in the region. Any dirty lines
|
are invalidated without being written to memory.
|
are invalidated without being written to memory.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_DCACHE_STORE()</DT
|
>HAL_DCACHE_STORE()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Writes all dirty lines in the region to memory, but does not
|
> Writes all dirty lines in the region to memory, but does not
|
invalidate any lines.
|
invalidate any lines.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_DCACHE_READ_HINT()</DT
|
>HAL_DCACHE_READ_HINT()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Hints to the cache that the region is going to be read from
|
> Hints to the cache that the region is going to be read from
|
in the near future. This may cause the region to be speculatively
|
in the near future. This may cause the region to be speculatively
|
read into the cache.
|
read into the cache.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_DCACHE_WRITE_HINT()</DT
|
>HAL_DCACHE_WRITE_HINT()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Hints to the cache that the region is going to be written
|
> Hints to the cache that the region is going to be written
|
to in the near future. This may have the identical behavior to
|
to in the near future. This may have the identical behavior to
|
HAL_DCACHE_READ_HINT().
|
HAL_DCACHE_READ_HINT().
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>HAL_DCACHE_ZERO()</DT
|
>HAL_DCACHE_ZERO()</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Allocates and zeroes lines in the cache for the given
|
> Allocates and zeroes lines in the cache for the given
|
region without reading memory. This is useful if a large area of
|
region without reading memory. This is useful if a large area of
|
memory is to be cleared.
|
memory is to be cleared.
|
</P
|
</P
|
></DD
|
></DD
|
></DL
|
></DL
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
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|
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|
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|
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