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>Chapter 9. HAL Interfaces</TD
>Chapter 9. HAL Interfaces</TD
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><H1
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CLASS="SECTION"
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><A
><A
NAME="HAL-INPUT-AND-OUTPUT">HAL I/O</H1
NAME="HAL-INPUT-AND-OUTPUT">HAL I/O</H1
><P
><P
>This section contains definitions for supporting access
>This section contains definitions for supporting access
to device control registers in an architecture neutral
to device control registers in an architecture neutral
fashion.</P
fashion.</P
><P
><P
>These definitions are normally found in the header file
>These definitions are normally found in the header file
<TT
<TT
CLASS="FILENAME"
CLASS="FILENAME"
>cyg/hal/hal_io.h</TT
>cyg/hal/hal_io.h</TT
>.  This file itself contains
>.  This file itself contains
macros that are generic to the architecture. If there are variant or
macros that are generic to the architecture. If there are variant or
platform specific IO access macros then these will be found in
platform specific IO access macros then these will be found in
<TT
<TT
CLASS="FILENAME"
CLASS="FILENAME"
>cyg/hal/var_io.h</TT
>cyg/hal/var_io.h</TT
> and
> and
<TT
<TT
CLASS="FILENAME"
CLASS="FILENAME"
>cyg/hal/plf_io.h</TT
>cyg/hal/plf_io.h</TT
> in the variant or platform HALs
> in the variant or platform HALs
respectively. These files are include automatically by this header, so
respectively. These files are include automatically by this header, so
need not be included explicitly.</P
need not be included explicitly.</P
><P
><P
>This header (or more likely <TT
>This header (or more likely <TT
CLASS="FILENAME"
CLASS="FILENAME"
>cyg/hal/plf_io.h</TT
>cyg/hal/plf_io.h</TT
>) also
>) also
defines the PCI access macros. For more information on these see <A
defines the PCI access macros. For more information on these see <A
HREF="pci-library-reference.html"
HREF="pci-library-reference.html"
>the Section called <I
>the Section called <I
>PCI Library reference</I
>PCI Library reference</I
> in Chapter 30</A
> in Chapter 30</A
>.</P
>.</P
><DIV
><DIV
CLASS="SECTION"
CLASS="SECTION"
><H2
><H2
CLASS="SECTION"
CLASS="SECTION"
><A
><A
NAME="AEN8057">Register address</H2
NAME="AEN8057">Register address</H2
><TABLE
><TABLE
BORDER="5"
BORDER="5"
BGCOLOR="#E0E0F0"
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WIDTH="70%"
WIDTH="70%"
><TR
><TR
><TD
><TD
><PRE
><PRE
CLASS="PROGRAMLISTING"
CLASS="PROGRAMLISTING"
>HAL_IO_REGISTER</PRE
>HAL_IO_REGISTER</PRE
></TD
></TD
></TR
></TR
></TABLE
></TABLE
><P
><P
>This type is used to store the address of an I/O register. It will
>This type is used to store the address of an I/O register. It will
normally be a memory address, an integer port address or an offset
normally be a memory address, an integer port address or an offset
into an I/O space. More complex architectures may need to code an
into an I/O space. More complex architectures may need to code an
address space plus offset pair into a single word, or may represent it
address space plus offset pair into a single word, or may represent it
as a structure.</P
as a structure.</P
><P
><P
>Values of variables and constants of this type will usually be
>Values of variables and constants of this type will usually be
supplied by configuration mechanisms or in target specific headers.</P
supplied by configuration mechanisms or in target specific headers.</P
></DIV
></DIV
><DIV
><DIV
CLASS="SECTION"
CLASS="SECTION"
><H2
><H2
CLASS="SECTION"
CLASS="SECTION"
><A
><A
NAME="AEN8062">Register read</H2
NAME="AEN8062">Register read</H2
><TABLE
><TABLE
BORDER="5"
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><TR
><TR
><TD
><TD
><PRE
><PRE
CLASS="PROGRAMLISTING"
CLASS="PROGRAMLISTING"
>HAL_READ_XXX( register, value )
>HAL_READ_XXX( register, value )
HAL_READ_XXX_VECTOR( register, buffer, count, stride )</PRE
HAL_READ_XXX_VECTOR( register, buffer, count, stride )</PRE
></TD
></TD
></TR
></TR
></TABLE
></TABLE
><P
><P
>These macros support the reading of I/O registers in various
>These macros support the reading of I/O registers in various
sizes. The <TT
sizes. The <TT
CLASS="REPLACEABLE"
CLASS="REPLACEABLE"
><I
><I
>XXX</I
>XXX</I
></TT
></TT
> component of the name may be
> component of the name may be
<TT
<TT
CLASS="LITERAL"
CLASS="LITERAL"
>UINT8</TT
>UINT8</TT
>, <TT
>, <TT
CLASS="LITERAL"
CLASS="LITERAL"
>UINT16</TT
>UINT16</TT
>,
>,
<TT
<TT
CLASS="LITERAL"
CLASS="LITERAL"
>UINT32</TT
>UINT32</TT
>.</P
>.</P
><P
><P
><TT
><TT
CLASS="FUNCTION"
CLASS="FUNCTION"
>HAL_READ_XXX()</TT
>HAL_READ_XXX()</TT
> reads the appropriately sized
> reads the appropriately sized
value from the register and stores it in the variable passed as the
value from the register and stores it in the variable passed as the
second argument.</P
second argument.</P
><P
><P
><TT
><TT
CLASS="FUNCTION"
CLASS="FUNCTION"
>HAL_READ_XXX_VECTOR()</TT
>HAL_READ_XXX_VECTOR()</TT
> reads
> reads
<TT
<TT
CLASS="PARAMETER"
CLASS="PARAMETER"
><I
><I
>count</I
>count</I
></TT
></TT
> values of the appropriate size into
> values of the appropriate size into
<TT
<TT
CLASS="PARAMETER"
CLASS="PARAMETER"
><I
><I
>buffer</I
>buffer</I
></TT
></TT
>. The <TT
>. The <TT
CLASS="PARAMETER"
CLASS="PARAMETER"
><I
><I
>stride</I
>stride</I
></TT
></TT
>
>
controls how the pointer advances through the register space. A stride
controls how the pointer advances through the register space. A stride
of zero will read the same register repeatedly, and a stride of one
of zero will read the same register repeatedly, and a stride of one
will read adjacent registers of the given size. Greater strides will
will read adjacent registers of the given size. Greater strides will
step by larger amounts, to allow for sparsely mapped registers for
step by larger amounts, to allow for sparsely mapped registers for
example.</P
example.</P
></DIV
></DIV
><DIV
><DIV
CLASS="SECTION"
CLASS="SECTION"
><H2
><H2
CLASS="SECTION"
CLASS="SECTION"
><A
><A
NAME="AEN8077">Register write</H2
NAME="AEN8077">Register write</H2
><TABLE
><TABLE
BORDER="5"
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WIDTH="70%"
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><TR
><TR
><TD
><TD
><PRE
><PRE
CLASS="PROGRAMLISTING"
CLASS="PROGRAMLISTING"
>HAL_WRITE_XXX( register, value )
>HAL_WRITE_XXX( register, value )
HAL_WRITE_XXX_VECTOR( register, buffer,count, stride )</PRE
HAL_WRITE_XXX_VECTOR( register, buffer,count, stride )</PRE
></TD
></TD
></TR
></TR
></TABLE
></TABLE
><P
><P
>These macros support the writing of I/O registers in various
>These macros support the writing of I/O registers in various
sizes. The <TT
sizes. The <TT
CLASS="REPLACEABLE"
CLASS="REPLACEABLE"
><I
><I
>XXX</I
>XXX</I
></TT
></TT
> component of the name may be
> component of the name may be
<TT
<TT
CLASS="LITERAL"
CLASS="LITERAL"
>UINT8</TT
>UINT8</TT
>, <TT
>, <TT
CLASS="LITERAL"
CLASS="LITERAL"
>UINT16</TT
>UINT16</TT
>,
>,
<TT
<TT
CLASS="LITERAL"
CLASS="LITERAL"
>UINT32</TT
>UINT32</TT
>.</P
>.</P
><P
><P
><TT
><TT
CLASS="FUNCTION"
CLASS="FUNCTION"
>HAL_WRITE_XXX()</TT
>HAL_WRITE_XXX()</TT
> writes
> writes
the appropriately sized value from the variable passed as the second argument
the appropriately sized value from the variable passed as the second argument
stored it in the register.</P
stored it in the register.</P
><P
><P
><TT
><TT
CLASS="FUNCTION"
CLASS="FUNCTION"
>HAL_WRITE_XXX_VECTOR()</TT
>HAL_WRITE_XXX_VECTOR()</TT
> writes
> writes
<TT
<TT
CLASS="PARAMETER"
CLASS="PARAMETER"
><I
><I
>count</I
>count</I
></TT
></TT
> values of the appropriate size from <TT
> values of the appropriate size from <TT
CLASS="PARAMETER"
CLASS="PARAMETER"
><I
><I
>buffer</I
>buffer</I
></TT
></TT
>. The <TT
>. The <TT
CLASS="PARAMETER"
CLASS="PARAMETER"
><I
><I
>stride</I
>stride</I
></TT
></TT
> controls
> controls
how the pointer advances through the register space. A stride of
how the pointer advances through the register space. A stride of
zero will write the same register repeatedly, and a stride of one
zero will write the same register repeatedly, and a stride of one
will write adjacent registers of the given size. Greater strides
will write adjacent registers of the given size. Greater strides
will step by larger amounts, to allow for sparsely mapped registers
will step by larger amounts, to allow for sparsely mapped registers
for example.</P
for example.</P
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