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><H1
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><H1
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CLASS="SECTION"
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CLASS="SECTION"
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><A
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><A
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NAME="HAL-PORTING-VARIANT">Variant HAL Porting</H1
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NAME="HAL-PORTING-VARIANT">Variant HAL Porting</H1
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><P
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><P
|
>A variant port can be a fairly limited job, but can also
|
>A variant port can be a fairly limited job, but can also
|
require quite a lot of work. A variant HAL describes how a specific
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require quite a lot of work. A variant HAL describes how a specific
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CPU variant differs from the generic CPU architecture. The variant HAL
|
CPU variant differs from the generic CPU architecture. The variant HAL
|
can re-define cache, MMU, interrupt, and other features which override
|
can re-define cache, MMU, interrupt, and other features which override
|
the default implementation provided by the architecture HAL.</P
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the default implementation provided by the architecture HAL.</P
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><P
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><P
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>Doing a variant port requires a preexisting architecture HAL port. It
|
>Doing a variant port requires a preexisting architecture HAL port. It
|
is also likely that a platform port will have to be done at the same
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is also likely that a platform port will have to be done at the same
|
time if it is to be tested.</P
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time if it is to be tested.</P
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><DIV
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><DIV
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CLASS="SECTION"
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CLASS="SECTION"
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><H2
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><H2
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CLASS="SECTION"
|
CLASS="SECTION"
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><A
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><A
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NAME="AEN9745">HAL Variant Porting Process</H2
|
NAME="AEN9745">HAL Variant Porting Process</H2
|
><P
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><P
|
>The easiest way to make a new variant HAL is simply to copy an
|
>The easiest way to make a new variant HAL is simply to copy an
|
existing variant HAL and change all the files to match the new
|
existing variant HAL and change all the files to match the new
|
variant. If this is the first variant for an architecture, it may be
|
variant. If this is the first variant for an architecture, it may be
|
hard to decide which parts should be put in the variant - knowledge of
|
hard to decide which parts should be put in the variant - knowledge of
|
other variants of the architecture is required.</P
|
other variants of the architecture is required.</P
|
><P
|
><P
|
>Looking at existing variant HALs (e.g., MIPS tx39, tx49) may be a
|
>Looking at existing variant HALs (e.g., MIPS tx39, tx49) may be a
|
help - usually things such as caching, interrupt and exception
|
help - usually things such as caching, interrupt and exception
|
handling differ between variants. Initialization code, and code for
|
handling differ between variants. Initialization code, and code for
|
handling various core components (FPU, DSP, MMU, etc.) may also differ
|
handling various core components (FPU, DSP, MMU, etc.) may also differ
|
or be missing altogether on some variants. Linker scripts may also require
|
or be missing altogether on some variants. Linker scripts may also require
|
specific variant versions.</P
|
specific variant versions.</P
|
><DIV
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><DIV
|
CLASS="NOTE"
|
CLASS="NOTE"
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><BLOCKQUOTE
|
><BLOCKQUOTE
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><P
|
><P
|
><B
|
><B
|
>Note: </B
|
>Note: </B
|
>Some CPU variants may require specific compiler
|
>Some CPU variants may require specific compiler
|
support. That support must be in place before you can undertake the
|
support. That support must be in place before you can undertake the
|
eCos variant port.</P
|
eCos variant port.</P
|
></BLOCKQUOTE
|
></BLOCKQUOTE
|
></DIV
|
></DIV
|
></DIV
|
></DIV
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><DIV
|
><DIV
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><H2
|
><H2
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><A
|
><A
|
NAME="AEN9752">HAL Variant CDL</H2
|
NAME="AEN9752">HAL Variant CDL</H2
|
><P
|
><P
|
>The CDL in a variant HAL tends to depend on the exact functionality
|
>The CDL in a variant HAL tends to depend on the exact functionality
|
supported by the variant. If it implements some of the devices
|
supported by the variant. If it implements some of the devices
|
described in the platform HAL, then the CDL for those will be here
|
described in the platform HAL, then the CDL for those will be here
|
rather than there (for example the real-time clock).</P
|
rather than there (for example the real-time clock).</P
|
><P
|
><P
|
>There may also be CDL to select options in the architecture HAL to
|
>There may also be CDL to select options in the architecture HAL to
|
configure it to a particular architectural variant.</P
|
configure it to a particular architectural variant.</P
|
><P
|
><P
|
>Each variant needs an entry in the <TT
|
>Each variant needs an entry in the <TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>ecos.db</TT
|
>ecos.db</TT
|
>
|
>
|
file. This is the one for the SH3:</P
|
file. This is the one for the SH3:</P
|
><TABLE
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><TABLE
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BORDER="5"
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BORDER="5"
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BGCOLOR="#E0E0F0"
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WIDTH="70%"
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WIDTH="70%"
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><TR
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><TR
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><TD
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><TD
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><PRE
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><PRE
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CLASS="PROGRAMLISTING"
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CLASS="PROGRAMLISTING"
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>package CYGPKG_HAL_SH_SH3 {
|
>package CYGPKG_HAL_SH_SH3 {
|
alias { "SH3 architecture" hal_sh_sh3 }
|
alias { "SH3 architecture" hal_sh_sh3 }
|
directory hal/sh/sh3
|
directory hal/sh/sh3
|
script hal_sh_sh3.cdl
|
script hal_sh_sh3.cdl
|
hardware
|
hardware
|
description "
|
description "
|
The SH3 (SuperH 3) variant HAL package provides generic
|
The SH3 (SuperH 3) variant HAL package provides generic
|
support for SH3 variant CPUs."
|
support for SH3 variant CPUs."
|
}</PRE
|
}</PRE
|
></TD
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></TD
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></TR
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></TR
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></TABLE
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></TABLE
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><P
|
><P
|
>As you can see, it is very similar to the platform entry.</P
|
>As you can see, it is very similar to the platform entry.</P
|
><P
|
><P
|
>The variant CDL file will contain a package entry named for the
|
>The variant CDL file will contain a package entry named for the
|
architecture and variant, matching the package name in the
|
architecture and variant, matching the package name in the
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>ecos.db</TT
|
>ecos.db</TT
|
> file. Here is the initial part of the
|
> file. Here is the initial part of the
|
MIPS VR4300 CDL file:</P
|
MIPS VR4300 CDL file:</P
|
><TABLE
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><TABLE
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BORDER="5"
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BORDER="5"
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BGCOLOR="#E0E0F0"
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BGCOLOR="#E0E0F0"
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WIDTH="70%"
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WIDTH="70%"
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><TR
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><TR
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><TD
|
><TD
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><PRE
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><PRE
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CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>cdl_package CYGPKG_HAL_MIPS_VR4300 {
|
>cdl_package CYGPKG_HAL_MIPS_VR4300 {
|
display "VR4300 variant"
|
display "VR4300 variant"
|
parent CYGPKG_HAL_MIPS
|
parent CYGPKG_HAL_MIPS
|
implements CYGINT_HAL_MIPS_VARIANT
|
implements CYGINT_HAL_MIPS_VARIANT
|
hardware
|
hardware
|
include_dir cyg/hal
|
include_dir cyg/hal
|
define_header hal_mips_vr4300.h
|
define_header hal_mips_vr4300.h
|
description "
|
description "
|
The VR4300 variant HAL package provides generic support
|
The VR4300 variant HAL package provides generic support
|
for this processor architecture. It is also necessary to
|
for this processor architecture. It is also necessary to
|
select a specific target platform HAL package."</PRE
|
select a specific target platform HAL package."</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>This defines the package, placing it under the MIPS architecture
|
>This defines the package, placing it under the MIPS architecture
|
package in the hierarchy. The <TT
|
package in the hierarchy. The <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>implements</TT
|
>implements</TT
|
> line
|
> line
|
indicates that this is a MIPS variant. The architecture package uses
|
indicates that this is a MIPS variant. The architecture package uses
|
this to check that exactly one variant is configured in.</P
|
this to check that exactly one variant is configured in.</P
|
><P
|
><P
|
>The variant defines some options that cause the architecture HAL to
|
>The variant defines some options that cause the architecture HAL to
|
configure itself to support this variant.</P
|
configure itself to support this variant.</P
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
> cdl_option CYGHWR_HAL_MIPS_64BIT {
|
> cdl_option CYGHWR_HAL_MIPS_64BIT {
|
display "Variant 64 bit architecture support"
|
display "Variant 64 bit architecture support"
|
calculated 1
|
calculated 1
|
}
|
}
|
|
|
cdl_option CYGHWR_HAL_MIPS_FPU {
|
cdl_option CYGHWR_HAL_MIPS_FPU {
|
display "Variant FPU support"
|
display "Variant FPU support"
|
calculated 1
|
calculated 1
|
}
|
}
|
|
|
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
|
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
|
display "Variant 64 bit FPU support"
|
display "Variant 64 bit FPU support"
|
calculated 1
|
calculated 1
|
}</PRE
|
}</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>These tell the architecture that this is a 64 bit MIPS architecture,
|
>These tell the architecture that this is a 64 bit MIPS architecture,
|
that it has a floating point unit, and that we are going to use it in
|
that it has a floating point unit, and that we are going to use it in
|
64 bit mode rather than 32 bit mode.</P
|
64 bit mode rather than 32 bit mode.</P
|
><P
|
><P
|
>The CDL file finishes off with some build options.</P
|
>The CDL file finishes off with some build options.</P
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
> define_proc {
|
> define_proc {
|
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
|
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
|
}
|
}
|
|
|
compile var_misc.c
|
compile var_misc.c
|
|
|
make {
|
make {
|
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_vr4300.ld
|
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_vr4300.ld
|
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
|
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
|
@echo $@ ": \\" > $(notdir $@).deps
|
@echo $@ ": \\" > $(notdir $@).deps
|
@tail +2 target.tmp >> $(notdir $@).deps
|
@tail +2 target.tmp >> $(notdir $@).deps
|
@echo >> $(notdir $@).deps
|
@echo >> $(notdir $@).deps
|
@rm target.tmp
|
@rm target.tmp
|
}
|
}
|
|
|
cdl_option CYGBLD_LINKER_SCRIPT {
|
cdl_option CYGBLD_LINKER_SCRIPT {
|
display "Linker script"
|
display "Linker script"
|
flavor data
|
flavor data
|
no_define
|
no_define
|
calculated { "src/mips_vr4300.ld" }
|
calculated { "src/mips_vr4300.ld" }
|
}
|
}
|
|
|
}</PRE
|
}</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>The <TT
|
>The <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>define_proc</TT
|
>define_proc</TT
|
> causes the architecture
|
> causes the architecture
|
configuration file to be included into the configuration file for the
|
configuration file to be included into the configuration file for the
|
variant. The <TT
|
variant. The <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>compile</TT
|
>compile</TT
|
> causes the single source file
|
> causes the single source file
|
for this variant, <TT
|
for this variant, <TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>var_misc.c</TT
|
>var_misc.c</TT
|
> to be compiled. The
|
> to be compiled. The
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>make</TT
|
>make</TT
|
> command emits makefile rules to combine the
|
> command emits makefile rules to combine the
|
linker script with the <TT
|
linker script with the <TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>.ldi</TT
|
>.ldi</TT
|
> file to generate
|
> file to generate
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>target.ld</TT
|
>target.ld</TT
|
>. Finally, in the MIPS HALs, the main
|
>. Finally, in the MIPS HALs, the main
|
linker script is defined in the variant, rather than the architecture,
|
linker script is defined in the variant, rather than the architecture,
|
so <TT
|
so <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>CYGBLD_LINKER_SCRIPT</TT
|
>CYGBLD_LINKER_SCRIPT</TT
|
> is defined here.</P
|
> is defined here.</P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><H2
|
><H2
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><A
|
><A
|
NAME="AEN9778">Cache Support</H2
|
NAME="AEN9778">Cache Support</H2
|
><P
|
><P
|
>The main area where the variant is likely to be involved is in cache
|
>The main area where the variant is likely to be involved is in cache
|
support. Often the only thing that distinguishes one CPU variant from
|
support. Often the only thing that distinguishes one CPU variant from
|
another is the size of its caches.</P
|
another is the size of its caches.</P
|
><P
|
><P
|
>In architectures such as the MIPS and PowerPC where cache instructions
|
>In architectures such as the MIPS and PowerPC where cache instructions
|
are part of the ISA, most of the actual cache operations are
|
are part of the ISA, most of the actual cache operations are
|
implemented in the architecture HAL. In this case the variant HAL only
|
implemented in the architecture HAL. In this case the variant HAL only
|
needs to define the cache dimensions. The following are the cache
|
needs to define the cache dimensions. The following are the cache
|
dimensions defined in the MIPS VR4300 variant
|
dimensions defined in the MIPS VR4300 variant
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>var_cache.h</TT
|
>var_cache.h</TT
|
>.</P
|
>.</P
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>// Data cache
|
>// Data cache
|
#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
|
#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
|
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
|
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
|
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
|
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
|
|
|
// Instruction cache
|
// Instruction cache
|
#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
|
#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
|
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
|
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
|
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
|
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
|
|
|
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
|
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
|
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))</PRE
|
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><P
|
><P
|
>Additional cache macros, or overrides for the defaults, may also
|
>Additional cache macros, or overrides for the defaults, may also
|
appear in here. While some architectures have instructions for
|
appear in here. While some architectures have instructions for
|
managing cache lines, overall enable/disable operations may be handled
|
managing cache lines, overall enable/disable operations may be handled
|
via variant specific registers. If so then
|
via variant specific registers. If so then
|
<TT
|
<TT
|
CLASS="FILENAME"
|
CLASS="FILENAME"
|
>var_cache.h</TT
|
>var_cache.h</TT
|
> should also define the
|
> should also define the
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>HAL_XCACHE_ENABLE()</TT
|
>HAL_XCACHE_ENABLE()</TT
|
> and
|
> and
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>HAL_XCACHE_DISABLE()</TT
|
>HAL_XCACHE_DISABLE()</TT
|
> macros.</P
|
> macros.</P
|
><P
|
><P
|
>If there are any generic features that the variant does not support
|
>If there are any generic features that the variant does not support
|
(cache locking is a typical example) then
|
(cache locking is a typical example) then
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>var_cache.h</TT
|
>var_cache.h</TT
|
> may need to disable definitions of
|
> may need to disable definitions of
|
certain operations. It is architecture dependent exactly how this is
|
certain operations. It is architecture dependent exactly how this is
|
done.</P
|
done.</P
|
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