<!-- Copyright (C) 2003 Red Hat, Inc. -->
|
<!-- Copyright (C) 2003 Red Hat, Inc. -->
|
<!-- This material may be distributed only subject to the terms -->
|
<!-- This material may be distributed only subject to the terms -->
|
<!-- and conditions set forth in the Open Publication License, v1.0 -->
|
<!-- and conditions set forth in the Open Publication License, v1.0 -->
|
<!-- or later (the latest version is presently available at -->
|
<!-- or later (the latest version is presently available at -->
|
<!-- http://www.opencontent.org/openpub/). -->
|
<!-- http://www.opencontent.org/openpub/). -->
|
<!-- Distribution of the work or derivative of the work in any -->
|
<!-- Distribution of the work or derivative of the work in any -->
|
<!-- standard (paper) book form is prohibited unless prior -->
|
<!-- standard (paper) book form is prohibited unless prior -->
|
<!-- permission is obtained from the copyright holder. -->
|
<!-- permission is obtained from the copyright holder. -->
|
<HTML
|
<HTML
|
><HEAD
|
><HEAD
|
><TITLE
|
><TITLE
|
>Vectors and VSRs</TITLE
|
>Vectors and VSRs</TITLE
|
><meta name="MSSmartTagsPreventParsing" content="TRUE">
|
><meta name="MSSmartTagsPreventParsing" content="TRUE">
|
<META
|
<META
|
NAME="GENERATOR"
|
NAME="GENERATOR"
|
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
|
CONTENT="Modular DocBook HTML Stylesheet Version 1.76b+
|
"><LINK
|
"><LINK
|
REL="HOME"
|
REL="HOME"
|
TITLE="eCos Reference Manual"
|
TITLE="eCos Reference Manual"
|
HREF="ecos-ref.html"><LINK
|
HREF="ecos-ref.html"><LINK
|
REL="UP"
|
REL="UP"
|
TITLE="Exception Handling"
|
TITLE="Exception Handling"
|
HREF="hal-exception-handling.html"><LINK
|
HREF="hal-exception-handling.html"><LINK
|
REL="PREVIOUS"
|
REL="PREVIOUS"
|
TITLE="Exception Handling"
|
TITLE="Exception Handling"
|
HREF="hal-exception-handling.html"><LINK
|
HREF="hal-exception-handling.html"><LINK
|
REL="NEXT"
|
REL="NEXT"
|
TITLE="Default Synchronous Exception Handling"
|
TITLE="Default Synchronous Exception Handling"
|
HREF="hal-default-synchronous-exception-handling.html"></HEAD
|
HREF="hal-default-synchronous-exception-handling.html"></HEAD
|
><BODY
|
><BODY
|
CLASS="SECTION"
|
CLASS="SECTION"
|
BGCOLOR="#FFFFFF"
|
BGCOLOR="#FFFFFF"
|
TEXT="#000000"
|
TEXT="#000000"
|
LINK="#0000FF"
|
LINK="#0000FF"
|
VLINK="#840084"
|
VLINK="#840084"
|
ALINK="#0000FF"
|
ALINK="#0000FF"
|
><DIV
|
><DIV
|
CLASS="NAVHEADER"
|
CLASS="NAVHEADER"
|
><TABLE
|
><TABLE
|
SUMMARY="Header navigation table"
|
SUMMARY="Header navigation table"
|
WIDTH="100%"
|
WIDTH="100%"
|
BORDER="0"
|
BORDER="0"
|
CELLPADDING="0"
|
CELLPADDING="0"
|
CELLSPACING="0"
|
CELLSPACING="0"
|
><TR
|
><TR
|
><TH
|
><TH
|
COLSPAN="3"
|
COLSPAN="3"
|
ALIGN="center"
|
ALIGN="center"
|
>eCos Reference Manual</TH
|
>eCos Reference Manual</TH
|
></TR
|
></TR
|
><TR
|
><TR
|
><TD
|
><TD
|
WIDTH="10%"
|
WIDTH="10%"
|
ALIGN="left"
|
ALIGN="left"
|
VALIGN="bottom"
|
VALIGN="bottom"
|
><A
|
><A
|
HREF="hal-exception-handling.html"
|
HREF="hal-exception-handling.html"
|
ACCESSKEY="P"
|
ACCESSKEY="P"
|
>Prev</A
|
>Prev</A
|
></TD
|
></TD
|
><TD
|
><TD
|
WIDTH="80%"
|
WIDTH="80%"
|
ALIGN="center"
|
ALIGN="center"
|
VALIGN="bottom"
|
VALIGN="bottom"
|
>Chapter 10. Exception Handling</TD
|
>Chapter 10. Exception Handling</TD
|
><TD
|
><TD
|
WIDTH="10%"
|
WIDTH="10%"
|
ALIGN="right"
|
ALIGN="right"
|
VALIGN="bottom"
|
VALIGN="bottom"
|
><A
|
><A
|
HREF="hal-default-synchronous-exception-handling.html"
|
HREF="hal-default-synchronous-exception-handling.html"
|
ACCESSKEY="N"
|
ACCESSKEY="N"
|
>Next</A
|
>Next</A
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
><HR
|
><HR
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
WIDTH="100%"></DIV
|
WIDTH="100%"></DIV
|
><DIV
|
><DIV
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><H1
|
><H1
|
CLASS="SECTION"
|
CLASS="SECTION"
|
><A
|
><A
|
NAME="HAL-VECTORS-AND-VSRS">Vectors and VSRs</H1
|
NAME="HAL-VECTORS-AND-VSRS">Vectors and VSRs</H1
|
><P
|
><P
|
>The CPU delivers all exceptions, whether
|
>The CPU delivers all exceptions, whether
|
synchronous faults or asynchronous interrupts, to a set of hardware
|
synchronous faults or asynchronous interrupts, to a set of hardware
|
defined vectors. Depending on the architecture, these may be
|
defined vectors. Depending on the architecture, these may be
|
implemented in a number of different ways. Examples of existing
|
implemented in a number of different ways. Examples of existing
|
mechanisms are:</P
|
mechanisms are:</P
|
><P
|
><P
|
></P
|
></P
|
><DIV
|
><DIV
|
CLASS="VARIABLELIST"
|
CLASS="VARIABLELIST"
|
><DL
|
><DL
|
><DT
|
><DT
|
>PowerPC</DT
|
>PowerPC</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Exceptions are vectored to locations 256 bytes apart starting at
|
> Exceptions are vectored to locations 256 bytes apart starting at
|
either zero or <TT
|
either zero or <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>0xFFF00000</TT
|
>0xFFF00000</TT
|
>. There are 16 such
|
>. There are 16 such
|
vectors defined by the basic architecture and extra vectors may
|
vectors defined by the basic architecture and extra vectors may
|
be defined by specific variants. One of the base vectors is for
|
be defined by specific variants. One of the base vectors is for
|
all external interrupts, and another is for the architecture
|
all external interrupts, and another is for the architecture
|
defined timer.
|
defined timer.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>MIPS</DT
|
>MIPS</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Most exceptions and all interrupts are vectored to a single
|
> Most exceptions and all interrupts are vectored to a single
|
address at either <TT
|
address at either <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>0x80000000</TT
|
>0x80000000</TT
|
> or
|
> or
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>0xBFC00180</TT
|
>0xBFC00180</TT
|
>. Software is responsible for
|
>. Software is responsible for
|
reading the exception code from the CPU <TT
|
reading the exception code from the CPU <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>cause</TT
|
>cause</TT
|
>
|
>
|
register to discover its true source. Some TLB and debug
|
register to discover its true source. Some TLB and debug
|
exceptions are delivered to different vector addresses, but
|
exceptions are delivered to different vector addresses, but
|
these are not used currently by eCos. One of the exception codes
|
these are not used currently by eCos. One of the exception codes
|
in the <TT
|
in the <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>cause</TT
|
>cause</TT
|
> register indicates an external
|
> register indicates an external
|
interrupt. Additional bits in the <TT
|
interrupt. Additional bits in the <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>cause</TT
|
>cause</TT
|
>
|
>
|
register provide a first-level decode for the interrupt source,
|
register provide a first-level decode for the interrupt source,
|
one of which represents an architecture defined timer.
|
one of which represents an architecture defined timer.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>IA32</DT
|
>IA32</DT
|
><DD
|
><DD
|
><P
|
><P
|
> Exceptions are delivered via an Interrupt Descriptor Table (IDT)
|
> Exceptions are delivered via an Interrupt Descriptor Table (IDT)
|
which is essentially an indirection table indexed by exception
|
which is essentially an indirection table indexed by exception
|
number. The IDT may be placed anywhere in memory. In PC hardware
|
number. The IDT may be placed anywhere in memory. In PC hardware
|
the standard interrupt controller can be programmed to deliver
|
the standard interrupt controller can be programmed to deliver
|
the external interrupts to a block of 16 vectors at any offset
|
the external interrupts to a block of 16 vectors at any offset
|
in the IDT. There is no hardware supplied mechanism for
|
in the IDT. There is no hardware supplied mechanism for
|
determining the vector taken, other than from the address jumped
|
determining the vector taken, other than from the address jumped
|
to.
|
to.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>ARM</DT
|
>ARM</DT
|
><DD
|
><DD
|
><P
|
><P
|
> All exceptions, including the FIQ and IRQ interrupts, are
|
> All exceptions, including the FIQ and IRQ interrupts, are
|
vectored to locations four bytes apart starting at zero. There
|
vectored to locations four bytes apart starting at zero. There
|
is only room for one instruction here, which must immediately
|
is only room for one instruction here, which must immediately
|
jump out to handling code higher in memory. Interrupt sources
|
jump out to handling code higher in memory. Interrupt sources
|
have to be decoded entirely from the interrupt controller.
|
have to be decoded entirely from the interrupt controller.
|
</P
|
</P
|
></DD
|
></DD
|
></DL
|
></DL
|
></DIV
|
></DIV
|
><P
|
><P
|
>With such a wide variety of hardware approaches, it is not possible to
|
>With such a wide variety of hardware approaches, it is not possible to
|
provide a generic mechanism for the substitution of exception vectors
|
provide a generic mechanism for the substitution of exception vectors
|
directly. Therefore, eCos translates all of these mechanisms in to a
|
directly. Therefore, eCos translates all of these mechanisms in to a
|
common approach that can be used by portable code on all platforms.</P
|
common approach that can be used by portable code on all platforms.</P
|
><P
|
><P
|
>The mechanism implemented is to attach to each hardware vector a short
|
>The mechanism implemented is to attach to each hardware vector a short
|
piece of trampoline code that makes an indirect jump via a table to
|
piece of trampoline code that makes an indirect jump via a table to
|
the actual handler for the exception. This handler is called the
|
the actual handler for the exception. This handler is called the
|
Vector Service Routine (VSR) and the table is called the VSR table.</P
|
Vector Service Routine (VSR) and the table is called the VSR table.</P
|
><P
|
><P
|
>The trampoline code performs the absolute minimum processing necessary
|
>The trampoline code performs the absolute minimum processing necessary
|
to identify the exception source, and jump to the VSR. The VSR is then
|
to identify the exception source, and jump to the VSR. The VSR is then
|
responsible for saving the CPU state and taking the necessary actions
|
responsible for saving the CPU state and taking the necessary actions
|
to handle the exception or interrupt. The entry conditions for the VSR
|
to handle the exception or interrupt. The entry conditions for the VSR
|
are as close to the raw hardware exception entry state as possible -
|
are as close to the raw hardware exception entry state as possible -
|
although on some platforms the trampoline will have had to move or
|
although on some platforms the trampoline will have had to move or
|
reorganize some registers to do its job.</P
|
reorganize some registers to do its job.</P
|
><P
|
><P
|
>To make this more concrete, consider how the trampoline code operates
|
>To make this more concrete, consider how the trampoline code operates
|
in each of the architectures described above:</P
|
in each of the architectures described above:</P
|
><P
|
><P
|
></P
|
></P
|
><DIV
|
><DIV
|
CLASS="VARIABLELIST"
|
CLASS="VARIABLELIST"
|
><DL
|
><DL
|
><DT
|
><DT
|
>PowerPC</DT
|
>PowerPC</DT
|
><DD
|
><DD
|
><P
|
><P
|
> A separate trampoline is contained in each of the vector
|
> A separate trampoline is contained in each of the vector
|
locations. This code saves a few work registers away to the
|
locations. This code saves a few work registers away to the
|
special purposes registers available, loads the exception number
|
special purposes registers available, loads the exception number
|
into a register and then uses that to index the VSR table and
|
into a register and then uses that to index the VSR table and
|
jump to the VSR. The VSR is entered with some registers move to
|
jump to the VSR. The VSR is entered with some registers move to
|
the SPRs, and one of the data register containing the number of
|
the SPRs, and one of the data register containing the number of
|
the vector taken.
|
the vector taken.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>MIPS</DT
|
>MIPS</DT
|
><DD
|
><DD
|
><P
|
><P
|
> A single trampoline routine attached to the common vector reads
|
> A single trampoline routine attached to the common vector reads
|
the exception code out of the <TT
|
the exception code out of the <TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>cause</TT
|
>cause</TT
|
> register
|
> register
|
and uses that value to index the VSR table and jump to the VSR.
|
and uses that value to index the VSR table and jump to the VSR.
|
The trampoline uses the two registers defined in the ABI for
|
The trampoline uses the two registers defined in the ABI for
|
kernel use to do this, one of these will contain the exception
|
kernel use to do this, one of these will contain the exception
|
vector number for the VSR.
|
vector number for the VSR.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>IA32</DT
|
>IA32</DT
|
><DD
|
><DD
|
><P
|
><P
|
> There is a separate 3 or 4 instruction trampoline pointed to by
|
> There is a separate 3 or 4 instruction trampoline pointed to by
|
each active IDT table entry. The trampoline for exceptions that
|
each active IDT table entry. The trampoline for exceptions that
|
also have an error code pop it from the stack and put it into a
|
also have an error code pop it from the stack and put it into a
|
memory location. Trampolines for non-error-code exceptions just
|
memory location. Trampolines for non-error-code exceptions just
|
zero the memory location. Then all trampolines push an
|
zero the memory location. Then all trampolines push an
|
interrupt/exception number onto the stack, and take an indirect
|
interrupt/exception number onto the stack, and take an indirect
|
jump through a precalculated offset in the VSR table. This is
|
jump through a precalculated offset in the VSR table. This is
|
all done without saving any registers, using memory-only
|
all done without saving any registers, using memory-only
|
operations. The VSR is entered with the vector number pushed
|
operations. The VSR is entered with the vector number pushed
|
onto the stack on top of the standard hardware saved state.
|
onto the stack on top of the standard hardware saved state.
|
</P
|
</P
|
></DD
|
></DD
|
><DT
|
><DT
|
>ARM</DT
|
>ARM</DT
|
><DD
|
><DD
|
><P
|
><P
|
> The trampoline consists solely of the single instruction at the
|
> The trampoline consists solely of the single instruction at the
|
exception entry point. This is an indirect jump via a location
|
exception entry point. This is an indirect jump via a location
|
32 bytes higher in memory. These locations, from
|
32 bytes higher in memory. These locations, from
|
<TT
|
<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>0x20</TT
|
>0x20</TT
|
> up, form the VSR table. Since each VSR
|
> up, form the VSR table. Since each VSR
|
is entered in a different CPU mode
|
is entered in a different CPU mode
|
(<TT
|
(<TT
|
CLASS="LITERAL"
|
CLASS="LITERAL"
|
>SVC,UNDEF,ABORT,IRQ or FIQ</TT
|
>SVC,UNDEF,ABORT,IRQ or FIQ</TT
|
>) there has to be a
|
>) there has to be a
|
different VSR for each exception that knows how to save the CPU
|
different VSR for each exception that knows how to save the CPU
|
state correctly.
|
state correctly.
|
</P
|
</P
|
></DD
|
></DD
|
></DL
|
></DL
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="NAVFOOTER"
|
CLASS="NAVFOOTER"
|
><HR
|
><HR
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
WIDTH="100%"><TABLE
|
WIDTH="100%"><TABLE
|
SUMMARY="Footer navigation table"
|
SUMMARY="Footer navigation table"
|
WIDTH="100%"
|
WIDTH="100%"
|
BORDER="0"
|
BORDER="0"
|
CELLPADDING="0"
|
CELLPADDING="0"
|
CELLSPACING="0"
|
CELLSPACING="0"
|
><TR
|
><TR
|
><TD
|
><TD
|
WIDTH="33%"
|
WIDTH="33%"
|
ALIGN="left"
|
ALIGN="left"
|
VALIGN="top"
|
VALIGN="top"
|
><A
|
><A
|
HREF="hal-exception-handling.html"
|
HREF="hal-exception-handling.html"
|
ACCESSKEY="P"
|
ACCESSKEY="P"
|
>Prev</A
|
>Prev</A
|
></TD
|
></TD
|
><TD
|
><TD
|
WIDTH="34%"
|
WIDTH="34%"
|
ALIGN="center"
|
ALIGN="center"
|
VALIGN="top"
|
VALIGN="top"
|
><A
|
><A
|
HREF="ecos-ref.html"
|
HREF="ecos-ref.html"
|
ACCESSKEY="H"
|
ACCESSKEY="H"
|
>Home</A
|
>Home</A
|
></TD
|
></TD
|
><TD
|
><TD
|
WIDTH="33%"
|
WIDTH="33%"
|
ALIGN="right"
|
ALIGN="right"
|
VALIGN="top"
|
VALIGN="top"
|
><A
|
><A
|
HREF="hal-default-synchronous-exception-handling.html"
|
HREF="hal-default-synchronous-exception-handling.html"
|
ACCESSKEY="N"
|
ACCESSKEY="N"
|
>Next</A
|
>Next</A
|
></TD
|
></TD
|
></TR
|
></TR
|
><TR
|
><TR
|
><TD
|
><TD
|
WIDTH="33%"
|
WIDTH="33%"
|
ALIGN="left"
|
ALIGN="left"
|
VALIGN="top"
|
VALIGN="top"
|
>Exception Handling</TD
|
>Exception Handling</TD
|
><TD
|
><TD
|
WIDTH="34%"
|
WIDTH="34%"
|
ALIGN="center"
|
ALIGN="center"
|
VALIGN="top"
|
VALIGN="top"
|
><A
|
><A
|
HREF="hal-exception-handling.html"
|
HREF="hal-exception-handling.html"
|
ACCESSKEY="U"
|
ACCESSKEY="U"
|
>Up</A
|
>Up</A
|
></TD
|
></TD
|
><TD
|
><TD
|
WIDTH="33%"
|
WIDTH="33%"
|
ALIGN="right"
|
ALIGN="right"
|
VALIGN="top"
|
VALIGN="top"
|
>Default Synchronous Exception Handling</TD
|
>Default Synchronous Exception Handling</TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
></DIV
|
></DIV
|
></BODY
|
></BODY
|
></HTML
|
></HTML
|
|
|
