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>Chapter 5. Installation and Testing</TD
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>Chapter 5. Installation and Testing</TD
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><TD
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><TD
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WIDTH="10%"
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WIDTH="10%"
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ALIGN="right"
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WIDTH="100%"></DIV
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WIDTH="100%"></DIV
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><DIV
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><DIV
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CLASS="SECT1"
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CLASS="SECT1"
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><H1
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><H1
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CLASS="SECT1"
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CLASS="SECT1"
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><A
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><A
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NAME="IQ80310">ARM/Xscale Cyclone IQ80310</H1
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NAME="IQ80310">ARM/Xscale Cyclone IQ80310</H1
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><DIV
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><DIV
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CLASS="SECT2"
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CLASS="SECT2"
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><H2
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><H2
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CLASS="SECT2"
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CLASS="SECT2"
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><A
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><A
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NAME="AEN6164">Overview</H2
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NAME="AEN6164">Overview</H2
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><P
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><P
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>RedBoot supports
|
>RedBoot supports
|
both serial ports and the built-in ethernet port for communication and downloads.
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both serial ports and the built-in ethernet port for communication and downloads.
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The default serial port settings are 115200,8,N,1. RedBoot also supports flash
|
The default serial port settings are 115200,8,N,1. RedBoot also supports flash
|
management for the onboard 8MB flash.</P
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management for the onboard 8MB flash.</P
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><P
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><P
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>The following RedBoot configurations are supported:
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>The following RedBoot configurations are supported:
|
|
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<DIV
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<DIV
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CLASS="INFORMALTABLE"
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CLASS="INFORMALTABLE"
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><A
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><A
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NAME="AEN6174"><P
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NAME="AEN6174"><P
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></P
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></P
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><TABLE
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><TABLE
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BORDER="1"
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BORDER="1"
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CLASS="CALSTABLE"
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CLASS="CALSTABLE"
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><THEAD
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><THEAD
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><TR
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><TR
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><TH
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><TH
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ALIGN="LEFT"
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ALIGN="LEFT"
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VALIGN="TOP"
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VALIGN="TOP"
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>Configuration</TH
|
>Configuration</TH
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><TH
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><TH
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ALIGN="LEFT"
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ALIGN="LEFT"
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VALIGN="TOP"
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VALIGN="TOP"
|
>Mode</TH
|
>Mode</TH
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><TH
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><TH
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ALIGN="LEFT"
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ALIGN="LEFT"
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VALIGN="TOP"
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VALIGN="TOP"
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>Description</TH
|
>Description</TH
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><TH
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><TH
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ALIGN="LEFT"
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ALIGN="LEFT"
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VALIGN="TOP"
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VALIGN="TOP"
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>File</TH
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>File</TH
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></TR
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></TR
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></THEAD
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></THEAD
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><TBODY
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><TBODY
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><TR
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><TR
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><TD
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><TD
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ALIGN="LEFT"
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ALIGN="LEFT"
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VALIGN="TOP"
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VALIGN="TOP"
|
>ROM</TD
|
>ROM</TD
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><TD
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><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>[ROM]</TD
|
>[ROM]</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>RedBoot running from the board's flash boot
|
>RedBoot running from the board's flash boot
|
sector.</TD
|
sector.</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>redboot_ROM.ecm</TD
|
>redboot_ROM.ecm</TD
|
></TR
|
></TR
|
><TR
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><TR
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>RAM</TD
|
>RAM</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>[RAM]</TD
|
>[RAM]</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>RedBoot running from RAM with RedBoot in the
|
>RedBoot running from RAM with RedBoot in the
|
flash boot sector.</TD
|
flash boot sector.</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>redboot_RAM.ecm</TD
|
>redboot_RAM.ecm</TD
|
></TR
|
></TR
|
><TR
|
><TR
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>ROMA</TD
|
>ROMA</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>[ROM]</TD
|
>[ROM]</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>RedBoot running from flash address 0x40000, with
|
>RedBoot running from flash address 0x40000, with
|
ARM bootloader in flash boot sector.</TD
|
ARM bootloader in flash boot sector.</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>redboot_ROMA.ecm</TD
|
>redboot_ROMA.ecm</TD
|
></TR
|
></TR
|
><TR
|
><TR
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>RAMA</TD
|
>RAMA</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>[RAM]</TD
|
>[RAM]</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>RedBoot running from RAM with ARM bootloader in
|
>RedBoot running from RAM with ARM bootloader in
|
flash boot sector.</TD
|
flash boot sector.</TD
|
><TD
|
><TD
|
ALIGN="LEFT"
|
ALIGN="LEFT"
|
VALIGN="TOP"
|
VALIGN="TOP"
|
>redboot_RAMA.ecm</TD
|
>redboot_RAMA.ecm</TD
|
></TR
|
></TR
|
></TBODY
|
></TBODY
|
></TABLE
|
></TABLE
|
><P
|
><P
|
></P
|
></P
|
></DIV
|
></DIV
|
></P
|
></P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6203">Initial Installation Method</H2
|
NAME="AEN6203">Initial Installation Method</H2
|
><P
|
><P
|
>The board manufacturer provides a DOS application which is
|
>The board manufacturer provides a DOS application which is
|
capable of programming the flash over the PCI bus, and this is
|
capable of programming the flash over the PCI bus, and this is
|
required for initial installations of RedBoot. Please see the board
|
required for initial installations of RedBoot. Please see the board
|
manual for information on using this utility. In general, the process
|
manual for information on using this utility. In general, the process
|
involves programming one of the two flash based RedBoot images to
|
involves programming one of the two flash based RedBoot images to
|
flash. The ROM mode RedBoot (which runs from the flash boot sector)
|
flash. The ROM mode RedBoot (which runs from the flash boot sector)
|
should be programmed to flash address 0x00000000. The ROMA RedBoot
|
should be programmed to flash address 0x00000000. The ROMA RedBoot
|
mode (which is started by the ARM bootloader) should be programmed to
|
mode (which is started by the ARM bootloader) should be programmed to
|
flash address 0x00004000.</P
|
flash address 0x00004000.</P
|
><P
|
><P
|
> To install RedBoot to run from the flash boot sector, use the manufacturer's
|
> To install RedBoot to run from the flash boot sector, use the manufacturer's
|
flash utility to install the ROM mode image at address zero.</P
|
flash utility to install the ROM mode image at address zero.</P
|
><P
|
><P
|
>To install RedBoot to run from address 0x40000 with the ARM bootloader
|
>To install RedBoot to run from address 0x40000 with the ARM bootloader
|
in the flash boot sector, use the manufacturer's flash utility to install
|
in the flash boot sector, use the manufacturer's flash utility to install
|
the ROMA mode image at address 0x40000. </P
|
the ROMA mode image at address 0x40000. </P
|
><P
|
><P
|
>After booting the initial installation of RedBoot, this warning may
|
>After booting the initial installation of RedBoot, this warning may
|
be printed: <TABLE
|
be printed: <TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="SCREEN"
|
CLASS="SCREEN"
|
>flash configuration checksum error or invalid key</PRE
|
>flash configuration checksum error or invalid key</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
>This is normal, and indicates that the flash must be configured
|
>This is normal, and indicates that the flash must be configured
|
for use by RedBoot. Even if the above message is not printed, it may be a
|
for use by RedBoot. Even if the above message is not printed, it may be a
|
good idea to reinitialize the flash anyway. Do this with the <B
|
good idea to reinitialize the flash anyway. Do this with the <B
|
CLASS="COMMAND"
|
CLASS="COMMAND"
|
>fis</B
|
>fis</B
|
> command: <TABLE
|
> command: <TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="SCREEN"
|
CLASS="SCREEN"
|
>RedBoot> <TT
|
>RedBoot> <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>fis init</B
|
>fis init</B
|
></TT
|
></TT
|
>
|
>
|
About to initialize [format] flash image system - continue (y/n)? <TT
|
About to initialize [format] flash image system - continue (y/n)? <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>y</B
|
>y</B
|
></TT
|
></TT
|
>
|
>
|
*** Initialize flash Image System
|
*** Initialize flash Image System
|
Warning: device contents not erased, some blocks may not be usable
|
Warning: device contents not erased, some blocks may not be usable
|
... Unlock from 0x007e0000-0x00800000: .
|
... Unlock from 0x007e0000-0x00800000: .
|
... Erase from 0x007e0000-0x00800000: .
|
... Erase from 0x007e0000-0x00800000: .
|
... Program from 0xa1fd0000-0xa1fd0400 at 0x007e0000: .
|
... Program from 0xa1fd0000-0xa1fd0400 at 0x007e0000: .
|
... Lock from 0x007e0000-0x00800000: .
|
... Lock from 0x007e0000-0x00800000: .
|
Followed by the fconfig command:
|
Followed by the fconfig command:
|
RedBoot> <TT
|
RedBoot> <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>fconfig</B
|
>fconfig</B
|
></TT
|
></TT
|
>
|
>
|
Run script at boot: <TT
|
Run script at boot: <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>false</B
|
>false</B
|
></TT
|
></TT
|
>
|
>
|
Use BOOTP for network configuration: <TT
|
Use BOOTP for network configuration: <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>false</B
|
>false</B
|
></TT
|
></TT
|
>
|
>
|
Local IP address: <TT
|
Local IP address: <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>192.168.1.153</B
|
>192.168.1.153</B
|
></TT
|
></TT
|
>
|
>
|
Default server IP address: <TT
|
Default server IP address: <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>192.168.1.10</B
|
>192.168.1.10</B
|
></TT
|
></TT
|
>
|
>
|
GDB connection port: <TT
|
GDB connection port: <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>1000</B
|
>1000</B
|
></TT
|
></TT
|
>
|
>
|
Network debug at boot time: <TT
|
Network debug at boot time: <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>false</B
|
>false</B
|
></TT
|
></TT
|
>
|
>
|
Update RedBoot non-volatile configuration - continue (y/n)? <TT
|
Update RedBoot non-volatile configuration - continue (y/n)? <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>y</B
|
>y</B
|
></TT
|
></TT
|
>
|
>
|
... Unlock from 0x007c0000-0x007e0000: .
|
... Unlock from 0x007c0000-0x007e0000: .
|
... Erase from 0x007c0000-0x007e0000: .
|
... Erase from 0x007c0000-0x007e0000: .
|
... Program from 0xa0013018-0xa0013418 at 0x007c0000: .
|
... Program from 0xa0013018-0xa0013418 at 0x007c0000: .
|
... Lock from 0x007c0000-0x007e0000: .</PRE
|
... Lock from 0x007c0000-0x007e0000: .</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
></P
|
></P
|
><DIV
|
><DIV
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><BLOCKQUOTE
|
><BLOCKQUOTE
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><P
|
><P
|
><B
|
><B
|
>Note: </B
|
>Note: </B
|
>When later updating RedBoot in situ, it is important to
|
>When later updating RedBoot in situ, it is important to
|
use a matching ROM and RAM mode pair of images. So use either RAM/ROM
|
use a matching ROM and RAM mode pair of images. So use either RAM/ROM
|
or RAMA/ROMA images. Do not mix them.</P
|
or RAMA/ROMA images. Do not mix them.</P
|
></BLOCKQUOTE
|
></BLOCKQUOTE
|
></DIV
|
></DIV
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6224">Error codes</H2
|
NAME="AEN6224">Error codes</H2
|
><P
|
><P
|
>RedBoot uses the two digit LED display to indicate errors during board
|
>RedBoot uses the two digit LED display to indicate errors during board
|
initialization. Possible error codes are: <P
|
initialization. Possible error codes are: <P
|
CLASS="LITERALLAYOUT"
|
CLASS="LITERALLAYOUT"
|
>88 - Unknown Error<br>
|
>88 - Unknown Error<br>
|
55 - I2C Error<br>
|
55 - I2C Error<br>
|
FF - SDRAM Error<br>
|
FF - SDRAM Error<br>
|
01 - No Error</P
|
01 - No Error</P
|
></P
|
></P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6228">Using RedBoot with ARM Bootloader</H2
|
NAME="AEN6228">Using RedBoot with ARM Bootloader</H2
|
><P
|
><P
|
>RedBoot can coexist with ARM tools in flash on the IQ80310 board. In
|
>RedBoot can coexist with ARM tools in flash on the IQ80310 board. In
|
this configuration, the ARM bootloader will occupy the flash boot sector while
|
this configuration, the ARM bootloader will occupy the flash boot sector while
|
RedBoot is located at flash address 0x40000. The sixteen position rotary switch
|
RedBoot is located at flash address 0x40000. The sixteen position rotary switch
|
is used to tell the ARM bootloader to jump to the RedBoot image located at
|
is used to tell the ARM bootloader to jump to the RedBoot image located at
|
address 0x40000. RedBoot is selected by switch position 0 or 1. Other switch
|
address 0x40000. RedBoot is selected by switch position 0 or 1. Other switch
|
positions are used by the ARM firmware and RedBoot will not be started. </P
|
positions are used by the ARM firmware and RedBoot will not be started. </P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6231">Special RedBoot Commands</H2
|
NAME="AEN6231">Special RedBoot Commands</H2
|
><P
|
><P
|
>A special RedBoot command, <B
|
>A special RedBoot command, <B
|
CLASS="COMMAND"
|
CLASS="COMMAND"
|
>diag</B
|
>diag</B
|
>, is used to
|
>, is used to
|
access a set of hardware diagnostics provided by the board
|
access a set of hardware diagnostics provided by the board
|
manufacturer. To access the diagnostic menu, enter diag at the RedBoot prompt:
|
manufacturer. To access the diagnostic menu, enter diag at the RedBoot prompt:
|
<TABLE
|
<TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="SCREEN"
|
CLASS="SCREEN"
|
>RedBoot> <TT
|
>RedBoot> <TT
|
CLASS="USERINPUT"
|
CLASS="USERINPUT"
|
><B
|
><B
|
>diag</B
|
>diag</B
|
></TT
|
></TT
|
>
|
>
|
Entering Hardware Diagnostics - Disabling Data Cache!
|
Entering Hardware Diagnostics - Disabling Data Cache!
|
1 - Memory Tests
|
1 - Memory Tests
|
2 - Repeating Memory Tests
|
2 - Repeating Memory Tests
|
3 - 16C552 DUART Serial Port Tests
|
3 - 16C552 DUART Serial Port Tests
|
4 - Rotary Switch S1 Test for positions 0-3
|
4 - Rotary Switch S1 Test for positions 0-3
|
5 - seven Segment LED Tests
|
5 - seven Segment LED Tests
|
6 - Backplane Detection Test
|
6 - Backplane Detection Test
|
7 - Battery Status Test
|
7 - Battery Status Test
|
8 - External Timer Test
|
8 - External Timer Test
|
9 - i82559 Ethernet Configuration
|
9 - i82559 Ethernet Configuration
|
10 - i82559 Ethernet Test
|
10 - i82559 Ethernet Test
|
11 - Secondary PCI Bus Test
|
11 - Secondary PCI Bus Test
|
12 - Primary PCI Bus Test
|
12 - Primary PCI Bus Test
|
13 - i960Rx/303 PCI Interrupt Test
|
13 - i960Rx/303 PCI Interrupt Test
|
14 - Internal Timer Test
|
14 - Internal Timer Test
|
15 - GPIO Test
|
15 - GPIO Test
|
0 - quit Enter the menu item number (0 to quit):</PRE
|
0 - quit Enter the menu item number (0 to quit):</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
>
|
>
|
Tests for various hardware subsystems are provided, and some
|
Tests for various hardware subsystems are provided, and some
|
tests require special hardware in order to execute normally. The Ethernet
|
tests require special hardware in order to execute normally. The Ethernet
|
Configuration item may be used to set the board ethernet address.</P
|
Configuration item may be used to set the board ethernet address.</P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6237">IQ80310 Hardware Tests</H2
|
NAME="AEN6237">IQ80310 Hardware Tests</H2
|
><P
|
><P
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="SCREEN"
|
CLASS="SCREEN"
|
>1 - Memory Tests
|
>1 - Memory Tests
|
2 - Repeating Memory Tests
|
2 - Repeating Memory Tests
|
3 - 16C552 DUART Serial Port Tests
|
3 - 16C552 DUART Serial Port Tests
|
4 - Rotary Switch S1 Test for positions 0-3
|
4 - Rotary Switch S1 Test for positions 0-3
|
5 - 7 Segment LED Tests
|
5 - 7 Segment LED Tests
|
6 - Backplane Detection Test
|
6 - Backplane Detection Test
|
7 - Battery Status Test
|
7 - Battery Status Test
|
8 - External Timer Test
|
8 - External Timer Test
|
9 - i82559 Ethernet Configuration
|
9 - i82559 Ethernet Configuration
|
10 - i82559 Ethernet Test
|
10 - i82559 Ethernet Test
|
11 - i960Rx/303 PCI Interrupt Test
|
11 - i960Rx/303 PCI Interrupt Test
|
12 - Internal Timer Test
|
12 - Internal Timer Test
|
13 - Secondary PCI Bus Test
|
13 - Secondary PCI Bus Test
|
14 - Primary PCI Bus Test
|
14 - Primary PCI Bus Test
|
15 - Battery Backup SDRAM Memory Test
|
15 - Battery Backup SDRAM Memory Test
|
16 - GPIO Test
|
16 - GPIO Test
|
17 - Repeat-On-Fail Memory Test
|
17 - Repeat-On-Fail Memory Test
|
18 - Coyonosa Cache Loop (No return)
|
18 - Coyonosa Cache Loop (No return)
|
19 - Show Software and Hardware Revision
|
19 - Show Software and Hardware Revision
|
0 - quit
|
0 - quit
|
Enter the menu item number (0 to quit): </PRE
|
Enter the menu item number (0 to quit): </PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
></P
|
></P
|
><P
|
><P
|
>Tests for various hardware subsystems are provided, and some tests require
|
>Tests for various hardware subsystems are provided, and some tests require
|
special hardware in order to execute normally. The Ethernet Configuration
|
special hardware in order to execute normally. The Ethernet Configuration
|
item may be used to set the board ethernet address.</P
|
item may be used to set the board ethernet address.</P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6242">Rebuilding RedBoot</H2
|
NAME="AEN6242">Rebuilding RedBoot</H2
|
><P
|
><P
|
>These shell variables provide the platform-specific information
|
>These shell variables provide the platform-specific information
|
needed for building RedBoot according to the procedure described in
|
needed for building RedBoot according to the procedure described in
|
<A
|
<A
|
HREF="rebuilding-redboot.html"
|
HREF="rebuilding-redboot.html"
|
>Chapter 3</A
|
>Chapter 3</A
|
>:
|
>:
|
<TABLE
|
<TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>export TARGET=iq80310
|
>export TARGET=iq80310
|
export ARCH_DIR=arm
|
export ARCH_DIR=arm
|
export PLATFORM_DIR=iq80310</PRE
|
export PLATFORM_DIR=iq80310</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
></P
|
></P
|
><P
|
><P
|
>The names of configuration files are listed above with the
|
>The names of configuration files are listed above with the
|
description of the associated modes.</P
|
description of the associated modes.</P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6248">Interrupts</H2
|
NAME="AEN6248">Interrupts</H2
|
><P
|
><P
|
>RedBoot uses an interrupt vector table which is located at address 0xA000A004.
|
>RedBoot uses an interrupt vector table which is located at address 0xA000A004.
|
Entries in this table are pointers to functions with this protoype:: <TABLE
|
Entries in this table are pointers to functions with this protoype:: <TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>int irq_handler( unsigned vector, unsigned data )</PRE
|
>int irq_handler( unsigned vector, unsigned data )</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
>On an IQ80310
|
>On an IQ80310
|
board, the vector argument is one of 49 interrupts defined in <TT
|
board, the vector argument is one of 49 interrupts defined in <TT
|
CLASS="COMPUTEROUTPUT"
|
CLASS="COMPUTEROUTPUT"
|
>hal/arm/iq80310/current/include/hal_platform_ints.h:</TT
|
>hal/arm/iq80310/current/include/hal_platform_ints.h:</TT
|
>: <TABLE
|
>: <TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>// *** 80200 CPU ***
|
>// *** 80200 CPU ***
|
#define CYGNUM_HAL_INTERRUPT_reserved0 0
|
#define CYGNUM_HAL_INTERRUPT_reserved0 0
|
#define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon.
|
#define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon.
|
#define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow
|
#define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow
|
#define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow
|
#define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow
|
#define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit
|
#define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit
|
#define CYGNUM_HAL_INTERRUPT_NIRQ 5 // external IRQ
|
#define CYGNUM_HAL_INTERRUPT_NIRQ 5 // external IRQ
|
#define CYGNUM_HAL_INTERRUPT_NFIQ 6 // external FIQ
|
#define CYGNUM_HAL_INTERRUPT_NFIQ 6 // external FIQ
|
|
|
|
|
// *** XINT6 interrupts ***
|
// *** XINT6 interrupts ***
|
#define CYGNUM_HAL_INTERRUPT_DMA_0 7
|
#define CYGNUM_HAL_INTERRUPT_DMA_0 7
|
#define CYGNUM_HAL_INTERRUPT_DMA_1 8
|
#define CYGNUM_HAL_INTERRUPT_DMA_1 8
|
#define CYGNUM_HAL_INTERRUPT_DMA_2 9
|
#define CYGNUM_HAL_INTERRUPT_DMA_2 9
|
#define CYGNUM_HAL_INTERRUPT_GTSC 10 // Global Time Stamp Counter
|
#define CYGNUM_HAL_INTERRUPT_GTSC 10 // Global Time Stamp Counter
|
#define CYGNUM_HAL_INTERRUPT_PEC 11 // Performance Event Counter
|
#define CYGNUM_HAL_INTERRUPT_PEC 11 // Performance Event Counter
|
#define CYGNUM_HAL_INTERRUPT_AAIP 12 // application accelerator unit
|
#define CYGNUM_HAL_INTERRUPT_AAIP 12 // application accelerator unit
|
|
|
|
|
// *** XINT7 interrupts ***
|
// *** XINT7 interrupts ***
|
// I2C interrupts
|
// I2C interrupts
|
#define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13
|
#define CYGNUM_HAL_INTERRUPT_I2C_TX_EMPTY 13
|
#define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL 14
|
#define CYGNUM_HAL_INTERRUPT_I2C_RX_FULL 14
|
#define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR 15
|
#define CYGNUM_HAL_INTERRUPT_I2C_BUS_ERR 15
|
#define CYGNUM_HAL_INTERRUPT_I2C_STOP 16
|
#define CYGNUM_HAL_INTERRUPT_I2C_STOP 16
|
#define CYGNUM_HAL_INTERRUPT_I2C_LOSS 17
|
#define CYGNUM_HAL_INTERRUPT_I2C_LOSS 17
|
#define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS 18
|
#define CYGNUM_HAL_INTERRUPT_I2C_ADDRESS 18
|
|
|
|
|
// Messaging Unit interrupts
|
// Messaging Unit interrupts
|
#define CYGNUM_HAL_INTERRUPT_MESSAGE_0 19
|
#define CYGNUM_HAL_INTERRUPT_MESSAGE_0 19
|
#define CYGNUM_HAL_INTERRUPT_MESSAGE_1 20
|
#define CYGNUM_HAL_INTERRUPT_MESSAGE_1 20
|
#define CYGNUM_HAL_INTERRUPT_DOORBELL 21
|
#define CYGNUM_HAL_INTERRUPT_DOORBELL 21
|
#define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL 22
|
#define CYGNUM_HAL_INTERRUPT_NMI_DOORBELL 22
|
#define CYGNUM_HAL_INTERRUPT_QUEUE_POST 23
|
#define CYGNUM_HAL_INTERRUPT_QUEUE_POST 23
|
#define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24
|
#define CYGNUM_HAL_INTERRUPT_OUTBOUND_QUEUE_FULL 24
|
#define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER 25
|
#define CYGNUM_HAL_INTERRUPT_INDEX_REGISTER 25
|
// PCI Address Translation Unit
|
// PCI Address Translation Unit
|
#define CYGNUM_HAL_INTERRUPT_BIST 26
|
#define CYGNUM_HAL_INTERRUPT_BIST 26
|
|
|
|
|
// *** External board interrupts (XINT3) ***
|
// *** External board interrupts (XINT3) ***
|
#define CYGNUM_HAL_INTERRUPT_TIMER 27 // external timer
|
#define CYGNUM_HAL_INTERRUPT_TIMER 27 // external timer
|
#define CYGNUM_HAL_INTERRUPT_ETHERNET 28 // onboard enet
|
#define CYGNUM_HAL_INTERRUPT_ETHERNET 28 // onboard enet
|
#define CYGNUM_HAL_INTERRUPT_SERIAL_A 29 // 16x50 uart A
|
#define CYGNUM_HAL_INTERRUPT_SERIAL_A 29 // 16x50 uart A
|
#define CYGNUM_HAL_INTERRUPT_SERIAL_B 30 // 16x50 uart B
|
#define CYGNUM_HAL_INTERRUPT_SERIAL_B 30 // 16x50 uart B
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTD 31 // secondary PCI INTD
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTD 31 // secondary PCI INTD
|
// The hardware doesn't (yet?) provide masking or status for these
|
// The hardware doesn't (yet?) provide masking or status for these
|
// even though they can trigger cpu interrupts. ISRs will need to
|
// even though they can trigger cpu interrupts. ISRs will need to
|
// poll the device to see if the device actually triggered the
|
// poll the device to see if the device actually triggered the
|
// interrupt.
|
// interrupt.
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTC 32 // secondary PCI INTC
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTC 32 // secondary PCI INTC
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTB 33 // secondary PCI INTB
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTB 33 // secondary PCI INTB
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTA 34 // secondary PCI INTA
|
#define CYGNUM_HAL_INTERRUPT_PCI_S_INTA 34 // secondary PCI INTA
|
|
|
|
|
// *** NMI Interrupts go to FIQ ***
|
// *** NMI Interrupts go to FIQ ***
|
#define CYGNUM_HAL_INTERRUPT_MCU_ERR 35
|
#define CYGNUM_HAL_INTERRUPT_MCU_ERR 35
|
#define CYGNUM_HAL_INTERRUPT_PATU_ERR 36
|
#define CYGNUM_HAL_INTERRUPT_PATU_ERR 36
|
#define CYGNUM_HAL_INTERRUPT_SATU_ERR 37
|
#define CYGNUM_HAL_INTERRUPT_SATU_ERR 37
|
#define CYGNUM_HAL_INTERRUPT_PBDG_ERR 38
|
#define CYGNUM_HAL_INTERRUPT_PBDG_ERR 38
|
#define CYGNUM_HAL_INTERRUPT_SBDG_ERR 39
|
#define CYGNUM_HAL_INTERRUPT_SBDG_ERR 39
|
#define CYGNUM_HAL_INTERRUPT_DMA0_ERR 40
|
#define CYGNUM_HAL_INTERRUPT_DMA0_ERR 40
|
#define CYGNUM_HAL_INTERRUPT_DMA1_ERR 41
|
#define CYGNUM_HAL_INTERRUPT_DMA1_ERR 41
|
#define CYGNUM_HAL_INTERRUPT_DMA2_ERR 42
|
#define CYGNUM_HAL_INTERRUPT_DMA2_ERR 42
|
#define CYGNUM_HAL_INTERRUPT_MU_ERR 43
|
#define CYGNUM_HAL_INTERRUPT_MU_ERR 43
|
#define CYGNUM_HAL_INTERRUPT_reserved52 44
|
#define CYGNUM_HAL_INTERRUPT_reserved52 44
|
#define CYGNUM_HAL_INTERRUPT_AAU_ERR 45
|
#define CYGNUM_HAL_INTERRUPT_AAU_ERR 45
|
#define CYGNUM_HAL_INTERRUPT_BIU_ERR 46
|
#define CYGNUM_HAL_INTERRUPT_BIU_ERR 46
|
|
|
|
|
// *** ATU FIQ sources ***
|
// *** ATU FIQ sources ***
|
#define CYGNUM_HAL_INTERRUPT_P_SERR 47
|
#define CYGNUM_HAL_INTERRUPT_P_SERR 47
|
#define CYGNUM_HAL_INTERRUPT_S_SERR 48</PRE
|
#define CYGNUM_HAL_INTERRUPT_S_SERR 48</PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
>The data passed
|
>The data passed
|
to the ISR is pulled from a data table <TT
|
to the ISR is pulled from a data table <TT
|
CLASS="COMPUTEROUTPUT"
|
CLASS="COMPUTEROUTPUT"
|
>(hal_interrupt_data)</TT
|
>(hal_interrupt_data)</TT
|
> which immediately follows the interrupt vector table. With
|
> which immediately follows the interrupt vector table. With
|
49 interrupts, the data table starts at address 0xA000A0C8. </P
|
49 interrupts, the data table starts at address 0xA000A0C8. </P
|
><P
|
><P
|
>An application may create a normal C function with the above prototype
|
>An application may create a normal C function with the above prototype
|
to be an ISR. Just poke its address into the table at the correct index and
|
to be an ISR. Just poke its address into the table at the correct index and
|
enable the interrupt at its source. The return value of the ISR is ignored
|
enable the interrupt at its source. The return value of the ISR is ignored
|
by RedBoot.</P
|
by RedBoot.</P
|
></DIV
|
></DIV
|
><DIV
|
><DIV
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><H2
|
><H2
|
CLASS="SECT2"
|
CLASS="SECT2"
|
><A
|
><A
|
NAME="AEN6256">Memory Maps</H2
|
NAME="AEN6256">Memory Maps</H2
|
><P
|
><P
|
>The first level page table is located at 0xa0004000. Two second level
|
>The first level page table is located at 0xa0004000. Two second level
|
tables are also used. One second level table is located at 0xa0008000 and
|
tables are also used. One second level table is located at 0xa0008000 and
|
maps the first 1MB of flash. The other second level table is at 0xa0008400,
|
maps the first 1MB of flash. The other second level table is at 0xa0008400,
|
and maps the first 1MB of SDRAM. <DIV
|
and maps the first 1MB of SDRAM. <DIV
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><BLOCKQUOTE
|
><BLOCKQUOTE
|
CLASS="NOTE"
|
CLASS="NOTE"
|
><P
|
><P
|
><B
|
><B
|
>NOTE: </B
|
>NOTE: </B
|
>The virtual memory maps in this section use a C and B column to indicate
|
>The virtual memory maps in this section use a C and B column to indicate
|
whether or not the region is cached (C) or buffered (B).</P
|
whether or not the region is cached (C) or buffered (B).</P
|
></BLOCKQUOTE
|
></BLOCKQUOTE
|
></DIV
|
></DIV
|
></P
|
></P
|
><P
|
><P
|
><TABLE
|
><TABLE
|
BORDER="5"
|
BORDER="5"
|
BGCOLOR="#E0E0F0"
|
BGCOLOR="#E0E0F0"
|
WIDTH="70%"
|
WIDTH="70%"
|
><TR
|
><TR
|
><TD
|
><TD
|
><PRE
|
><PRE
|
CLASS="PROGRAMLISTING"
|
CLASS="PROGRAMLISTING"
|
>Physical Address Range Description
|
>Physical Address Range Description
|
----------------------- ----------------------------------
|
----------------------- ----------------------------------
|
0x00000000 - 0x00000fff flash Memory
|
0x00000000 - 0x00000fff flash Memory
|
0x00001000 - 0x00001fff 80312 Internal Registers
|
0x00001000 - 0x00001fff 80312 Internal Registers
|
0x00002000 - 0x007fffff flash Memory
|
0x00002000 - 0x007fffff flash Memory
|
0x00800000 - 0x7fffffff PCI ATU Outbound Direct Window
|
0x00800000 - 0x7fffffff PCI ATU Outbound Direct Window
|
0x80000000 - 0x83ffffff Primary PCI 32-bit Memory
|
0x80000000 - 0x83ffffff Primary PCI 32-bit Memory
|
0x84000000 - 0x87ffffff Primary PCI 64-bit Memory
|
0x84000000 - 0x87ffffff Primary PCI 64-bit Memory
|
0x88000000 - 0x8bffffff Secondary PCI 32-bit Memory
|
0x88000000 - 0x8bffffff Secondary PCI 32-bit Memory
|
0x8c000000 - 0x8fffffff Secondary PCI 64-bit Memory
|
0x8c000000 - 0x8fffffff Secondary PCI 64-bit Memory
|
0x90000000 - 0x9000ffff Primary PCI IO Space
|
0x90000000 - 0x9000ffff Primary PCI IO Space
|
0x90010000 - 0x9001ffff Secondary PCI IO Space
|
0x90010000 - 0x9001ffff Secondary PCI IO Space
|
0x90020000 - 0x9fffffff Unused
|
0x90020000 - 0x9fffffff Unused
|
0xa0000000 - 0xbfffffff SDRAM
|
0xa0000000 - 0xbfffffff SDRAM
|
0xc0000000 - 0xefffffff Unused
|
0xc0000000 - 0xefffffff Unused
|
0xf0000000 - 0xffffffff 80200 Internal Registers
|
0xf0000000 - 0xffffffff 80200 Internal Registers
|
|
|
|
|
Virtual Address Range C B Description
|
Virtual Address Range C B Description
|
----------------------- - - ----------------------------------
|
----------------------- - - ----------------------------------
|
0x00000000 - 0x00000fff Y Y SDRAM
|
0x00000000 - 0x00000fff Y Y SDRAM
|
0x00001000 - 0x00001fff N N 80312 Internal Registers
|
0x00001000 - 0x00001fff N N 80312 Internal Registers
|
0x00002000 - 0x007fffff Y N flash Memory
|
0x00002000 - 0x007fffff Y N flash Memory
|
0x00800000 - 0x7fffffff N N PCI ATU Outbound Direct Window
|
0x00800000 - 0x7fffffff N N PCI ATU Outbound Direct Window
|
0x80000000 - 0x83ffffff N N Primary PCI 32-bit Memory
|
0x80000000 - 0x83ffffff N N Primary PCI 32-bit Memory
|
0x84000000 - 0x87ffffff N N Primary PCI 64-bit Memory
|
0x84000000 - 0x87ffffff N N Primary PCI 64-bit Memory
|
0x88000000 - 0x8bffffff N N Secondary PCI 32-bit Memory
|
0x88000000 - 0x8bffffff N N Secondary PCI 32-bit Memory
|
0x8c000000 - 0x8fffffff N N Secondary PCI 64-bit Memory
|
0x8c000000 - 0x8fffffff N N Secondary PCI 64-bit Memory
|
0x90000000 - 0x9000ffff N N Primary PCI IO Space
|
0x90000000 - 0x9000ffff N N Primary PCI IO Space
|
0x90010000 - 0x9001ffff N N Secondary PCI IO Space
|
0x90010000 - 0x9001ffff N N Secondary PCI IO Space
|
0xa0000000 - 0xbfffffff Y Y SDRAM
|
0xa0000000 - 0xbfffffff Y Y SDRAM
|
0xc0000000 - 0xcfffffff Y Y Cache Flush Region
|
0xc0000000 - 0xcfffffff Y Y Cache Flush Region
|
0xd0000000 - 0xd0000fff Y N first 4k page of flash
|
0xd0000000 - 0xd0000fff Y N first 4k page of flash
|
0xf0000000 - 0xffffffff N N 80200 Internal Registers </PRE
|
0xf0000000 - 0xffffffff N N 80200 Internal Registers </PRE
|
></TD
|
></TD
|
></TR
|
></TR
|
></TABLE
|
></TABLE
|
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|
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|
><P
|
><P
|
>The external timer is used as a polled timer to provide timeout support
|
>The external timer is used as a polled timer to provide timeout support
|
for networking and XModem file transfers.</P
|
for networking and XModem file transfers.</P
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