//==========================================================================
|
//==========================================================================
|
//
|
//
|
// frv400_misc.c
|
// frv400_misc.c
|
//
|
//
|
// HAL misc board support code for Fujitsu MB93091 ( FR-V 400)
|
// HAL misc board support code for Fujitsu MB93091 ( FR-V 400)
|
//
|
//
|
//==========================================================================
|
//==========================================================================
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
// -------------------------------------------
|
// -------------------------------------------
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
//
|
//
|
// eCos is free software; you can redistribute it and/or modify it under
|
// eCos is free software; you can redistribute it and/or modify it under
|
// the terms of the GNU General Public License as published by the Free
|
// the terms of the GNU General Public License as published by the Free
|
// Software Foundation; either version 2 or (at your option) any later version.
|
// Software Foundation; either version 2 or (at your option) any later version.
|
//
|
//
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
//
|
//
|
// As a special exception, if other files instantiate templates or use macros
|
// As a special exception, if other files instantiate templates or use macros
|
// or inline functions from this file, or you compile this file and link it
|
// or inline functions from this file, or you compile this file and link it
|
// with other works to produce a work based on this file, this file does not
|
// with other works to produce a work based on this file, this file does not
|
// by itself cause the resulting work to be covered by the GNU General Public
|
// by itself cause the resulting work to be covered by the GNU General Public
|
// License. However the source code for this file must still be made available
|
// License. However the source code for this file must still be made available
|
// in accordance with section (3) of the GNU General Public License.
|
// in accordance with section (3) of the GNU General Public License.
|
//
|
//
|
// This exception does not invalidate any other reasons why a work based on
|
// This exception does not invalidate any other reasons why a work based on
|
// this file might be covered by the GNU General Public License.
|
// this file might be covered by the GNU General Public License.
|
//
|
//
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
// at http://sources.redhat.com/ecos/ecos-license/
|
// at http://sources.redhat.com/ecos/ecos-license/
|
// -------------------------------------------
|
// -------------------------------------------
|
//####ECOSGPLCOPYRIGHTEND####
|
//####ECOSGPLCOPYRIGHTEND####
|
//==========================================================================
|
//==========================================================================
|
//#####DESCRIPTIONBEGIN####
|
//#####DESCRIPTIONBEGIN####
|
//
|
//
|
// Author(s): gthomas
|
// Author(s): gthomas
|
// Contributors: gthomas
|
// Contributors: gthomas
|
// Date: 2001-09-07
|
// Date: 2001-09-07
|
// Purpose: HAL board support
|
// Purpose: HAL board support
|
// Description: Implementations of HAL board interfaces
|
// Description: Implementations of HAL board interfaces
|
//
|
//
|
//####DESCRIPTIONEND####
|
//####DESCRIPTIONEND####
|
//
|
//
|
//========================================================================*/
|
//========================================================================*/
|
|
|
#include <pkgconf/hal.h>
|
#include <pkgconf/hal.h>
|
#include <pkgconf/system.h>
|
#include <pkgconf/system.h>
|
#include CYGBLD_HAL_PLATFORM_H
|
#include CYGBLD_HAL_PLATFORM_H
|
|
|
#include <cyg/infra/cyg_type.h> // base types
|
#include <cyg/infra/cyg_type.h> // base types
|
#include <cyg/infra/cyg_trac.h> // tracing macros
|
#include <cyg/infra/cyg_trac.h> // tracing macros
|
#include <cyg/infra/cyg_ass.h> // assertion macros
|
#include <cyg/infra/cyg_ass.h> // assertion macros
|
#include <cyg/infra/diag.h> // diag_printf() and friends
|
#include <cyg/infra/diag.h> // diag_printf() and friends
|
|
|
#include <cyg/hal/hal_io.h> // IO macros
|
#include <cyg/hal/hal_io.h> // IO macros
|
#include <cyg/hal/hal_arch.h> // Register state info
|
#include <cyg/hal/hal_arch.h> // Register state info
|
#include <cyg/hal/hal_diag.h>
|
#include <cyg/hal/hal_diag.h>
|
#include <cyg/hal/hal_intr.h> // Interrupt names
|
#include <cyg/hal/hal_intr.h> // Interrupt names
|
#include <cyg/hal/hal_cache.h>
|
#include <cyg/hal/hal_cache.h>
|
#include <cyg/hal/frv400.h> // Hardware definitions
|
#include <cyg/hal/frv400.h> // Hardware definitions
|
#include <cyg/hal/hal_if.h> // calling interface API
|
#include <cyg/hal/hal_if.h> // calling interface API
|
|
|
#include <pkgconf/io_pci.h>
|
#include <pkgconf/io_pci.h>
|
#include <cyg/io/pci_hw.h>
|
#include <cyg/io/pci_hw.h>
|
#include <cyg/io/pci.h>
|
#include <cyg/io/pci.h>
|
|
|
static cyg_uint32 _period;
|
static cyg_uint32 _period;
|
|
|
void hal_clock_initialize(cyg_uint32 period)
|
void hal_clock_initialize(cyg_uint32 period)
|
{
|
{
|
_period = period;
|
_period = period;
|
// Set timer #1 to run in terminal count mode for period
|
// Set timer #1 to run in terminal count mode for period
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
|
// Configure interrupt
|
// Configure interrupt
|
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_TIMER1, 1, 1); // Interrupt when TOUT1 is high
|
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_TIMER1, 1, 1); // Interrupt when TOUT1 is high
|
}
|
}
|
|
|
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
|
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
|
{
|
{
|
cyg_int16 offset;
|
cyg_int16 offset;
|
cyg_uint8 _val;
|
cyg_uint8 _val;
|
|
|
// Latch & read counter from timer #1
|
// Latch & read counter from timer #1
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
offset = _val;
|
offset = _val;
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
offset |= _val << 8; // This will be the number of clocks beyond 0
|
offset |= _val << 8; // This will be the number of clocks beyond 0
|
period += offset;
|
period += offset;
|
// Reinitialize with adjusted count
|
// Reinitialize with adjusted count
|
// Set timer #1 to run in terminal count mode for period
|
// Set timer #1 to run in terminal count mode for period
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
|
HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
|
}
|
}
|
|
|
// Read the current value of the clock, returning the number of hardware "ticks"
|
// Read the current value of the clock, returning the number of hardware "ticks"
|
// that have occurred (i.e. how far away the current value is from the start)
|
// that have occurred (i.e. how far away the current value is from the start)
|
|
|
void hal_clock_read(cyg_uint32 *pvalue)
|
void hal_clock_read(cyg_uint32 *pvalue)
|
{
|
{
|
cyg_int16 offset;
|
cyg_int16 offset;
|
cyg_uint8 _val;
|
cyg_uint8 _val;
|
|
|
// Latch & read counter from timer #1
|
// Latch & read counter from timer #1
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
offset = _val;
|
offset = _val;
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
HAL_READ_UINT8(_FRV400_TCSR1, _val);
|
offset |= _val << 8;
|
offset |= _val << 8;
|
|
|
// 'offset' is the current timer value
|
// 'offset' is the current timer value
|
*pvalue = _period - offset;
|
*pvalue = _period - offset;
|
}
|
}
|
|
|
// Delay for some number of useconds.
|
// Delay for some number of useconds.
|
// Assumptions:
|
// Assumptions:
|
// Use timer #2
|
// Use timer #2
|
// Min granularity is 10us
|
// Min granularity is 10us
|
#define _MIN_DELAY 10
|
#define _MIN_DELAY 10
|
|
|
void hal_delay_us(int us)
|
void hal_delay_us(int us)
|
{
|
{
|
cyg_uint8 stat;
|
cyg_uint8 stat;
|
int timeout;
|
int timeout;
|
|
|
while (us >= _MIN_DELAY) {
|
while (us >= _MIN_DELAY) {
|
us -= _MIN_DELAY;
|
us -= _MIN_DELAY;
|
// Set timer #2 to run in terminal count mode for _MIN_DELAY us
|
// Set timer #2 to run in terminal count mode for _MIN_DELAY us
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL2|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL2|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
|
HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY & 0xFF);
|
HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY & 0xFF);
|
HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY >> 8);
|
HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY >> 8);
|
timeout = 100000;
|
timeout = 100000;
|
// Wait for TOUT to indicate terminal count reached
|
// Wait for TOUT to indicate terminal count reached
|
do {
|
do {
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_RB|_FRV400_TCTR_RB_NCOUNT|_FRV400_TCTR_RB_CTR2);
|
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_RB|_FRV400_TCTR_RB_NCOUNT|_FRV400_TCTR_RB_CTR2);
|
HAL_READ_UINT8(_FRV400_TCSR2, stat);
|
HAL_READ_UINT8(_FRV400_TCSR2, stat);
|
if (--timeout == 0) break;
|
if (--timeout == 0) break;
|
} while ((stat & _FRV400_TCxSR_TOUT) == 0);
|
} while ((stat & _FRV400_TCxSR_TOUT) == 0);
|
}
|
}
|
}
|
}
|
|
|
//
|
//
|
// Early stage hardware initialization
|
// Early stage hardware initialization
|
// Some initialization has already been done before we get here. For now
|
// Some initialization has already been done before we get here. For now
|
// just set up the interrupt environment.
|
// just set up the interrupt environment.
|
|
|
long _system_clock; // Calculated clock frequency
|
long _system_clock; // Calculated clock frequency
|
|
|
void hal_hardware_init(void)
|
void hal_hardware_init(void)
|
{
|
{
|
cyg_uint32 clk;
|
cyg_uint32 clk;
|
|
|
// Set up interrupt controller
|
// Set up interrupt controller
|
HAL_WRITE_UINT16(_FRV400_IRC_MASK, 0xFFFE); // All masked
|
HAL_WRITE_UINT16(_FRV400_IRC_MASK, 0xFFFE); // All masked
|
HAL_WRITE_UINT16(_FRV400_IRC_RC, 0xFFFE); // All cleared
|
HAL_WRITE_UINT16(_FRV400_IRC_RC, 0xFFFE); // All cleared
|
HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clear IRL (interrupt request latch)
|
HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clear IRL (interrupt request latch)
|
|
|
// Onboard FPGA interrupts
|
// Onboard FPGA interrupts
|
HAL_WRITE_UINT16(_FRV400_FPGA_CONTROL, _FRV400_FPGA_CONTROL_IRQ); // Enable IRQ registers
|
HAL_WRITE_UINT16(_FRV400_FPGA_CONTROL, _FRV400_FPGA_CONTROL_IRQ); // Enable IRQ registers
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, // Set up for LAN, PCI INTx
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, // Set up for LAN, PCI INTx
|
0x7FFE &
|
0x7FFE &
|
~(_FRV400_FPGA_IRQ_LAN |
|
~(_FRV400_FPGA_IRQ_LAN |
|
_FRV400_FPGA_IRQ_INTA |
|
_FRV400_FPGA_IRQ_INTA |
|
_FRV400_FPGA_IRQ_INTB |
|
_FRV400_FPGA_IRQ_INTB |
|
_FRV400_FPGA_IRQ_INTC |
|
_FRV400_FPGA_IRQ_INTC |
|
_FRV400_FPGA_IRQ_INTD)
|
_FRV400_FPGA_IRQ_INTD)
|
);
|
);
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_LEVELS, // Set up for LAN, PCI INTx
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_LEVELS, // Set up for LAN, PCI INTx
|
0x7FFE &
|
0x7FFE &
|
~(_FRV400_FPGA_IRQ_LAN |
|
~(_FRV400_FPGA_IRQ_LAN |
|
_FRV400_FPGA_IRQ_INTA |
|
_FRV400_FPGA_IRQ_INTA |
|
_FRV400_FPGA_IRQ_INTB |
|
_FRV400_FPGA_IRQ_INTB |
|
_FRV400_FPGA_IRQ_INTC |
|
_FRV400_FPGA_IRQ_INTC |
|
_FRV400_FPGA_IRQ_INTD)
|
_FRV400_FPGA_IRQ_INTD)
|
);
|
);
|
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 0); // Level, low
|
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 0); // Level, low
|
|
|
// Set up system clock
|
// Set up system clock
|
HAL_READ_UINT32(_FRV400_MB_CLKSW, clk);
|
HAL_READ_UINT32(_FRV400_MB_CLKSW, clk);
|
_system_clock = (((clk&0xFF) * 125 * 2) / 240) * 1000000;
|
_system_clock = (((clk&0xFF) * 125 * 2) / 240) * 1000000;
|
|
|
// Set scalers to achieve 1us resolution in timer
|
// Set scalers to achieve 1us resolution in timer
|
HAL_WRITE_UINT8(_FRV400_TPRV, _system_clock / (1000*1000));
|
HAL_WRITE_UINT8(_FRV400_TPRV, _system_clock / (1000*1000));
|
HAL_WRITE_UINT8(_FRV400_TCKSL0, 0x80);
|
HAL_WRITE_UINT8(_FRV400_TCKSL0, 0x80);
|
HAL_WRITE_UINT8(_FRV400_TCKSL1, 0x80);
|
HAL_WRITE_UINT8(_FRV400_TCKSL1, 0x80);
|
HAL_WRITE_UINT8(_FRV400_TCKSL2, 0x80);
|
HAL_WRITE_UINT8(_FRV400_TCKSL2, 0x80);
|
|
|
hal_if_init();
|
hal_if_init();
|
|
|
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
|
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
|
hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
|
hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
|
|
|
_frv400_pci_init();
|
_frv400_pci_init();
|
}
|
}
|
|
|
//
|
//
|
// Interrupt control
|
// Interrupt control
|
//
|
//
|
|
|
void hal_interrupt_mask(int vector)
|
void hal_interrupt_mask(int vector)
|
{
|
{
|
cyg_uint16 _mask;
|
cyg_uint16 _mask;
|
|
|
switch (vector) {
|
switch (vector) {
|
case CYGNUM_HAL_INTERRUPT_LAN:
|
case CYGNUM_HAL_INTERRUPT_LAN:
|
HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
_mask |= _FRV400_FPGA_IRQ_LAN;
|
_mask |= _FRV400_FPGA_IRQ_LAN;
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
break;
|
break;
|
}
|
}
|
HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
|
HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
|
_mask |= (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
|
_mask |= (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
|
HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
|
HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
|
}
|
}
|
|
|
void hal_interrupt_unmask(int vector)
|
void hal_interrupt_unmask(int vector)
|
{
|
{
|
cyg_uint16 _mask;
|
cyg_uint16 _mask;
|
|
|
switch (vector) {
|
switch (vector) {
|
case CYGNUM_HAL_INTERRUPT_LAN:
|
case CYGNUM_HAL_INTERRUPT_LAN:
|
HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
_mask &= ~_FRV400_FPGA_IRQ_LAN;
|
_mask &= ~_FRV400_FPGA_IRQ_LAN;
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
|
break;
|
break;
|
}
|
}
|
HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
|
HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
|
_mask &= ~(1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
|
_mask &= ~(1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
|
HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
|
HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
|
}
|
}
|
|
|
void hal_interrupt_acknowledge(int vector)
|
void hal_interrupt_acknowledge(int vector)
|
{
|
{
|
cyg_uint16 _mask;
|
cyg_uint16 _mask;
|
|
|
switch (vector) {
|
switch (vector) {
|
case CYGNUM_HAL_INTERRUPT_LAN:
|
case CYGNUM_HAL_INTERRUPT_LAN:
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_REQUEST, // Clear LAN interrupt
|
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_REQUEST, // Clear LAN interrupt
|
0x7FFE & ~_FRV400_FPGA_IRQ_LAN);
|
0x7FFE & ~_FRV400_FPGA_IRQ_LAN);
|
break;
|
break;
|
}
|
}
|
_mask = (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
|
_mask = (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
|
HAL_WRITE_UINT16(_FRV400_IRC_RC, _mask);
|
HAL_WRITE_UINT16(_FRV400_IRC_RC, _mask);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clears IRL latch
|
HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clears IRL latch
|
}
|
}
|
|
|
//
|
//
|
// Configure an interrupt
|
// Configure an interrupt
|
// level - boolean (0=> edge, 1=>level)
|
// level - boolean (0=> edge, 1=>level)
|
// up - edge: (0=>falling edge, 1=>rising edge)
|
// up - edge: (0=>falling edge, 1=>rising edge)
|
// level: (0=>low, 1=>high)
|
// level: (0=>low, 1=>high)
|
//
|
//
|
void hal_interrupt_configure(int vector, int level, int up)
|
void hal_interrupt_configure(int vector, int level, int up)
|
{
|
{
|
cyg_uint16 _irr, _tmr, _trig;
|
cyg_uint16 _irr, _tmr, _trig;
|
|
|
if (level) {
|
if (level) {
|
if (up) {
|
if (up) {
|
_trig = 0; // level, high
|
_trig = 0; // level, high
|
} else {
|
} else {
|
_trig = 1; // level, low
|
_trig = 1; // level, low
|
}
|
}
|
} else {
|
} else {
|
if (up) {
|
if (up) {
|
_trig = 2; // edge, rising
|
_trig = 2; // edge, rising
|
} else {
|
} else {
|
_trig = 3; // edge, falling
|
_trig = 3; // edge, falling
|
}
|
}
|
}
|
}
|
switch (vector) {
|
switch (vector) {
|
case CYGNUM_HAL_INTERRUPT_TIMER0:
|
case CYGNUM_HAL_INTERRUPT_TIMER0:
|
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
|
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_TIMER1:
|
case CYGNUM_HAL_INTERRUPT_TIMER1:
|
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
|
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_TIMER2:
|
case CYGNUM_HAL_INTERRUPT_TIMER2:
|
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
|
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_DMA0:
|
case CYGNUM_HAL_INTERRUPT_DMA0:
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
|
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_DMA1:
|
case CYGNUM_HAL_INTERRUPT_DMA1:
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
|
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_DMA2:
|
case CYGNUM_HAL_INTERRUPT_DMA2:
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0xCFFF) | (_trig<<12);
|
_tmr = (_tmr & 0xCFFF) | (_trig<<12);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_DMA3:
|
case CYGNUM_HAL_INTERRUPT_DMA3:
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
|
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
|
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
|
_tmr = (_tmr & 0x3FFF) | (_trig<<14);
|
_tmr = (_tmr & 0x3FFF) | (_trig<<14);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_UART0:
|
case CYGNUM_HAL_INTERRUPT_UART0:
|
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
|
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
|
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_UART1:
|
case CYGNUM_HAL_INTERRUPT_UART1:
|
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
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HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
|
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
|
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_EXT0:
|
case CYGNUM_HAL_INTERRUPT_EXT0:
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
|
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_EXT1:
|
case CYGNUM_HAL_INTERRUPT_EXT1:
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
|
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_EXT2:
|
case CYGNUM_HAL_INTERRUPT_EXT2:
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
|
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
break;
|
break;
|
case CYGNUM_HAL_INTERRUPT_EXT3:
|
case CYGNUM_HAL_INTERRUPT_EXT3:
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
|
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
|
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
|
_tmr = (_tmr & 0xFF3F) | (_trig<<6);
|
_tmr = (_tmr & 0xFF3F) | (_trig<<6);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
|
break;
|
break;
|
default:
|
default:
|
; // Nothing to do
|
; // Nothing to do
|
};
|
};
|
}
|
}
|
|
|
void hal_interrupt_set_level(int vector, int level)
|
void hal_interrupt_set_level(int vector, int level)
|
{
|
{
|
// UNIMPLEMENTED(__FUNCTION__);
|
// UNIMPLEMENTED(__FUNCTION__);
|
}
|
}
|
|
|
// PCI support
|
// PCI support
|
|
|
externC void
|
externC void
|
_frv400_pci_init(void)
|
_frv400_pci_init(void)
|
{
|
{
|
static int _init = 0;
|
static int _init = 0;
|
cyg_uint8 next_bus;
|
cyg_uint8 next_bus;
|
cyg_uint32 cmd_state;
|
cyg_uint32 cmd_state;
|
|
|
if (_init) return;
|
if (_init) return;
|
_init = 1;
|
_init = 1;
|
|
|
// Enable controller - most of the basic configuration
|
// Enable controller - most of the basic configuration
|
// was set up at boot time in "platform.inc"
|
// was set up at boot time in "platform.inc"
|
|
|
// Setup for bus mastering
|
// Setup for bus mastering
|
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
CYG_PCI_CFG_COMMAND, cmd_state);
|
CYG_PCI_CFG_COMMAND, cmd_state);
|
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
|
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
|
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
CYG_PCI_CFG_COMMAND,
|
CYG_PCI_CFG_COMMAND,
|
CYG_PCI_CFG_COMMAND_MEMORY |
|
CYG_PCI_CFG_COMMAND_MEMORY |
|
CYG_PCI_CFG_COMMAND_MASTER |
|
CYG_PCI_CFG_COMMAND_MASTER |
|
CYG_PCI_CFG_COMMAND_PARITY |
|
CYG_PCI_CFG_COMMAND_PARITY |
|
CYG_PCI_CFG_COMMAND_SERR);
|
CYG_PCI_CFG_COMMAND_SERR);
|
|
|
// Setup latency timer field
|
// Setup latency timer field
|
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
|
CYG_PCI_CFG_LATENCY_TIMER, 32);
|
CYG_PCI_CFG_LATENCY_TIMER, 32);
|
|
|
// Configure PCI bus.
|
// Configure PCI bus.
|
next_bus = 1;
|
next_bus = 1;
|
cyg_pci_configure_bus(0, &next_bus);
|
cyg_pci_configure_bus(0, &next_bus);
|
}
|
}
|
|
|
}
|
}
|
|
|
externC void
|
externC void
|
_frv400_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
|
_frv400_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
|
{
|
{
|
cyg_uint8 req;
|
cyg_uint8 req;
|
cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
|
cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
|
|
|
if (dev == CYG_PCI_MIN_DEV) {
|
if (dev == CYG_PCI_MIN_DEV) {
|
// On board LAN
|
// On board LAN
|
*vec = CYGNUM_HAL_INTERRUPT_LAN;
|
*vec = CYGNUM_HAL_INTERRUPT_LAN;
|
*valid = true;
|
*valid = true;
|
} else {
|
} else {
|
HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);
|
HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);
|
if (0 != req) {
|
if (0 != req) {
|
CYG_ADDRWORD __translation[4] = {
|
CYG_ADDRWORD __translation[4] = {
|
CYGNUM_HAL_INTERRUPT_PCIINTC, /* INTC# */
|
CYGNUM_HAL_INTERRUPT_PCIINTC, /* INTC# */
|
CYGNUM_HAL_INTERRUPT_PCIINTB, /* INTB# */
|
CYGNUM_HAL_INTERRUPT_PCIINTB, /* INTB# */
|
CYGNUM_HAL_INTERRUPT_PCIINTA, /* INTA# */
|
CYGNUM_HAL_INTERRUPT_PCIINTA, /* INTA# */
|
CYGNUM_HAL_INTERRUPT_PCIINTD}; /* INTD# */
|
CYGNUM_HAL_INTERRUPT_PCIINTD}; /* INTD# */
|
|
|
/* The PCI lines from the different slots are wired like this */
|
/* The PCI lines from the different slots are wired like this */
|
/* on the PCI backplane: */
|
/* on the PCI backplane: */
|
/* pin6A pin7B pin7A pin8B */
|
/* pin6A pin7B pin7A pin8B */
|
/* I/O Slot 1 INTA# INTB# INTC# INTD# */
|
/* I/O Slot 1 INTA# INTB# INTC# INTD# */
|
/* I/O Slot 2 INTD# INTA# INTB# INTC# */
|
/* I/O Slot 2 INTD# INTA# INTB# INTC# */
|
/* I/O Slot 3 INTC# INTD# INTA# INTB# */
|
/* I/O Slot 3 INTC# INTD# INTA# INTB# */
|
/* */
|
/* */
|
/* (From PCI Development Backplane, 3.2.2 Interrupts) */
|
/* (From PCI Development Backplane, 3.2.2 Interrupts) */
|
/* */
|
/* */
|
/* Devsel signals are wired to, resulting in device IDs: */
|
/* Devsel signals are wired to, resulting in device IDs: */
|
/* I/O Slot 1 AD30 / dev 19 [(8+1)&3 = 1] */
|
/* I/O Slot 1 AD30 / dev 19 [(8+1)&3 = 1] */
|
/* I/O Slot 2 AD29 / dev 18 [(7+1)&3 = 0] */
|
/* I/O Slot 2 AD29 / dev 18 [(7+1)&3 = 0] */
|
/* I/O Slot 3 AD28 / dev 17 [(6+1)&3 = 3] */
|
/* I/O Slot 3 AD28 / dev 17 [(6+1)&3 = 3] */
|
|
|
*vec = __translation[((req+dev)&3)];
|
*vec = __translation[((req+dev)&3)];
|
*valid = true;
|
*valid = true;
|
} else {
|
} else {
|
/* Device will not generate interrupt requests. */
|
/* Device will not generate interrupt requests. */
|
*valid = false;
|
*valid = false;
|
}
|
}
|
diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
|
diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
|
}
|
}
|
}
|
}
|
|
|
// PCI configuration space access
|
// PCI configuration space access
|
#define _EXT_ENABLE 0x80000000 // Could be 0x80000000
|
#define _EXT_ENABLE 0x80000000 // Could be 0x80000000
|
|
|
static __inline__ cyg_uint32
|
static __inline__ cyg_uint32
|
_cfg_addr(int bus, int devfn, int offset)
|
_cfg_addr(int bus, int devfn, int offset)
|
{
|
{
|
return _EXT_ENABLE | (bus << 22) | (devfn << 8) | (offset << 0);
|
return _EXT_ENABLE | (bus << 22) | (devfn << 8) | (offset << 0);
|
}
|
}
|
|
|
externC cyg_uint8
|
externC cyg_uint8
|
_frv400_pci_cfg_read_uint8(int bus, int devfn, int offset)
|
_frv400_pci_cfg_read_uint8(int bus, int devfn, int offset)
|
{
|
{
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint8 cfg_val = (cyg_uint8)0xFF;
|
cyg_uint8 cfg_val = (cyg_uint8)0xFF;
|
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
// PCI bridge
|
// PCI bridge
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
|
} else {
|
} else {
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
|
}
|
}
|
HAL_READ_UINT8(addr, cfg_val);
|
HAL_READ_UINT8(addr, cfg_val);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
// Cycle failed - clean up and get out
|
// Cycle failed - clean up and get out
|
cfg_val = (cyg_uint8)0xFF;
|
cfg_val = (cyg_uint8)0xFF;
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
}
|
}
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%x\n", cfg_val);
|
diag_printf("%x\n", cfg_val);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
return cfg_val;
|
return cfg_val;
|
}
|
}
|
|
|
externC cyg_uint16
|
externC cyg_uint16
|
_frv400_pci_cfg_read_uint16(int bus, int devfn, int offset)
|
_frv400_pci_cfg_read_uint16(int bus, int devfn, int offset)
|
{
|
{
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
|
cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
|
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
// PCI bridge
|
// PCI bridge
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
|
} else {
|
} else {
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
|
}
|
}
|
HAL_READ_UINT16(addr, cfg_val);
|
HAL_READ_UINT16(addr, cfg_val);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
// Cycle failed - clean up and get out
|
// Cycle failed - clean up and get out
|
cfg_val = (cyg_uint16)0xFFFF;
|
cfg_val = (cyg_uint16)0xFFFF;
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
}
|
}
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%x\n", cfg_val);
|
diag_printf("%x\n", cfg_val);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
return cfg_val;
|
return cfg_val;
|
}
|
}
|
|
|
externC cyg_uint32
|
externC cyg_uint32
|
_frv400_pci_cfg_read_uint32(int bus, int devfn, int offset)
|
_frv400_pci_cfg_read_uint32(int bus, int devfn, int offset)
|
{
|
{
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
|
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
|
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
// PCI bridge
|
// PCI bridge
|
addr = _FRV400_PCI_CONFIG + (offset << 1);
|
addr = _FRV400_PCI_CONFIG + (offset << 1);
|
} else {
|
} else {
|
cfg_addr = _cfg_addr(bus, devfn, offset);
|
cfg_addr = _cfg_addr(bus, devfn, offset);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
addr = _FRV400_PCI_CONFIG_DATA;
|
addr = _FRV400_PCI_CONFIG_DATA;
|
}
|
}
|
HAL_READ_UINT32(addr, cfg_val);
|
HAL_READ_UINT32(addr, cfg_val);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
// Cycle failed - clean up and get out
|
// Cycle failed - clean up and get out
|
cfg_val = (cyg_uint32)0xFFFFFFFF;
|
cfg_val = (cyg_uint32)0xFFFFFFFF;
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
}
|
}
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%x\n", cfg_val);
|
diag_printf("%x\n", cfg_val);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
return cfg_val;
|
return cfg_val;
|
}
|
}
|
|
|
externC void
|
externC void
|
_frv400_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
|
_frv400_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
|
{
|
{
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_addr, addr, status;
|
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
// PCI bridge
|
// PCI bridge
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
|
} else {
|
} else {
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
|
}
|
}
|
HAL_WRITE_UINT8(addr, cfg_val);
|
HAL_WRITE_UINT8(addr, cfg_val);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
// Cycle failed - clean up and get out
|
// Cycle failed - clean up and get out
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
}
|
}
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
}
|
}
|
|
|
externC void
|
externC void
|
_frv400_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
|
_frv400_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
|
{
|
{
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_addr, addr, status;
|
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
// PCI bridge
|
// PCI bridge
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
|
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
|
} else {
|
} else {
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
|
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
|
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
|
}
|
}
|
HAL_WRITE_UINT16(addr, cfg_val);
|
HAL_WRITE_UINT16(addr, cfg_val);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
// Cycle failed - clean up and get out
|
// Cycle failed - clean up and get out
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
}
|
}
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
}
|
}
|
|
|
externC void
|
externC void
|
_frv400_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
|
_frv400_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
|
{
|
{
|
cyg_uint32 cfg_addr, addr, status;
|
cyg_uint32 cfg_addr, addr, status;
|
|
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
#ifdef CYGPKG_IO_PCI_DEBUG
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
|
#endif // CYGPKG_IO_PCI_DEBUG
|
#endif // CYGPKG_IO_PCI_DEBUG
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
|
// PCI bridge
|
// PCI bridge
|
addr = _FRV400_PCI_CONFIG + (offset << 1);
|
addr = _FRV400_PCI_CONFIG + (offset << 1);
|
} else {
|
} else {
|
cfg_addr = _cfg_addr(bus, devfn, offset);
|
cfg_addr = _cfg_addr(bus, devfn, offset);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
|
addr = _FRV400_PCI_CONFIG_DATA;
|
addr = _FRV400_PCI_CONFIG_DATA;
|
}
|
}
|
HAL_WRITE_UINT32(addr, cfg_val);
|
HAL_WRITE_UINT32(addr, cfg_val);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
|
// Cycle failed - clean up and get out
|
// Cycle failed - clean up and get out
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
|
}
|
}
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
|
}
|
}
|
|
|
// ------------------------------------------------------------------------
|
// ------------------------------------------------------------------------
|
//
|
//
|
// Hardware breakpoint/watchpoint support
|
// Hardware breakpoint/watchpoint support
|
// ======================================
|
// ======================================
|
//
|
//
|
// Now follows a load of extreme unpleasantness to deal with the totally
|
// Now follows a load of extreme unpleasantness to deal with the totally
|
// broken debug model of this device.
|
// broken debug model of this device.
|
//
|
//
|
// To modify the special hardware debug registers, it is necessary to put
|
// To modify the special hardware debug registers, it is necessary to put
|
// the CPU into "debug mode". This can only be done by executing a break
|
// the CPU into "debug mode". This can only be done by executing a break
|
// instruction, or taking a special hardware break event as described by
|
// instruction, or taking a special hardware break event as described by
|
// the special hardware debug registers.
|
// the special hardware debug registers.
|
//
|
//
|
// But once in debug mode, no break is taken, and break instructions are
|
// But once in debug mode, no break is taken, and break instructions are
|
// ignored, because we are in debug mode.
|
// ignored, because we are in debug mode.
|
//
|
//
|
// So we must exit debug mode for normal running, which you can only do via
|
// So we must exit debug mode for normal running, which you can only do via
|
// a rett #1 instruction. Because rett is for returning from traps, it
|
// a rett #1 instruction. Because rett is for returning from traps, it
|
// halts the CPU if you do it with traps enabled. So you have to mess
|
// halts the CPU if you do it with traps enabled. So you have to mess
|
// about disabling traps before the rett. Also, because rett #1 is for
|
// about disabling traps before the rett. Also, because rett #1 is for
|
// returning from a *debug* trap, you can only issue it from debug mode -
|
// returning from a *debug* trap, you can only issue it from debug mode -
|
// or it halts the CPU.
|
// or it halts the CPU.
|
//
|
//
|
// To be able to set and unset hardware debug breakpoints and watchpoints,
|
// To be able to set and unset hardware debug breakpoints and watchpoints,
|
// we must enter debug mode (via a "break" instruction). Fortunately, it
|
// we must enter debug mode (via a "break" instruction). Fortunately, it
|
// is possible to return from a "break" remaining in debug mode, using a
|
// is possible to return from a "break" remaining in debug mode, using a
|
// rett #0, so we can arrange that a break instruction just means "go to
|
// rett #0, so we can arrange that a break instruction just means "go to
|
// debug mode".
|
// debug mode".
|
//
|
//
|
// So we can manipulate the special hardware debug registers by executing a
|
// So we can manipulate the special hardware debug registers by executing a
|
// "break", doing the work, then doing the magic sequence to rett #1.
|
// "break", doing the work, then doing the magic sequence to rett #1.
|
// These are encapsulated in HAL_FRV_ENTER_DEBUG_MODE() and
|
// These are encapsulated in HAL_FRV_ENTER_DEBUG_MODE() and
|
// HAL_FRV_EXIT_DEBUG_MODE() from plf_stub.h
|
// HAL_FRV_EXIT_DEBUG_MODE() from plf_stub.h
|
//
|
//
|
// So, we get into break_hander() for two reasons:
|
// So, we get into break_hander() for two reasons:
|
// 1) a break instruction. Detect this and do nothing; return skipping
|
// 1) a break instruction. Detect this and do nothing; return skipping
|
// over the break instruction. CPU remains in debug mode.
|
// over the break instruction. CPU remains in debug mode.
|
// 2) a hardware debug trap. Continue just as for a normal exception;
|
// 2) a hardware debug trap. Continue just as for a normal exception;
|
// GDB and the stubs will handle it. But first, exit debug mode, or
|
// GDB and the stubs will handle it. But first, exit debug mode, or
|
// stuff happening in the stubs will go wrong.
|
// stuff happening in the stubs will go wrong.
|
//
|
//
|
// In order to be certain that we are in debug mode, for performing (2)
|
// In order to be certain that we are in debug mode, for performing (2)
|
// safely, vectors.S installs a special debug trap handler on vector #255.
|
// safely, vectors.S installs a special debug trap handler on vector #255.
|
// That's the reason for break_handler() existing as a separate routine.
|
// That's the reason for break_handler() existing as a separate routine.
|
//
|
//
|
// Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for the
|
// Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for the
|
// FRV_FRV400 target; while we do use Hardware Debug, we don't use *that*
|
// FRV_FRV400 target; while we do use Hardware Debug, we don't use *that*
|
// sort of hardware debug, specifically we do not use hardware single-step,
|
// sort of hardware debug, specifically we do not use hardware single-step,
|
// because it breaks as soon as we exit debug mode, ie. whilst we are still
|
// because it breaks as soon as we exit debug mode, ie. whilst we are still
|
// within the stub. So in fact defining CYGSEM_HAL_FRV_HW_DEBUG is bad; I
|
// within the stub. So in fact defining CYGSEM_HAL_FRV_HW_DEBUG is bad; I
|
// guess it is mis-named.
|
// guess it is mis-named.
|
//
|
//
|
|
|
// ------------------------------------------------------------------------
|
// ------------------------------------------------------------------------
|
// First a load of ugly boilerplate for register access.
|
// First a load of ugly boilerplate for register access.
|
|
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
|
|
#include <cyg/hal/hal_stub.h> // HAL_STUB_HW_STOP_NONE et al
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#include <cyg/hal/hal_stub.h> // HAL_STUB_HW_STOP_NONE et al
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#include <cyg/hal/frv_stub.h> // register names PC, PSR et al
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#include <cyg/hal/frv_stub.h> // register names PC, PSR et al
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#include <cyg/hal/plf_stub.h> // HAL_FRV_EXIT_DEBUG_MODE()
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#include <cyg/hal/plf_stub.h> // HAL_FRV_EXIT_DEBUG_MODE()
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// First a load of glue
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// First a load of glue
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static inline unsigned get_bpsr(void) {
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static inline unsigned get_bpsr(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg bpsr,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg bpsr,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_bpsr(unsigned val) {
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static inline void set_bpsr(unsigned val) {
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asm volatile ( "movgs %0,bpsr\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,bpsr\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dcr(void) {
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static inline unsigned get_dcr(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dcr,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dcr,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dcr(unsigned val) {
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static inline void set_dcr(unsigned val) {
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asm volatile ( "movgs %0,dcr\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dcr\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_brr(void) {
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static inline unsigned get_brr(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg brr,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg brr,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_brr(unsigned val) {
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static inline void set_brr(unsigned val) {
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asm volatile ( "movgs %0,brr\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,brr\n" : /* no outputs */ : "r" (val) );}
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// Four Instruction Break Address Registers
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// Four Instruction Break Address Registers
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static inline unsigned get_ibar0(void) {
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static inline unsigned get_ibar0(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg ibar0,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg ibar0,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_ibar0(unsigned val) {
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static inline void set_ibar0(unsigned val) {
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asm volatile ( "movgs %0,ibar0\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,ibar0\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_ibar1(void) {
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static inline unsigned get_ibar1(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg ibar1,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg ibar1,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_ibar1(unsigned val){
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static inline void set_ibar1(unsigned val){
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asm volatile ( "movgs %0,ibar1\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,ibar1\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_ibar2(void) {
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static inline unsigned get_ibar2(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg ibar2,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg ibar2,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_ibar2(unsigned val) {
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static inline void set_ibar2(unsigned val) {
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asm volatile ( "movgs %0,ibar2\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,ibar2\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_ibar3(void) {
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static inline unsigned get_ibar3(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg ibar3,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg ibar3,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_ibar3(unsigned val){
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static inline void set_ibar3(unsigned val){
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asm volatile ( "movgs %0,ibar3\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,ibar3\n" : /* no outputs */ : "r" (val) );}
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// Two Data Break Address Registers
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// Two Data Break Address Registers
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static inline unsigned get_dbar0(void) {
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static inline unsigned get_dbar0(void) {
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbar0,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbar0,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbar0(unsigned val){
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static inline void set_dbar0(unsigned val){
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asm volatile ( "movgs %0,dbar0\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbar0\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbar1(void){
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static inline unsigned get_dbar1(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbar1,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbar1,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbar1(unsigned val){
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static inline void set_dbar1(unsigned val){
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asm volatile ( "movgs %0,dbar1\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbar1\n" : /* no outputs */ : "r" (val) );}
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// Two times two Data Break Data Registers
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// Two times two Data Break Data Registers
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static inline unsigned get_dbdr00(void){
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static inline unsigned get_dbdr00(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbdr00,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbdr00,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbdr00(unsigned val){
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static inline void set_dbdr00(unsigned val){
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asm volatile ( "movgs %0,dbdr00\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbdr00\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbdr01(void){
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static inline unsigned get_dbdr01(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbdr01,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbdr01,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbdr01(unsigned val){
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static inline void set_dbdr01(unsigned val){
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asm volatile ( "movgs %0,dbdr01\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbdr01\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbdr10(void){
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static inline unsigned get_dbdr10(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbdr10,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbdr10,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbdr10(unsigned val){
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static inline void set_dbdr10(unsigned val){
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asm volatile ( "movgs %0,dbdr10\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbdr10\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbdr11(void){
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static inline unsigned get_dbdr11(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbdr11,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbdr11,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbdr11(unsigned val){
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static inline void set_dbdr11(unsigned val){
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asm volatile ( "movgs %0,dbdr11\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbdr11\n" : /* no outputs */ : "r" (val) );}
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// Two times two Data Break Mask Registers
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// Two times two Data Break Mask Registers
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static inline unsigned get_dbmr00(void){
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static inline unsigned get_dbmr00(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbmr00,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbmr00,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbmr00(unsigned val){
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static inline void set_dbmr00(unsigned val){
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asm volatile ( "movgs %0,dbmr00\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbmr00\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbmr01(void){
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static inline unsigned get_dbmr01(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbmr01,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbmr01,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbmr01(unsigned val){
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static inline void set_dbmr01(unsigned val){
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asm volatile ( "movgs %0,dbmr01\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbmr01\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbmr10(void){
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static inline unsigned get_dbmr10(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbmr10,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbmr10,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbmr10(unsigned val){
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static inline void set_dbmr10(unsigned val){
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asm volatile ( "movgs %0,dbmr10\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbmr10\n" : /* no outputs */ : "r" (val) );}
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static inline unsigned get_dbmr11(void){
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static inline unsigned get_dbmr11(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg dbmr11,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg dbmr11,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_dbmr11(unsigned val){
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static inline void set_dbmr11(unsigned val){
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asm volatile ( "movgs %0,dbmr11\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,dbmr11\n" : /* no outputs */ : "r" (val) );}
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// and here's the prototype. Which compiles, believe it or not.
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// and here's the prototype. Which compiles, believe it or not.
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static inline unsigned get_XXXX(void){
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static inline unsigned get_XXXX(void){
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unsigned retval;
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unsigned retval;
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asm volatile ( "movsg XXXX,%0\n" : "=r" (retval) : /* no inputs */ );
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asm volatile ( "movsg XXXX,%0\n" : "=r" (retval) : /* no inputs */ );
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return retval;}
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return retval;}
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static inline void set_XXXX(unsigned val){
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static inline void set_XXXX(unsigned val){
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asm volatile ( "movgs %0,XXXX\n" : /* no outputs */ : "r" (val) );}
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asm volatile ( "movgs %0,XXXX\n" : /* no outputs */ : "r" (val) );}
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// ------------------------------------------------------------------------
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// ------------------------------------------------------------------------
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// This is called in the same manner as exception_handler() in hal_misc.c
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// This is called in the same manner as exception_handler() in hal_misc.c
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// Comments compare and contrast what we do here.
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// Comments compare and contrast what we do here.
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static unsigned int saved_brr = 0;
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static unsigned int saved_brr = 0;
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void
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void
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break_handler(HAL_SavedRegisters *regs)
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break_handler(HAL_SavedRegisters *regs)
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{
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{
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unsigned int i, old_bpsr;
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unsigned int i, old_bpsr;
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// See if it an actual "break" instruction.
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// See if it an actual "break" instruction.
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i = get_brr();
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i = get_brr();
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saved_brr |= i; // do not lose previous state
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saved_brr |= i; // do not lose previous state
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// Acknowledge the trap, clear the "factor" (== cause)
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// Acknowledge the trap, clear the "factor" (== cause)
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set_brr( 0 );
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set_brr( 0 );
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// Now leave debug mode so that it's safe to run the stub code.
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// Now leave debug mode so that it's safe to run the stub code.
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// Unfortunately, leaving debug mode isn't a self-contained
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// Unfortunately, leaving debug mode isn't a self-contained
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// operation. The only means of doing it is with a "rett #1"
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// operation. The only means of doing it is with a "rett #1"
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// instruction, which will also restore the previous values of
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// instruction, which will also restore the previous values of
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// the ET and S status flags. We can massage the BPSR
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// the ET and S status flags. We can massage the BPSR
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// register so that the flags keep their current values, but
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// register so that the flags keep their current values, but
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// we need to save the old one first.
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// we need to save the old one first.
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i = old_bpsr = get_bpsr ();
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i = old_bpsr = get_bpsr ();
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i |= _BPSR_BS; // Stay in supervisor mode
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i |= _BPSR_BS; // Stay in supervisor mode
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i &= ~_BPSR_BET; // Keep traps disabled
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i &= ~_BPSR_BET; // Keep traps disabled
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set_bpsr (i);
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set_bpsr (i);
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HAL_FRV_EXIT_DEBUG_MODE();
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HAL_FRV_EXIT_DEBUG_MODE();
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// Only perturb this variable if stopping, not
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// Only perturb this variable if stopping, not
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// just for a break instruction.
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// just for a break instruction.
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_hal_registers = regs;
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_hal_registers = regs;
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// Continue with the standard mechanism:
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// Continue with the standard mechanism:
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__handle_exception();
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__handle_exception();
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// Go back into debug mode.
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// Go back into debug mode.
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HAL_FRV_ENTER_DEBUG_MODE();
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HAL_FRV_ENTER_DEBUG_MODE();
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// Restore the original BPSR register.
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// Restore the original BPSR register.
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set_bpsr (old_bpsr);
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set_bpsr (old_bpsr);
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return;
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return;
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}
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}
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// ------------------------------------------------------------------------
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// ------------------------------------------------------------------------
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// Now the routines to manipulate said hardware break and watchpoints.
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// Now the routines to manipulate said hardware break and watchpoints.
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int cyg_hal_plf_hw_breakpoint(int setflag, void *vaddr, int len)
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int cyg_hal_plf_hw_breakpoint(int setflag, void *vaddr, int len)
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{
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{
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unsigned int addr = (unsigned)vaddr;
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unsigned int addr = (unsigned)vaddr;
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unsigned int dcr;
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unsigned int dcr;
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unsigned int retcode = 0;
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unsigned int retcode = 0;
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HAL_FRV_ENTER_DEBUG_MODE();
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HAL_FRV_ENTER_DEBUG_MODE();
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dcr = get_dcr();
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dcr = get_dcr();
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// GDB manual suggests that idempotency is required, so first remove
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// GDB manual suggests that idempotency is required, so first remove
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// any identical BP in residence. Implements remove arm anyway.
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// any identical BP in residence. Implements remove arm anyway.
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if ( 0 != (dcr & (_DCR_IBE0 | _DCR_IBCE0)) &&
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if ( 0 != (dcr & (_DCR_IBE0 | _DCR_IBCE0)) &&
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get_ibar0() == addr )
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get_ibar0() == addr )
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dcr &=~(_DCR_IBE0 | _DCR_IBCE0);
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dcr &=~(_DCR_IBE0 | _DCR_IBCE0);
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else if ( 0 != (dcr & (_DCR_IBE1 | _DCR_IBCE1)) &&
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else if ( 0 != (dcr & (_DCR_IBE1 | _DCR_IBCE1)) &&
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get_ibar1() == addr )
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get_ibar1() == addr )
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dcr &=~(_DCR_IBE1 | _DCR_IBCE1);
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dcr &=~(_DCR_IBE1 | _DCR_IBCE1);
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else if ( 0 != (dcr & (_DCR_IBE2 | _DCR_IBCE2)) &&
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else if ( 0 != (dcr & (_DCR_IBE2 | _DCR_IBCE2)) &&
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get_ibar2() == addr )
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get_ibar2() == addr )
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dcr &=~(_DCR_IBE2 | _DCR_IBCE2);
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dcr &=~(_DCR_IBE2 | _DCR_IBCE2);
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else if ( 0 != (dcr & (_DCR_IBE3 | _DCR_IBCE3)) &&
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else if ( 0 != (dcr & (_DCR_IBE3 | _DCR_IBCE3)) &&
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get_ibar3() == addr )
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get_ibar3() == addr )
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dcr &=~(_DCR_IBE3 | _DCR_IBCE3);
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dcr &=~(_DCR_IBE3 | _DCR_IBCE3);
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else
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else
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retcode = -1;
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retcode = -1;
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if (setflag) {
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if (setflag) {
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retcode = 0; // it is OK really
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retcode = 0; // it is OK really
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if ( 0 == (dcr & (_DCR_IBE0 | _DCR_IBCE0)) ) {
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if ( 0 == (dcr & (_DCR_IBE0 | _DCR_IBCE0)) ) {
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set_ibar0(addr);
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set_ibar0(addr);
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dcr |= _DCR_IBE0;
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dcr |= _DCR_IBE0;
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}
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}
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else if ( 0 == (dcr & (_DCR_IBE1 | _DCR_IBCE1)) ) {
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else if ( 0 == (dcr & (_DCR_IBE1 | _DCR_IBCE1)) ) {
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set_ibar1(addr);
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set_ibar1(addr);
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dcr |= _DCR_IBE1;
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dcr |= _DCR_IBE1;
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}
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}
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else if ( 0 == (dcr & (_DCR_IBE2 | _DCR_IBCE2)) ) {
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else if ( 0 == (dcr & (_DCR_IBE2 | _DCR_IBCE2)) ) {
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set_ibar2(addr);
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set_ibar2(addr);
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dcr |= _DCR_IBE2;
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dcr |= _DCR_IBE2;
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}
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}
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else if ( 0 == (dcr & (_DCR_IBE3 | _DCR_IBCE3)) ) {
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else if ( 0 == (dcr & (_DCR_IBE3 | _DCR_IBCE3)) ) {
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set_ibar3(addr);
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set_ibar3(addr);
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dcr |= _DCR_IBE3;
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dcr |= _DCR_IBE3;
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}
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}
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else
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else
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retcode = -1;
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retcode = -1;
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}
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}
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|
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if ( 0 == retcode )
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if ( 0 == retcode )
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set_dcr(dcr);
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set_dcr(dcr);
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HAL_FRV_EXIT_DEBUG_MODE();
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HAL_FRV_EXIT_DEBUG_MODE();
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return retcode;
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return retcode;
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}
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}
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int cyg_hal_plf_hw_watchpoint(int setflag, void *vaddr, int len, int type)
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int cyg_hal_plf_hw_watchpoint(int setflag, void *vaddr, int len, int type)
|
{
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{
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unsigned int addr = (unsigned)vaddr;
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unsigned int addr = (unsigned)vaddr;
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unsigned int mode;
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unsigned int mode;
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unsigned int dcr;
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unsigned int dcr;
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unsigned int retcode = 0;
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unsigned int retcode = 0;
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unsigned long long mask;
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unsigned long long mask;
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unsigned int mask0, mask1;
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unsigned int mask0, mask1;
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int i;
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int i;
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|
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// Check the length fits within one block.
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// Check the length fits within one block.
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if ( ((~7) & (addr + len - 1)) != ((~7) & addr) )
|
if ( ((~7) & (addr + len - 1)) != ((~7) & addr) )
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return -1;
|
return -1;
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|
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// Assuming big-endian like the platform seems to be...
|
// Assuming big-endian like the platform seems to be...
|
|
|
// Get masks for the 8-byte span. 00 means enabled, ff means ignore a
|
// Get masks for the 8-byte span. 00 means enabled, ff means ignore a
|
// byte, which is why this looks funny at first glance.
|
// byte, which is why this looks funny at first glance.
|
mask = 0x00ffffffffffffffULL >> ((len - 1) << 3);
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mask = 0x00ffffffffffffffULL >> ((len - 1) << 3);
|
for (i = 0; i < (addr & 7); i++) {
|
for (i = 0; i < (addr & 7); i++) {
|
mask >>= 8;
|
mask >>= 8;
|
mask |= 0xff00000000000000ULL;
|
mask |= 0xff00000000000000ULL;
|
}
|
}
|
|
|
mask0 = mask >> 32;
|
mask0 = mask >> 32;
|
mask1 = mask & 0xffffffffULL;
|
mask1 = mask & 0xffffffffULL;
|
|
|
addr &=~7; // round to 8-byte block
|
addr &=~7; // round to 8-byte block
|
|
|
HAL_FRV_ENTER_DEBUG_MODE();
|
HAL_FRV_ENTER_DEBUG_MODE();
|
dcr = get_dcr();
|
dcr = get_dcr();
|
|
|
// GDB manual suggests that idempotency is required, so first remove
|
// GDB manual suggests that idempotency is required, so first remove
|
// any identical WP in residence. Implements remove arm anyway.
|
// any identical WP in residence. Implements remove arm anyway.
|
if ( 0 != (dcr & (7 * _DCR_DBASE0)) &&
|
if ( 0 != (dcr & (7 * _DCR_DBASE0)) &&
|
get_dbar0() == addr &&
|
get_dbar0() == addr &&
|
get_dbmr00() == mask0 && get_dbmr01() == mask1 )
|
get_dbmr00() == mask0 && get_dbmr01() == mask1 )
|
dcr &=~(7 * _DCR_DBASE0);
|
dcr &=~(7 * _DCR_DBASE0);
|
else if ( 0 != (dcr & (7 * _DCR_DBASE1)) &&
|
else if ( 0 != (dcr & (7 * _DCR_DBASE1)) &&
|
get_dbar1() == addr&&
|
get_dbar1() == addr&&
|
get_dbmr10() == mask0 && get_dbmr11() == mask1 )
|
get_dbmr10() == mask0 && get_dbmr11() == mask1 )
|
dcr &=~(7 * _DCR_DBASE1);
|
dcr &=~(7 * _DCR_DBASE1);
|
else
|
else
|
retcode = -1;
|
retcode = -1;
|
|
|
if (setflag) {
|
if (setflag) {
|
retcode = 0; // it is OK really
|
retcode = 0; // it is OK really
|
if (type == 2) mode = 2; // break on write
|
if (type == 2) mode = 2; // break on write
|
else if (type == 3) mode = 4; // break on read
|
else if (type == 3) mode = 4; // break on read
|
else if (type == 4) mode = 6; // break on any access
|
else if (type == 4) mode = 6; // break on any access
|
else {
|
else {
|
mode = 0; // actually add no enable at all.
|
mode = 0; // actually add no enable at all.
|
retcode = -1;
|
retcode = -1;
|
}
|
}
|
if ( 0 == (dcr & (7 * _DCR_DBASE0)) ) {
|
if ( 0 == (dcr & (7 * _DCR_DBASE0)) ) {
|
set_dbar0(addr);
|
set_dbar0(addr);
|
// Data and Mask 0,1 to zero (mask no bits/bytes)
|
// Data and Mask 0,1 to zero (mask no bits/bytes)
|
set_dbdr00(0); set_dbdr01(0); set_dbmr00(mask0); set_dbmr01(mask1);
|
set_dbdr00(0); set_dbdr01(0); set_dbmr00(mask0); set_dbmr01(mask1);
|
mode *= _DCR_DBASE0;
|
mode *= _DCR_DBASE0;
|
dcr |= mode;
|
dcr |= mode;
|
}
|
}
|
else if ( 0 == (dcr & (7 * _DCR_DBASE1)) ) {
|
else if ( 0 == (dcr & (7 * _DCR_DBASE1)) ) {
|
set_dbar1(addr);
|
set_dbar1(addr);
|
set_dbdr10(0); set_dbdr11(0); set_dbmr10(mask0); set_dbmr11(mask1);
|
set_dbdr10(0); set_dbdr11(0); set_dbmr10(mask0); set_dbmr11(mask1);
|
mode *= _DCR_DBASE1;
|
mode *= _DCR_DBASE1;
|
dcr |= mode;
|
dcr |= mode;
|
}
|
}
|
else
|
else
|
retcode = -1;
|
retcode = -1;
|
}
|
}
|
|
|
if ( 0 == retcode )
|
if ( 0 == retcode )
|
set_dcr(dcr);
|
set_dcr(dcr);
|
HAL_FRV_EXIT_DEBUG_MODE();
|
HAL_FRV_EXIT_DEBUG_MODE();
|
return retcode;
|
return retcode;
|
}
|
}
|
|
|
// Return indication of whether or not we stopped because of a
|
// Return indication of whether or not we stopped because of a
|
// watchpoint or hardware breakpoint. If stopped by a watchpoint,
|
// watchpoint or hardware breakpoint. If stopped by a watchpoint,
|
// also set '*data_addr_p' to the data address which triggered the
|
// also set '*data_addr_p' to the data address which triggered the
|
// watchpoint.
|
// watchpoint.
|
int cyg_hal_plf_is_stopped_by_hardware(void **data_addr_p)
|
int cyg_hal_plf_is_stopped_by_hardware(void **data_addr_p)
|
{
|
{
|
unsigned int brr;
|
unsigned int brr;
|
int retcode = HAL_STUB_HW_STOP_NONE;
|
int retcode = HAL_STUB_HW_STOP_NONE;
|
unsigned long long mask;
|
unsigned long long mask;
|
|
|
// There was a debug event. Check the BRR for details
|
// There was a debug event. Check the BRR for details
|
brr = saved_brr;
|
brr = saved_brr;
|
saved_brr = 0;
|
saved_brr = 0;
|
|
|
if ( brr & (_BRR_IB0 | _BRR_IB1 | _BRR_IB2 | _BRR_IB3) ) {
|
if ( brr & (_BRR_IB0 | _BRR_IB1 | _BRR_IB2 | _BRR_IB3) ) {
|
// then it was an instruction break
|
// then it was an instruction break
|
retcode = HAL_STUB_HW_STOP_BREAK;
|
retcode = HAL_STUB_HW_STOP_BREAK;
|
}
|
}
|
else if ( brr & (_BRR_DB0 | _BRR_DB1) ) {
|
else if ( brr & (_BRR_DB0 | _BRR_DB1) ) {
|
unsigned int addr, kind;
|
unsigned int addr, kind;
|
kind = get_dcr();
|
kind = get_dcr();
|
if ( brr & (_BRR_DB0) ) {
|
if ( brr & (_BRR_DB0) ) {
|
addr = get_dbar0();
|
addr = get_dbar0();
|
kind &= 7 * _DCR_DBASE0;
|
kind &= 7 * _DCR_DBASE0;
|
kind /= _DCR_DBASE0;
|
kind /= _DCR_DBASE0;
|
mask = (((unsigned long long)get_dbmr00())<<32) | (unsigned long long)get_dbmr01();
|
mask = (((unsigned long long)get_dbmr00())<<32) | (unsigned long long)get_dbmr01();
|
} else {
|
} else {
|
addr = get_dbar1();
|
addr = get_dbar1();
|
kind &= 7 * _DCR_DBASE1;
|
kind &= 7 * _DCR_DBASE1;
|
kind /= _DCR_DBASE1;
|
kind /= _DCR_DBASE1;
|
mask = (((unsigned long long)get_dbmr10())<<32) | (unsigned long long)get_dbmr11();
|
mask = (((unsigned long long)get_dbmr10())<<32) | (unsigned long long)get_dbmr11();
|
}
|
}
|
|
|
if ( data_addr_p ) {
|
if ( data_addr_p ) {
|
// Scan for a zero byte in the mask - this gives the true address.
|
// Scan for a zero byte in the mask - this gives the true address.
|
// 0123456789abcdef
|
// 0123456789abcdef
|
while ( 0 != (0xff00000000000000LLU & mask) ) {
|
while ( 0 != (0xff00000000000000LLU & mask) ) {
|
mask <<= 8;
|
mask <<= 8;
|
addr++;
|
addr++;
|
}
|
}
|
*data_addr_p = (void *)addr;
|
*data_addr_p = (void *)addr;
|
}
|
}
|
|
|
// Inverse of the mapping above in the "set" code.
|
// Inverse of the mapping above in the "set" code.
|
if (kind == 2) retcode = HAL_STUB_HW_STOP_WATCH;
|
if (kind == 2) retcode = HAL_STUB_HW_STOP_WATCH;
|
else if (kind == 6) retcode = HAL_STUB_HW_STOP_AWATCH;
|
else if (kind == 6) retcode = HAL_STUB_HW_STOP_AWATCH;
|
else if (kind == 4) retcode = HAL_STUB_HW_STOP_RWATCH;
|
else if (kind == 4) retcode = HAL_STUB_HW_STOP_RWATCH;
|
}
|
}
|
return retcode;
|
return retcode;
|
}
|
}
|
|
|
// ------------------------------------------------------------------------
|
// ------------------------------------------------------------------------
|
|
|
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
|
|
|
/*------------------------------------------------------------------------*/
|
/*------------------------------------------------------------------------*/
|
// EOF frv400_misc.c
|
// EOF frv400_misc.c
|
|
|
