OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [mips/] [mips32/] [v2_0/] [src/] [var_misc.c] - Diff between revs 27 and 174

Only display areas with differences | Details | Blame | View Log

Rev 27 Rev 174
//==========================================================================
//==========================================================================
//
//
//      var_misc.c
//      var_misc.c
//
//
//      HAL implementation miscellaneous functions
//      HAL implementation miscellaneous functions
//
//
//==========================================================================
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
//
// eCos is free software; you can redistribute it and/or modify it under
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
// Software Foundation; either version 2 or (at your option) any later version.
//
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
// for more details.
//
//
// You should have received a copy of the GNU General Public License along
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
//
// As a special exception, if other files instantiate templates or use macros
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
// in accordance with section (3) of the GNU General Public License.
//
//
// This exception does not invalidate any other reasons why a work based on
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
// this file might be covered by the GNU General Public License.
//
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//==========================================================================
//#####DESCRIPTIONBEGIN####
//#####DESCRIPTIONBEGIN####
//
//
// Author(s):    nickg
// Author(s):    nickg
// Contributors: nickg, jlarmour, dmoseley
// Contributors: nickg, jlarmour, dmoseley
// Date:         2000-07-14
// Date:         2000-07-14
// Purpose:      HAL miscellaneous functions
// Purpose:      HAL miscellaneous functions
// Description:  This file contains miscellaneous functions provided by the
// Description:  This file contains miscellaneous functions provided by the
//               HAL.
//               HAL.
//
//
//####DESCRIPTIONEND####
//####DESCRIPTIONEND####
//
//
//========================================================================*/
//========================================================================*/
 
 
#include <pkgconf/hal.h>
#include <pkgconf/hal.h>
 
 
#include <cyg/infra/cyg_type.h>         // Base types
#include <cyg/infra/cyg_type.h>         // Base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros
#include <cyg/infra/cyg_ass.h>          // assertion macros
 
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_intr.h>
 
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/var_arch.h>
#include <cyg/hal/var_arch.h>
#include <cyg/hal/plf_io.h>
#include <cyg/hal/plf_io.h>
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_cache.h>
 
 
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
// Array which stores the configured priority levels for the configured
// Array which stores the configured priority levels for the configured
// interrupts.
// interrupts.
 
 
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
 
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
 
 
void hal_variant_init(void)
void hal_variant_init(void)
{
{
}
}
 
 
/*
/*
 * Uncomment the following to allow for dynamic cache sizing.
 * Uncomment the following to allow for dynamic cache sizing.
 * Currently we are going to assume the exact part specified in the ecosconfig stuff.
 * Currently we are going to assume the exact part specified in the ecosconfig stuff.
 * Perhaps in the near future this can all be done dynamically.
 * Perhaps in the near future this can all be done dynamically.
 */
 */
/* define DYNAMIC_CACHE_SIZING */
/* define DYNAMIC_CACHE_SIZING */
 
 
#if 0
#if 0
#ifndef DYNAMIC_CACHE_SIZING
#ifndef DYNAMIC_CACHE_SIZING
#warning "                                                                           \n\
#warning "                                                                           \n\
STILL NEED TO IMPLEMENT DYNAMIC_CACHE_SIZING.                                        \n\
STILL NEED TO IMPLEMENT DYNAMIC_CACHE_SIZING.                                        \n\
ALSO, the HAL_PLATFORM_CPU/etc defines need to be dynamic.                           \n\
ALSO, the HAL_PLATFORM_CPU/etc defines need to be dynamic.                           \n\
ALSO, need to do big endian stuff as well.                                           \n\
ALSO, need to do big endian stuff as well.                                           \n\
Determine if network debug is necessary.                                             \n\
Determine if network debug is necessary.                                             \n\
Remove MIPS memc_init code"
Remove MIPS memc_init code"
#endif
#endif
#endif
#endif
 
 
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
// Initialize the caches
// Initialize the caches
 
 
int hal_init_icache(unsigned long config1_val)
int hal_init_icache(unsigned long config1_val)
{
{
#ifdef DYNAMIC_CACHE_SIZING
#ifdef DYNAMIC_CACHE_SIZING
  int icache_linesize, icache_assoc, icache_sets, icache_lines, icache_size;
  int icache_linesize, icache_assoc, icache_sets, icache_lines, icache_size;
  unsigned long cache_addr;
  unsigned long cache_addr;
 
 
  switch (config1_val & CONFIG1_IL)
  switch (config1_val & CONFIG1_IL)
    {
    {
    case CONFIG1_ICACHE_LINE_SIZE_16_BYTES: icache_linesize = 16;      break;
    case CONFIG1_ICACHE_LINE_SIZE_16_BYTES: icache_linesize = 16;      break;
    case CONFIG1_ICACHE_NOT_PRESET:         return -1;                 break;
    case CONFIG1_ICACHE_NOT_PRESET:         return -1;                 break;
    default:      /* Error */               return -1;                 break;
    default:      /* Error */               return -1;                 break;
    }
    }
 
 
  switch (config1_val & CONFIG1_IA)
  switch (config1_val & CONFIG1_IA)
    {
    {
    case CONFIG1_ICACHE_DIRECT_MAPPED:      icache_assoc = 1;          break;
    case CONFIG1_ICACHE_DIRECT_MAPPED:      icache_assoc = 1;          break;
    case CONFIG1_ICACHE_2_WAY:              icache_assoc = 2;          break;
    case CONFIG1_ICACHE_2_WAY:              icache_assoc = 2;          break;
    case CONFIG1_ICACHE_3_WAY:              icache_assoc = 3;          break;
    case CONFIG1_ICACHE_3_WAY:              icache_assoc = 3;          break;
    case CONFIG1_ICACHE_4_WAY:              icache_assoc = 4;          break;
    case CONFIG1_ICACHE_4_WAY:              icache_assoc = 4;          break;
    default:      /* Error */               return -1;                 break;
    default:      /* Error */               return -1;                 break;
    }
    }
 
 
  switch (config1_val & CONFIG1_IS)
  switch (config1_val & CONFIG1_IS)
    {
    {
    case CONFIG1_ICACHE_64_SETS_PER_WAY:    icache_sets = 64;          break;
    case CONFIG1_ICACHE_64_SETS_PER_WAY:    icache_sets = 64;          break;
    case CONFIG1_ICACHE_128_SETS_PER_WAY:   icache_sets = 128;         break;
    case CONFIG1_ICACHE_128_SETS_PER_WAY:   icache_sets = 128;         break;
    case CONFIG1_ICACHE_256_SETS_PER_WAY:   icache_sets = 256;         break;
    case CONFIG1_ICACHE_256_SETS_PER_WAY:   icache_sets = 256;         break;
    default:      /* Error */               return -1;                 break;
    default:      /* Error */               return -1;                 break;
    }
    }
 
 
  icache_lines = icache_sets * icache_assoc;
  icache_lines = icache_sets * icache_assoc;
  icache_size = icache_lines * icache_linesize;
  icache_size = icache_lines * icache_linesize;
#endif /* DYNAMIC_CACHE_SIZING */
#endif /* DYNAMIC_CACHE_SIZING */
 
 
  /*
  /*
   * Reset does not invalidate the cache so let's do so now.
   * Reset does not invalidate the cache so let's do so now.
   */
   */
  HAL_ICACHE_INVALIDATE_ALL();
  HAL_ICACHE_INVALIDATE_ALL();
 
 
#ifdef DYNAMIC_CACHE_SIZING
#ifdef DYNAMIC_CACHE_SIZING
  return icache_size;
  return icache_size;
#else
#else
  return HAL_ICACHE_SIZE;
  return HAL_ICACHE_SIZE;
#endif
#endif
}
}
 
 
int hal_init_dcache(unsigned long config1_val)
int hal_init_dcache(unsigned long config1_val)
{
{
#ifdef DYNAMIC_CACHE_SIZING
#ifdef DYNAMIC_CACHE_SIZING
  int dcache_linesize, dcache_assoc, dcache_sets, dcache_lines, dcache_size;
  int dcache_linesize, dcache_assoc, dcache_sets, dcache_lines, dcache_size;
 
 
  switch (config1_val & CONFIG1_DL)
  switch (config1_val & CONFIG1_DL)
    {
    {
    case CONFIG1_DCACHE_LINE_SIZE_16_BYTES: dcache_linesize = 16;      break;
    case CONFIG1_DCACHE_LINE_SIZE_16_BYTES: dcache_linesize = 16;      break;
    case CONFIG1_DCACHE_NOT_PRESET:         return -1;                 break;
    case CONFIG1_DCACHE_NOT_PRESET:         return -1;                 break;
    default:      /* Error */               return -1;                 break;
    default:      /* Error */               return -1;                 break;
    }
    }
 
 
  switch (config1_val & CONFIG1_DA)
  switch (config1_val & CONFIG1_DA)
    {
    {
    case CONFIG1_DCACHE_DIRECT_MAPPED:      dcache_assoc = 1;          break;
    case CONFIG1_DCACHE_DIRECT_MAPPED:      dcache_assoc = 1;          break;
    case CONFIG1_DCACHE_2_WAY:              dcache_assoc = 2;          break;
    case CONFIG1_DCACHE_2_WAY:              dcache_assoc = 2;          break;
    case CONFIG1_DCACHE_3_WAY:              dcache_assoc = 3;          break;
    case CONFIG1_DCACHE_3_WAY:              dcache_assoc = 3;          break;
    case CONFIG1_DCACHE_4_WAY:              dcache_assoc = 4;          break;
    case CONFIG1_DCACHE_4_WAY:              dcache_assoc = 4;          break;
    default:      /* Error */               return -1;                 break;
    default:      /* Error */               return -1;                 break;
    }
    }
 
 
  switch (config1_val & CONFIG1_DS)
  switch (config1_val & CONFIG1_DS)
    {
    {
    case CONFIG1_DCACHE_64_SETS_PER_WAY:    dcache_sets = 64;          break;
    case CONFIG1_DCACHE_64_SETS_PER_WAY:    dcache_sets = 64;          break;
    case CONFIG1_DCACHE_128_SETS_PER_WAY:   dcache_sets = 128;         break;
    case CONFIG1_DCACHE_128_SETS_PER_WAY:   dcache_sets = 128;         break;
    case CONFIG1_DCACHE_256_SETS_PER_WAY:   dcache_sets = 256;         break;
    case CONFIG1_DCACHE_256_SETS_PER_WAY:   dcache_sets = 256;         break;
    default:      /* Error */               return -1;                 break;
    default:      /* Error */               return -1;                 break;
    }
    }
 
 
  dcache_lines = dcache_sets * dcache_assoc;
  dcache_lines = dcache_sets * dcache_assoc;
  dcache_size = dcache_lines * dcache_linesize;
  dcache_size = dcache_lines * dcache_linesize;
#endif /* DYNAMIC_CACHE_SIZING */
#endif /* DYNAMIC_CACHE_SIZING */
 
 
  /*
  /*
   * Reset does not invalidate the cache so let's do so now.
   * Reset does not invalidate the cache so let's do so now.
   */
   */
  HAL_DCACHE_INVALIDATE_ALL();
  HAL_DCACHE_INVALIDATE_ALL();
 
 
#ifdef DYNAMIC_CACHE_SIZING
#ifdef DYNAMIC_CACHE_SIZING
  return dcache_size;
  return dcache_size;
#else
#else
  return HAL_DCACHE_SIZE;
  return HAL_DCACHE_SIZE;
#endif
#endif
}
}
 
 
void hal_c_cache_init(unsigned long config1_val)
void hal_c_cache_init(unsigned long config1_val)
{
{
  volatile unsigned val;
  volatile unsigned val;
 
 
  if (hal_init_icache(config1_val) == -1)
  if (hal_init_icache(config1_val) == -1)
    {
    {
        /* Error */
        /* Error */
        ;
        ;
    }
    }
 
 
  if (hal_init_dcache(config1_val) == -1)
  if (hal_init_dcache(config1_val) == -1)
    {
    {
        /* Error */
        /* Error */
        ;
        ;
    }
    }
 
 
  // enable cached KSEG0
  // enable cached KSEG0
  asm volatile("mfc0 %0,$16;" : "=r"(val));
  asm volatile("mfc0 %0,$16;" : "=r"(val));
  val &= ~3;
  val &= ~3;
  asm volatile("mtc0 %0,$16;" : : "r"(val));
  asm volatile("mtc0 %0,$16;" : : "r"(val));
}
}
 
 
void hal_icache_sync(void)
void hal_icache_sync(void)
{
{
    HAL_ICACHE_INVALIDATE_ALL();
    HAL_ICACHE_INVALIDATE_ALL();
}
}
 
 
void hal_dcache_sync(void)
void hal_dcache_sync(void)
{
{
    HAL_DCACHE_INVALIDATE_ALL();
    HAL_DCACHE_INVALIDATE_ALL();
}
}
 
 
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* End of var_misc.c                                                      */
/* End of var_misc.c                                                      */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.