#ifndef CYGONCE_HAL_PLATFORM_INC
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#ifndef CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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##=============================================================================
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##=============================================================================
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##
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##
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## platform.inc
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## platform.inc
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##
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##
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## DDB-VRC4373 board assembler header file
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## DDB-VRC4373 board assembler header file
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##
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##
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##=============================================================================
|
##=============================================================================
|
#####ECOSGPLCOPYRIGHTBEGIN####
|
#####ECOSGPLCOPYRIGHTBEGIN####
|
## -------------------------------------------
|
## -------------------------------------------
|
## This file is part of eCos, the Embedded Configurable Operating System.
|
## This file is part of eCos, the Embedded Configurable Operating System.
|
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
##
|
##
|
## eCos is free software; you can redistribute it and/or modify it under
|
## eCos is free software; you can redistribute it and/or modify it under
|
## the terms of the GNU General Public License as published by the Free
|
## the terms of the GNU General Public License as published by the Free
|
## Software Foundation; either version 2 or (at your option) any later version.
|
## Software Foundation; either version 2 or (at your option) any later version.
|
##
|
##
|
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
## for more details.
|
## for more details.
|
##
|
##
|
## You should have received a copy of the GNU General Public License along
|
## You should have received a copy of the GNU General Public License along
|
## with eCos; if not, write to the Free Software Foundation, Inc.,
|
## with eCos; if not, write to the Free Software Foundation, Inc.,
|
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
##
|
##
|
## As a special exception, if other files instantiate templates or use macros
|
## As a special exception, if other files instantiate templates or use macros
|
## or inline functions from this file, or you compile this file and link it
|
## or inline functions from this file, or you compile this file and link it
|
## with other works to produce a work based on this file, this file does not
|
## with other works to produce a work based on this file, this file does not
|
## by itself cause the resulting work to be covered by the GNU General Public
|
## by itself cause the resulting work to be covered by the GNU General Public
|
## License. However the source code for this file must still be made available
|
## License. However the source code for this file must still be made available
|
## in accordance with section (3) of the GNU General Public License.
|
## in accordance with section (3) of the GNU General Public License.
|
##
|
##
|
## This exception does not invalidate any other reasons why a work based on
|
## This exception does not invalidate any other reasons why a work based on
|
## this file might be covered by the GNU General Public License.
|
## this file might be covered by the GNU General Public License.
|
##
|
##
|
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
## at http://sources.redhat.com/ecos/ecos-license/
|
## at http://sources.redhat.com/ecos/ecos-license/
|
## -------------------------------------------
|
## -------------------------------------------
|
#####ECOSGPLCOPYRIGHTEND####
|
#####ECOSGPLCOPYRIGHTEND####
|
##=============================================================================
|
##=============================================================================
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#######DESCRIPTIONBEGIN####
|
#######DESCRIPTIONBEGIN####
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##
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##
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## Author(s): nickg
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## Author(s): nickg
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## Contributors: nickg
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## Contributors: nickg
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## Date: 1999-04-06
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## Date: 1999-04-06
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## Purpose: VRC4373 board definitions.
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## Purpose: VRC4373 board definitions.
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## Description: This file contains various definitions and macros that are
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the VRC4373 board.
|
## useful for writing assembly code for the VRC4373 board.
|
## Usage:
|
## Usage:
|
## #include
|
## #include
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## ...
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## ...
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##
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##
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##
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##
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######DESCRIPTIONEND####
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######DESCRIPTIONEND####
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##
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##
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##=============================================================================
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##=============================================================================
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|
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#include
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#include
|
|
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##-----------------------------------------------------------------------------
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##-----------------------------------------------------------------------------
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## VRC4372 registers
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## VRC4372 registers
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#define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000
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#define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220)
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#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220)
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|
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##-----------------------------------------------------------------------------
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##-----------------------------------------------------------------------------
|
## configure the architecture HAL to define the right things.
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## configure the architecture HAL to define the right things.
|
|
|
## ISR tables are defined in platform.S
|
## ISR tables are defined in platform.S
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#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
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#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
|
|
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## VSR table is at a fixed RAM address defined by the linker script
|
## VSR table is at a fixed RAM address defined by the linker script
|
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
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#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
|
|
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##-----------------------------------------------------------------------------
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##-----------------------------------------------------------------------------
|
|
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#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON)
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#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON)
|
|
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## Initial SR value for use with PMON:
|
## Initial SR value for use with PMON:
|
## CP0 usable
|
## CP0 usable
|
## Vectors to RAM
|
## Vectors to RAM
|
## All hw ints disabled
|
## All hw ints disabled
|
#define INITIAL_SR_PLF 0x10000000
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#define INITIAL_SR_PLF 0x10000000
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|
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#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
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#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
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|
|
## Initial SR value for use with GDB stubs:
|
## Initial SR value for use with GDB stubs:
|
## CP0 and CP1 usable
|
## CP0 and CP1 usable
|
## FP registers are 64 bit
|
## FP registers are 64 bit
|
## Vectors to RAM
|
## Vectors to RAM
|
## All hw ints disabled
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## All hw ints disabled
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#define INITIAL_SR_PLF 0x34000000
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#define INITIAL_SR_PLF 0x34000000
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|
|
#else
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#else
|
|
|
## Initial SR value for use standalone:
|
## Initial SR value for use standalone:
|
## CP0 usable
|
## CP0 usable
|
## Vectors to RAM
|
## Vectors to RAM
|
## All hw ints disabled
|
## All hw ints disabled
|
#define INITIAL_SR_PLF 0x10000000
|
#define INITIAL_SR_PLF 0x10000000
|
|
|
#endif
|
#endif
|
|
|
#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
|
## Load Address and Relocate. This macro is used in code that may be
|
## Load Address and Relocate. This macro is used in code that may be
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## linked to execute out of RAM but is actually executed from ROM. The
|
## linked to execute out of RAM but is actually executed from ROM. The
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## code that initializes the memory controller and copies the ROM
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## code that initializes the memory controller and copies the ROM
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## contents to RAM must work in this way, for example. This macro is used
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## contents to RAM must work in this way, for example. This macro is used
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## in place of an "la" macro instruction when loading code and data
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## in place of an "la" macro instruction when loading code and data
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## addresses. There are two versions of the macro here. The first
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## addresses. There are two versions of the macro here. The first
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## assumes that we are executing in the ROM space at 0xbfc00000 and are
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## assumes that we are executing in the ROM space at 0xbfc00000 and are
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## linked to run in the RAM space at 0x80000000. It simply adds the
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## linked to run in the RAM space at 0x80000000. It simply adds the
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## difference between the two to the loaded address. The second is more
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## difference between the two to the loaded address. The second is more
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## code, but will execute correctly at either location since it
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## code, but will execute correctly at either location since it
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## calculates the difference at runtime. The second variant is enabled
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## calculates the difference at runtime. The second variant is enabled
|
## by default.
|
## by default.
|
|
|
|
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#ifdef CYG_HAL_STARTUP_ROMRAM
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#ifdef CYG_HAL_STARTUP_ROMRAM
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|
|
#if 0
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#if 0
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.macro lar reg,addr
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.macro lar reg,addr
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.set noat
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.set noat
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la \reg,\addr
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la \reg,\addr
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la $at,0x3fc00000
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la $at,0x3fc00000
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addu \reg,\reg,$at
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addu \reg,\reg,$at
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.set at
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.set at
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.endm
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.endm
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#else
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#else
|
.macro lar reg,addr
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.macro lar reg,addr
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.set noat
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.set noat
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move $at,ra # save ra
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move $at,ra # save ra
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la \reg,\addr # get address into register
|
la \reg,\addr # get address into register
|
la ra,x\@ # get linked address of label
|
la ra,x\@ # get linked address of label
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subu \reg,\reg,ra # subtract it from value
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subu \reg,\reg,ra # subtract it from value
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bal x\@ # branch and link to label
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bal x\@ # branch and link to label
|
nop # to get current actual address
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nop # to get current actual address
|
x\@:
|
x\@:
|
addu \reg,\reg,ra # add actual address
|
addu \reg,\reg,ra # add actual address
|
move ra,$at # restore ra
|
move ra,$at # restore ra
|
.set at
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.set at
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.endm
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.endm
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|
|
#endif
|
#endif
|
|
|
#define CYGPKG_HAL_MIPS_LAR_DEFINED
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#define CYGPKG_HAL_MIPS_LAR_DEFINED
|
|
|
#endif
|
#endif
|
|
|
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
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# MMU macros.
|
# MMU macros.
|
# The MMU must be set up on this board before we can access any external devices,
|
# The MMU must be set up on this board before we can access any external devices,
|
# including the memory controller, so we have no RAM to work with yet.
|
# including the memory controller, so we have no RAM to work with yet.
|
# Since the setup code must work only in registers, we do not do a subroutine
|
# Since the setup code must work only in registers, we do not do a subroutine
|
# linkage here, instead the setup code knows to jump back here when finished.
|
# linkage here, instead the setup code knows to jump back here when finished.
|
|
|
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
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#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
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|
|
.macro hal_mmu_init
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.macro hal_mmu_init
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.extern hal_mmu_setup
|
.extern hal_mmu_setup
|
lar k0,hal_mmu_setup
|
lar k0,hal_mmu_setup
|
jr k0
|
jr k0
|
nop
|
nop
|
.global hal_mmu_setup_return
|
.global hal_mmu_setup_return
|
hal_mmu_setup_return:
|
hal_mmu_setup_return:
|
.endm
|
.endm
|
|
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#define CYGPKG_HAL_MIPS_MMU_DEFINED
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#define CYGPKG_HAL_MIPS_MMU_DEFINED
|
|
|
#endif
|
#endif
|
|
|
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
# MEMC macros.
|
# MEMC macros.
|
#
|
#
|
|
|
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
|
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
|
|
|
.macro hal_memc_init
|
.macro hal_memc_init
|
.extern hal_memc_setup
|
.extern hal_memc_setup
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lar k0,hal_memc_setup
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lar k0,hal_memc_setup
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jalr k0
|
jalr k0
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nop
|
nop
|
|
|
#if defined(CYG_HAL_STARTUP_ROMRAM)
|
#if defined(CYG_HAL_STARTUP_ROMRAM)
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# Having got the RAM working, we must now relocate the Entire
|
# Having got the RAM working, we must now relocate the Entire
|
# ROM into it and then continue execution from RAM.
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# ROM into it and then continue execution from RAM.
|
|
|
la t0,reset_vector # dest addr
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la t0,reset_vector # dest addr
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lar t1,reset_vector # source addr
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lar t1,reset_vector # source addr
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la t3,__ram_data_end # end dest addr
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la t3,__ram_data_end # end dest addr
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1:
|
1:
|
lw v0,0(t1) # get word
|
lw v0,0(t1) # get word
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sw v0,0(t0) # write word
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sw v0,0(t0) # write word
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addiu t1,t1,4
|
addiu t1,t1,4
|
addiu t0,t0,4
|
addiu t0,t0,4
|
bne t0,t3,1b
|
bne t0,t3,1b
|
nop
|
nop
|
|
|
la v0,2f # RAM address to go to
|
la v0,2f # RAM address to go to
|
jr v0
|
jr v0
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nop
|
nop
|
2:
|
2:
|
# We are now executing out of RAM!
|
# We are now executing out of RAM!
|
#endif
|
#endif
|
|
|
.endm
|
.endm
|
|
|
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
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#define CYGPKG_HAL_MIPS_MEMC_DEFINED
|
|
|
#endif
|
#endif
|
|
|
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
# Interrupt controller initialization.
|
# Interrupt controller initialization.
|
|
|
# initialize all interrupts to disabled
|
# initialize all interrupts to disabled
|
.macro hal_intc_init
|
.macro hal_intc_init
|
mfc0 v0,status
|
mfc0 v0,status
|
nop
|
nop
|
la v1,0xFFFF00FF
|
la v1,0xFFFF00FF
|
and v0,v0,v1 # clear the IntMask bits
|
and v0,v0,v1 # clear the IntMask bits
|
ori v0,v0,0x3800 # set 3 IPL bits
|
ori v0,v0,0x3800 # set 3 IPL bits
|
mtc0 v0,status
|
mtc0 v0,status
|
nop
|
nop
|
nop
|
nop
|
nop
|
nop
|
# mask them all in the VRC4372 interrupt controller too,
|
# mask them all in the VRC4372 interrupt controller too,
|
# and write zeros to the status registers to clear any
|
# and write zeros to the status registers to clear any
|
# pending interrupts.
|
# pending interrupts.
|
la v0,CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0
|
la v0,CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0
|
sw zero,0(v0)
|
sw zero,0(v0)
|
sw zero,4(v0)
|
sw zero,4(v0)
|
sw zero,8(v0)
|
sw zero,8(v0)
|
sw zero,12(v0)
|
sw zero,12(v0)
|
sw zero,16(v0)
|
sw zero,16(v0)
|
sw zero,20(v0)
|
sw zero,20(v0)
|
.endm
|
.endm
|
|
|
#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
|
#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
|
|
|
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
# Interrupt Translator.
|
# Interrupt Translator.
|
# This translates an interrupt number into an ISR table offset. Vector 0
|
# This translates an interrupt number into an ISR table offset. Vector 0
|
# contains a special ISR for dealing with spurious interrupts from the
|
# contains a special ISR for dealing with spurious interrupts from the
|
# Vrc437x, and vectors 1-3 contain springboards, so we chain via vector 4.
|
# Vrc437x, and vectors 1-3 contain springboards, so we chain via vector 4.
|
# This macro translates interrupt 0 to vector 0 and all others to vector 4.
|
# This macro translates interrupt 0 to vector 0 and all others to vector 4.
|
|
|
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
|
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
|
.macro hal_intc_translate inum,vnum
|
.macro hal_intc_translate inum,vnum
|
beqz \inum,1f # jump if interrupt is zero
|
beqz \inum,1f # jump if interrupt is zero
|
move v0,zero # set v0=0 in delay slot
|
move v0,zero # set v0=0 in delay slot
|
addi v0,v0,4 # non zero vector, inc v0
|
addi v0,v0,4 # non zero vector, inc v0
|
1: move \vnum,v0 # store 0 or 4 in vnum
|
1: move \vnum,v0 # store 0 or 4 in vnum
|
.endm
|
.endm
|
#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
|
#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
|
#endif
|
#endif
|
#endif
|
#endif
|
|
|
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
# Monitor initialization.
|
# Monitor initialization.
|
|
|
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
|
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
|
|
|
|
|
.macro hal_mon_init
|
.macro hal_mon_init
|
|
|
hal_mon_copy_trampoline
|
hal_mon_copy_trampoline
|
|
|
hal_mon_init_vsr_table
|
hal_mon_init_vsr_table
|
|
|
.endm
|
.endm
|
|
|
|
|
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON)
|
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON)
|
|
|
# Copy the other_vector trampoline code into the RAM
|
# Copy the other_vector trampoline code into the RAM
|
# area so we intercept all interrupts.
|
# area so we intercept all interrupts.
|
|
|
.macro hal_mon_copy_trampoline
|
.macro hal_mon_copy_trampoline
|
la a0,other_vector
|
la a0,other_vector
|
la a1,other_vector_end
|
la a1,other_vector_end
|
la t0,0xa0000180
|
la t0,0xa0000180
|
1:
|
1:
|
lw v0,0(a0)
|
lw v0,0(a0)
|
sw v0,0(t0)
|
sw v0,0(t0)
|
addiu a0,a0,4
|
addiu a0,a0,4
|
bne a0,a1,1b
|
bne a0,a1,1b
|
addiu t0,t0,4
|
addiu t0,t0,4
|
.endm
|
.endm
|
|
|
|
|
# plant a pointer to the breakpoint springboard into the
|
# plant a pointer to the breakpoint springboard into the
|
# correct vsr table slot.
|
# correct vsr table slot.
|
|
|
.macro hal_mon_init_vsr_table
|
.macro hal_mon_init_vsr_table
|
.extern hal_breakpoint_springboard
|
.extern hal_breakpoint_springboard
|
la v1,hal_vsr_table
|
la v1,hal_vsr_table
|
|
|
# Plant the interrupt VSR
|
# Plant the interrupt VSR
|
la v0,__default_interrupt_vsr
|
la v0,__default_interrupt_vsr
|
sw v0,(0*4)(v1)
|
sw v0,(0*4)(v1)
|
|
|
# And the breakpoint VSR
|
# And the breakpoint VSR
|
la v0,hal_breakpoint_springboard
|
la v0,hal_breakpoint_springboard
|
sw v0,(9*4)(v1)
|
sw v0,(9*4)(v1)
|
|
|
# Temporarily also plant all the others, so all exceptions
|
# Temporarily also plant all the others, so all exceptions
|
# go to PMON.
|
# go to PMON.
|
sw v0,(4*4)(v1)
|
sw v0,(4*4)(v1)
|
sw v0,(5*4)(v1)
|
sw v0,(5*4)(v1)
|
sw v0,(6*4)(v1)
|
sw v0,(6*4)(v1)
|
sw v0,(7*4)(v1)
|
sw v0,(7*4)(v1)
|
sw v0,(8*4)(v1)
|
sw v0,(8*4)(v1)
|
sw v0,(10*4)(v1)
|
sw v0,(10*4)(v1)
|
sw v0,(11*4)(v1)
|
sw v0,(11*4)(v1)
|
sw v0,(12*4)(v1)
|
sw v0,(12*4)(v1)
|
sw v0,(13*4)(v1)
|
sw v0,(13*4)(v1)
|
sw v0,(14*4)(v1)
|
sw v0,(14*4)(v1)
|
sw v0,(15*4)(v1)
|
sw v0,(15*4)(v1)
|
|
|
|
|
.endm
|
.endm
|
|
|
#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
|
#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
|
|
|
# The stubs have a trampoline of their own installed which
|
# The stubs have a trampoline of their own installed which
|
# already goes through the VSR table.
|
# already goes through the VSR table.
|
|
|
.macro hal_mon_copy_trampoline
|
.macro hal_mon_copy_trampoline
|
.endm
|
.endm
|
|
|
# plant a pointer to the interrupt VSR handler in the
|
# plant a pointer to the interrupt VSR handler in the
|
# correct vsr table slot. Leave the rest for the monitor.
|
# correct vsr table slot. Leave the rest for the monitor.
|
|
|
.macro hal_mon_init_vsr_table
|
.macro hal_mon_init_vsr_table
|
la v0,__default_interrupt_vsr
|
la v0,__default_interrupt_vsr
|
la v1,hal_vsr_table
|
la v1,hal_vsr_table
|
sw v0,(0*4)(v1)
|
sw v0,(0*4)(v1)
|
|
|
# plant a pointer to our own bus error handler. See the
|
# plant a pointer to our own bus error handler. See the
|
# comments in platform.S.
|
# comments in platform.S.
|
.extern hal_bus_error_vsr
|
.extern hal_bus_error_vsr
|
la v0,hal_bus_error_vsr
|
la v0,hal_bus_error_vsr
|
sw v0,(7*4)(v1)
|
sw v0,(7*4)(v1)
|
|
|
.endm
|
.endm
|
|
|
#else
|
#else
|
# The other_vector trampoline is already installed as part of
|
# The other_vector trampoline is already installed as part of
|
# the executable image. However, the TLB exception is, in RAM
|
# the executable image. However, the TLB exception is, in RAM
|
# in the analogous place to the reset vector in ROM. In a
|
# in the analogous place to the reset vector in ROM. In a
|
# ROM or ROMRAM startup we need to copy it into place.
|
# ROM or ROMRAM startup we need to copy it into place.
|
|
|
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
|
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
|
.macro hal_mon_copy_trampoline
|
.macro hal_mon_copy_trampoline
|
la a0,utlb_vector
|
la a0,utlb_vector
|
la a1,utlb_vector_end
|
la a1,utlb_vector_end
|
la t0,0xa0000000
|
la t0,0xa0000000
|
1:
|
1:
|
lw v0,0(a0)
|
lw v0,0(a0)
|
sw v0,0(t0)
|
sw v0,0(t0)
|
sw v0,0x80(t0)
|
sw v0,0x80(t0)
|
addiu a0,a0,4
|
addiu a0,a0,4
|
bne a0,a1,1b
|
bne a0,a1,1b
|
addiu t0,t0,4
|
addiu t0,t0,4
|
#if defined(CYG_HAL_STARTUP_ROM)
|
#if defined(CYG_HAL_STARTUP_ROM)
|
la a0,other_vector
|
la a0,other_vector
|
la a1,other_vector_end
|
la a1,other_vector_end
|
la t0,0xa0000180
|
la t0,0xa0000180
|
1:
|
1:
|
lw v0,0(a0)
|
lw v0,0(a0)
|
sw v0,0(t0)
|
sw v0,0(t0)
|
addiu a0,a0,4
|
addiu a0,a0,4
|
bne a0,a1,1b
|
bne a0,a1,1b
|
addiu t0,t0,4
|
addiu t0,t0,4
|
#endif
|
#endif
|
.endm
|
.endm
|
#else
|
#else
|
.macro hal_mon_copy_trampoline
|
.macro hal_mon_copy_trampoline
|
.endm
|
.endm
|
#endif
|
#endif
|
|
|
# Fill the VSR table with the default VSRs.
|
# Fill the VSR table with the default VSRs.
|
# If we contain the stubs, the default VSR will pass
|
# If we contain the stubs, the default VSR will pass
|
# exceptions on to the stubs.
|
# exceptions on to the stubs.
|
|
|
.macro hal_mon_init_vsr_table
|
.macro hal_mon_init_vsr_table
|
la v0,__default_exception_vsr
|
la v0,__default_exception_vsr
|
la v1,hal_vsr_table
|
la v1,hal_vsr_table
|
|
|
sw v0,(1*4)(v1)
|
sw v0,(1*4)(v1)
|
sw v0,(2*4)(v1)
|
sw v0,(2*4)(v1)
|
sw v0,(3*4)(v1)
|
sw v0,(3*4)(v1)
|
sw v0,(4*4)(v1)
|
sw v0,(4*4)(v1)
|
sw v0,(5*4)(v1)
|
sw v0,(5*4)(v1)
|
sw v0,(6*4)(v1)
|
sw v0,(6*4)(v1)
|
# sw v0,(7*4)(v1) # Bus error
|
# sw v0,(7*4)(v1) # Bus error
|
sw v0,(8*4)(v1)
|
sw v0,(8*4)(v1)
|
sw v0,(9*4)(v1)
|
sw v0,(9*4)(v1)
|
sw v0,(10*4)(v1)
|
sw v0,(10*4)(v1)
|
sw v0,(11*4)(v1)
|
sw v0,(11*4)(v1)
|
sw v0,(12*4)(v1)
|
sw v0,(12*4)(v1)
|
sw v0,(13*4)(v1)
|
sw v0,(13*4)(v1)
|
sw v0,(14*4)(v1)
|
sw v0,(14*4)(v1)
|
sw v0,(15*4)(v1)
|
sw v0,(15*4)(v1)
|
sw v0,(23*4)(v1)
|
sw v0,(23*4)(v1)
|
sw v0,(24*4)(v1)
|
sw v0,(24*4)(v1)
|
# sw v0,(32*4)(v1) # debug
|
# sw v0,(32*4)(v1) # debug
|
sw v0,(33*4)(v1) # utlb
|
sw v0,(33*4)(v1) # utlb
|
sw v0,(34*4)(v1) # nmi
|
sw v0,(34*4)(v1) # nmi
|
|
|
la v0,__default_interrupt_vsr
|
la v0,__default_interrupt_vsr
|
sw v0,(0*4)(v1)
|
sw v0,(0*4)(v1)
|
|
|
# plant a pointer to our own bus error handler. See the
|
# plant a pointer to our own bus error handler. See the
|
# comments in platform.S.
|
# comments in platform.S.
|
.extern hal_bus_error_vsr
|
.extern hal_bus_error_vsr
|
la v0,hal_bus_error_vsr
|
la v0,hal_bus_error_vsr
|
sw v0,(7*4)(v1)
|
sw v0,(7*4)(v1)
|
|
|
.endm
|
.endm
|
|
|
#endif
|
#endif
|
|
|
|
|
#define CYGPKG_HAL_MIPS_MON_DEFINED
|
#define CYGPKG_HAL_MIPS_MON_DEFINED
|
|
|
#endif
|
#endif
|
|
|
#------------------------------------------------------------------------------
|
#------------------------------------------------------------------------------
|
# Diagnostic macros
|
# Diagnostic macros
|
|
|
|
|
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
|
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
|
|
|
#if 0
|
#if 0
|
|
|
# This code generates characters and hex values to a
|
# This code generates characters and hex values to a
|
# Grammar Engine PromICE AI interface.
|
# Grammar Engine PromICE AI interface.
|
|
|
#define AILOC 0xbfc70000
|
#define AILOC 0xbfc70000
|
|
|
.macro hal_diag_init
|
.macro hal_diag_init
|
la v0,AILOC
|
la v0,AILOC
|
1:
|
1:
|
lbu v1,3(v0)
|
lbu v1,3(v0)
|
nop ; nop ; nop
|
nop ; nop ; nop
|
subu v1,0xCC
|
subu v1,0xCC
|
beqz v1,1b
|
beqz v1,1b
|
nop
|
nop
|
lbu v1,2(v0)
|
lbu v1,2(v0)
|
|
|
b 9f
|
b 9f
|
nop
|
nop
|
|
|
.global hal_diag_ai_write_char
|
.global hal_diag_ai_write_char
|
hal_diag_ai_write_char:
|
hal_diag_ai_write_char:
|
|
|
.set noat
|
.set noat
|
la v0,AILOC # v0 = AI location
|
la v0,AILOC # v0 = AI location
|
|
|
1:
|
1:
|
lbu v1,3(v0) # v1 = status register
|
lbu v1,3(v0) # v1 = status register
|
nop ; nop ; nop
|
nop ; nop ; nop
|
andi v1,v1,1 # v1 = TDA bit
|
andi v1,v1,1 # v1 = TDA bit
|
bnez v1,1b # loop while non-zero
|
bnez v1,1b # loop while non-zero
|
nop
|
nop
|
|
|
sll a0,a0,1 # a0 = a0<<1
|
sll a0,a0,1 # a0 = a0<<1
|
ori a0,a0,0x0201 # or in start and stop bits
|
ori a0,a0,0x0201 # or in start and stop bits
|
li $at,10 # we have 10 bits to send
|
li $at,10 # we have 10 bits to send
|
2:
|
2:
|
andi v1,a0,1 # v1 = ls bit of char
|
andi v1,a0,1 # v1 = ls bit of char
|
add v1,v0,v1 # v1 = address of ZERO or ONE register
|
add v1,v0,v1 # v1 = address of ZERO or ONE register
|
lbu zero,0(v1) # read it to send bit
|
lbu zero,0(v1) # read it to send bit
|
la v1,100 # delay a bit to let PROMICE deal with it
|
la v1,100 # delay a bit to let PROMICE deal with it
|
3: bnez v1,3b # loop while non-zero
|
3: bnez v1,3b # loop while non-zero
|
add v1,v1,-1 # decrement in delay slot
|
add v1,v1,-1 # decrement in delay slot
|
srl a0,a0,1 # a0 = a0>>1
|
srl a0,a0,1 # a0 = a0>>1
|
subu $at,1 # decrement count
|
subu $at,1 # decrement count
|
bnez $at,2b # loop while non-zero
|
bnez $at,2b # loop while non-zero
|
nop
|
nop
|
|
|
jr ra # all done, return
|
jr ra # all done, return
|
nop
|
nop
|
|
|
.set at
|
.set at
|
|
|
.global hal_diag_ai_write_hex1
|
.global hal_diag_ai_write_hex1
|
hal_diag_ai_write_hex1:
|
hal_diag_ai_write_hex1:
|
la v0,9
|
la v0,9
|
andi a0,a0,0xf
|
andi a0,a0,0xf
|
ble a0,v0,1f
|
ble a0,v0,1f
|
nop
|
nop
|
addi a0,a0,('A'-'9'-1)
|
addi a0,a0,('A'-'9'-1)
|
1: addi a0,a0,'0'
|
1: addi a0,a0,'0'
|
b hal_diag_ai_write_char
|
b hal_diag_ai_write_char
|
nop
|
nop
|
|
|
.global hal_diag_ai_write_hex2
|
.global hal_diag_ai_write_hex2
|
hal_diag_ai_write_hex2:
|
hal_diag_ai_write_hex2:
|
move t0,ra # save ra
|
move t0,ra # save ra
|
move t1,a0 # save arg
|
move t1,a0 # save arg
|
srl a0,a0,4 # ms nibble
|
srl a0,a0,4 # ms nibble
|
|
|
bal hal_diag_ai_write_hex1
|
bal hal_diag_ai_write_hex1
|
nop
|
nop
|
|
|
move a0,t1 # retrieve a0
|
move a0,t1 # retrieve a0
|
move ra,t0 # retrieve ra
|
move ra,t0 # retrieve ra
|
b hal_diag_ai_write_hex1
|
b hal_diag_ai_write_hex1
|
nop
|
nop
|
|
|
.global hal_diag_ai_write_hex4
|
.global hal_diag_ai_write_hex4
|
hal_diag_ai_write_hex4:
|
hal_diag_ai_write_hex4:
|
move t2,ra # save ra
|
move t2,ra # save ra
|
move t3,a0 # save arg
|
move t3,a0 # save arg
|
srl a0,a0,8 # ms byte
|
srl a0,a0,8 # ms byte
|
|
|
bal hal_diag_ai_write_hex2
|
bal hal_diag_ai_write_hex2
|
nop
|
nop
|
|
|
move a0,t3 # retrieve a0
|
move a0,t3 # retrieve a0
|
move ra,t2 # retrieve ra
|
move ra,t2 # retrieve ra
|
b hal_diag_ai_write_hex2
|
b hal_diag_ai_write_hex2
|
nop
|
nop
|
|
|
|
|
.global hal_diag_ai_write_hex8
|
.global hal_diag_ai_write_hex8
|
hal_diag_ai_write_hex8:
|
hal_diag_ai_write_hex8:
|
move t4,ra # save ra
|
move t4,ra # save ra
|
move t5,a0 # save arg
|
move t5,a0 # save arg
|
srl a0,a0,16 # ms short
|
srl a0,a0,16 # ms short
|
|
|
bal hal_diag_ai_write_hex4
|
bal hal_diag_ai_write_hex4
|
nop
|
nop
|
|
|
move a0,t5 # retrieve a0
|
move a0,t5 # retrieve a0
|
move ra,t4 # retrieve ra
|
move ra,t4 # retrieve ra
|
b hal_diag_ai_write_hex4
|
b hal_diag_ai_write_hex4
|
nop
|
nop
|
|
|
|
|
9:
|
9:
|
# Output a '!' to check that the interface is working
|
# Output a '!' to check that the interface is working
|
|
|
li a0,'!'
|
li a0,'!'
|
bal hal_diag_ai_write_char
|
bal hal_diag_ai_write_char
|
nop
|
nop
|
|
|
.endm
|
.endm
|
|
|
# Utility macro to emit a character
|
# Utility macro to emit a character
|
.macro hal_diag_writec char
|
.macro hal_diag_writec char
|
.extern hal_diag_ai_write_char
|
.extern hal_diag_ai_write_char
|
la a0,\char
|
la a0,\char
|
lar v0,hal_diag_ai_write_char
|
lar v0,hal_diag_ai_write_char
|
jalr v0
|
jalr v0
|
# bal hal_diag_ai_write_char
|
# bal hal_diag_ai_write_char
|
nop
|
nop
|
.endm
|
.endm
|
|
|
#if 0
|
#if 0
|
# This macro outputs a '+', the exception number as a
|
# This macro outputs a '+', the exception number as a
|
# character offset from 'A' and the exception address
|
# character offset from 'A' and the exception address
|
# in hex.
|
# in hex.
|
.macro hal_diag_excpt_start
|
.macro hal_diag_excpt_start
|
hal_diag_writec '+'
|
hal_diag_writec '+'
|
srl k0,k0,2
|
srl k0,k0,2
|
addi a0,k0,'A'
|
addi a0,k0,'A'
|
jal hal_diag_ai_write_char
|
jal hal_diag_ai_write_char
|
nop
|
nop
|
move a0,t6 # we know t6 contains the epc value
|
move a0,t6 # we know t6 contains the epc value
|
jal hal_diag_ai_write_hex8
|
jal hal_diag_ai_write_hex8
|
nop
|
nop
|
.endm
|
.endm
|
#else
|
#else
|
.macro hal_diag_excpt_start
|
.macro hal_diag_excpt_start
|
.endm
|
.endm
|
#endif
|
#endif
|
|
|
#if 0
|
#if 0
|
# This macro outputs a '=' and the vector number as a
|
# This macro outputs a '=' and the vector number as a
|
# character offset from 'A'.
|
# character offset from 'A'.
|
.macro hal_diag_intr_start
|
.macro hal_diag_intr_start
|
.extern hal_diag_ai_write_char
|
.extern hal_diag_ai_write_char
|
hal_diag_writec '='
|
hal_diag_writec '='
|
addi a0,s2,'A'
|
addi a0,s2,'A'
|
jal hal_diag_ai_write_char
|
jal hal_diag_ai_write_char
|
nop
|
nop
|
.endm
|
.endm
|
#else
|
#else
|
.macro hal_diag_intr_start
|
.macro hal_diag_intr_start
|
.endm
|
.endm
|
#endif
|
#endif
|
|
|
#if 0
|
#if 0
|
.macro hal_diag_restore
|
.macro hal_diag_restore
|
hal_diag_writec '^'
|
hal_diag_writec '^'
|
lw a0,mipsreg_pc(sp)
|
lw a0,mipsreg_pc(sp)
|
lar k0,hal_diag_ai_write_hex8
|
lar k0,hal_diag_ai_write_hex8
|
jalr k0
|
jalr k0
|
.endm
|
.endm
|
#else
|
#else
|
.macro hal_diag_restore
|
.macro hal_diag_restore
|
.endm
|
.endm
|
#endif
|
#endif
|
|
|
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
|
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
|
|
|
#elif 0
|
#elif 0
|
|
|
#define DELAY(n) \
|
#define DELAY(n) \
|
li $at,n; \
|
li $at,n; \
|
9: bnez $at,9b; \
|
9: bnez $at,9b; \
|
subu $at,1; \
|
subu $at,1; \
|
|
|
/* Zilog Access Delay */
|
/* Zilog Access Delay */
|
#define DELZ DELAY( (200) )
|
#define DELZ DELAY( (200) )
|
|
|
|
|
.macro hal_diag_init
|
.macro hal_diag_init
|
la v0,0xc2000000
|
la v0,0xc2000000
|
DELZ
|
DELZ
|
lbu v1,8(v0)
|
lbu v1,8(v0)
|
andi v1,v1,0xfc
|
andi v1,v1,0xfc
|
DELZ
|
DELZ
|
sb v1,8(v0)
|
sb v1,8(v0)
|
.endm
|
.endm
|
|
|
.macro hal_diag_excpt_start
|
.macro hal_diag_excpt_start
|
.endm
|
.endm
|
|
|
.macro hal_diag_intr_start
|
.macro hal_diag_intr_start
|
la v0,0xc2000000
|
la v0,0xc2000000
|
DELZ
|
DELZ
|
lbu v1,8(v0)
|
lbu v1,8(v0)
|
xori v1,v1,0x01
|
xori v1,v1,0x01
|
DELZ
|
DELZ
|
sb v1,8(v0)
|
sb v1,8(v0)
|
.endm
|
.endm
|
|
|
.macro hal_diag_restore
|
.macro hal_diag_restore
|
la v0,0xc2000000
|
la v0,0xc2000000
|
DELZ
|
DELZ
|
lbu v1,8(v0)
|
lbu v1,8(v0)
|
xori v1,v1,0x01
|
xori v1,v1,0x01
|
DELZ
|
DELZ
|
sb v1,8(v0)
|
sb v1,8(v0)
|
|
|
# li a0,0x0310 # a0 = type = INTR,RAISE
|
# li a0,0x0310 # a0 = type = INTR,RAISE
|
# lw a1,mipsreg_sr(sp) # a1 = sr
|
# lw a1,mipsreg_sr(sp) # a1 = sr
|
# mfc0 a2,status
|
# mfc0 a2,status
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# jal cyg_instrument # call instrument function
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# jal cyg_instrument # call instrument function
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# nop
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# nop
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.endm
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.endm
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#define CYGPKG_HAL_MIPS_DIAG_DEFINED
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#define CYGPKG_HAL_MIPS_DIAG_DEFINED
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#endif
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#endif
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#endif
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#endif
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#------------------------------------------------------------------------------
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#------------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLATFORM_INC
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#endif // ifndef CYGONCE_HAL_PLATFORM_INC
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# end of platform.inc
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# end of platform.inc
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