//==========================================================================
|
//==========================================================================
|
//
|
//
|
// hal_arch.h
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// hal_arch.h
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//
|
//
|
// Architecture specific abstractions
|
// Architecture specific abstractions
|
//
|
//
|
//==========================================================================
|
//==========================================================================
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
// -------------------------------------------
|
// -------------------------------------------
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
//
|
//
|
// eCos is free software; you can redistribute it and/or modify it under
|
// eCos is free software; you can redistribute it and/or modify it under
|
// the terms of the GNU General Public License as published by the Free
|
// the terms of the GNU General Public License as published by the Free
|
// Software Foundation; either version 2 or (at your option) any later
|
// Software Foundation; either version 2 or (at your option) any later
|
// version.
|
// version.
|
//
|
//
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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//
|
// As a special exception, if other files instantiate templates or use
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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// General Public License v2.
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//
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//
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// This exception does not invalidate any other reasons why a work based
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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// ####ECOSGPLCOPYRIGHTEND####
|
//==========================================================================
|
//==========================================================================
|
//#####DESCRIPTIONBEGIN####
|
//#####DESCRIPTIONBEGIN####
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//
|
//
|
// Author(s): sfurman
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// Author(s): sfurman
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// Contributors:
|
// Contributors:
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// Date: 2003-01-17
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// Date: 2003-01-17
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// Purpose: Define architecture abstractions
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// Purpose: Define architecture abstractions
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// Usage: #include <cyg/hal/hal_arch.h>
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// Usage: #include <cyg/hal/hal_arch.h>
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//
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//
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//####DESCRIPTIONEND####
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//####DESCRIPTIONEND####
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//
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//
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//==========================================================================
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//==========================================================================
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|
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#ifndef CYGONCE_HAL_HAL_ARCH_H
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#ifndef CYGONCE_HAL_HAL_ARCH_H
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#define CYGONCE_HAL_HAL_ARCH_H
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#define CYGONCE_HAL_HAL_ARCH_H
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|
|
// Include macros to access special-purpose registers (SPRs)
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// Include macros to access special-purpose registers (SPRs)
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#include <cyg/hal/spr_defs.h>
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#include <cyg/hal/spr_defs.h>
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|
|
#define CYG_HAL_OPENRISC_REG_SIZE 4
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#define CYG_HAL_OPENRISC_REG_SIZE 4
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|
|
#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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#include <pkgconf/hal.h>
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_type.h>
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|
|
//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Processor saved states:
|
// Processor saved states:
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// The layout of this structure is also defined in "arch.inc", for assembly
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// The layout of this structure is also defined in "arch.inc", for assembly
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// code. Do not change this without changing that (or vice versa).
|
// code. Do not change this without changing that (or vice versa).
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|
|
#define CYG_HAL_OPENRISC_REG CYG_WORD32
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#define CYG_HAL_OPENRISC_REG CYG_WORD32
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|
|
typedef struct
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typedef struct
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{
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{
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// These are common to all saved states
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// These are common to all saved states
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CYG_HAL_OPENRISC_REG r[32]; // GPR regs
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CYG_HAL_OPENRISC_REG r[32]; // GPR regs
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CYG_HAL_OPENRISC_REG machi; // High and low words of
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CYG_HAL_OPENRISC_REG machi; // High and low words of
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CYG_HAL_OPENRISC_REG maclo; // multiply/accumulate reg
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CYG_HAL_OPENRISC_REG maclo; // multiply/accumulate reg
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|
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// These are only saved for exceptions and interrupts
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// These are only saved for exceptions and interrupts
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CYG_WORD32 vector; /* Vector number */
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CYG_WORD32 vector; /* Vector number */
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CYG_WORD32 sr; /* Status Reg */
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CYG_WORD32 sr; /* Status Reg */
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CYG_HAL_OPENRISC_REG pc; /* Program Counter */
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CYG_HAL_OPENRISC_REG pc; /* Program Counter */
|
|
|
// Saved only for exceptions, and not restored when continued:
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// Saved only for exceptions, and not restored when continued:
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// Effective address of instruction/data access that caused exception
|
// Effective address of instruction/data access that caused exception
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CYG_HAL_OPENRISC_REG eear; /* Exception effective address reg */
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CYG_HAL_OPENRISC_REG eear; /* Exception effective address reg */
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} HAL_SavedRegisters;
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} HAL_SavedRegisters;
|
|
|
//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Utilities
|
// Utilities
|
|
|
// Move from architecture special register (SPR)
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// Move from architecture special register (SPR)
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#define MFSPR(_spr_) \
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#define MFSPR(_spr_) \
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({ CYG_HAL_OPENRISC_REG _result_; \
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({ CYG_HAL_OPENRISC_REG _result_; \
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asm volatile ("l.mfspr %0, r0, %1;" \
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asm volatile ("l.mfspr %0, r0, %1;" \
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: "=r"(_result_) \
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: "=r"(_result_) \
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: "K"(_spr_) \
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: "K"(_spr_) \
|
); \
|
); \
|
_result_;})
|
_result_;})
|
|
|
// Move data to architecture special registers (SPR)
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// Move data to architecture special registers (SPR)
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#define MTSPR(_spr_, _val_) \
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#define MTSPR(_spr_, _val_) \
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CYG_MACRO_START \
|
CYG_MACRO_START \
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CYG_HAL_OPENRISC_REG val = _val_; \
|
CYG_HAL_OPENRISC_REG val = _val_; \
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asm volatile ("l.mtspr r0, %0, %1;" \
|
asm volatile ("l.mtspr r0, %0, %1;" \
|
: \
|
: \
|
: "r"(val), "K"(_spr_) \
|
: "r"(val), "K"(_spr_) \
|
); \
|
); \
|
CYG_MACRO_END
|
CYG_MACRO_END
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Exception handling function.
|
// Exception handling function.
|
// This function is defined by the kernel according to this prototype. It is
|
// This function is defined by the kernel according to this prototype. It is
|
// invoked from the HAL to deal with any CPU exceptions that the HAL does
|
// invoked from the HAL to deal with any CPU exceptions that the HAL does
|
// not want to deal with itself. It usually invokes the kernel's exception
|
// not want to deal with itself. It usually invokes the kernel's exception
|
// delivery mechanism.
|
// delivery mechanism.
|
|
|
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
|
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Bit manipulation macros
|
// Bit manipulation macros
|
|
|
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
|
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
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externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
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externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
|
|
|
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
|
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
|
|
|
// NOTE - Below can be optimized with l.ff1 instruction if that optional
|
// NOTE - Below can be optimized with l.ff1 instruction if that optional
|
// instruction is implemented in HW. OR12k does not implement
|
// instruction is implemented in HW. OR12k does not implement
|
// it at this time, however.
|
// it at this time, however.
|
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
|
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Context Initialization
|
// Context Initialization
|
|
|
|
|
// Initialize the context of a thread.
|
// Initialize the context of a thread.
|
// Arguments:
|
// Arguments:
|
// _sparg_ name of variable containing current sp, will be written with new sp
|
// _sparg_ name of variable containing current sp, will be written with new sp
|
// _thread_ thread object address, passed as argument to entry point
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// _thread_ thread object address, passed as argument to entry point
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// _entry_ entry point address.
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// _entry_ entry point address.
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// _id_ bit pattern used in initializing registers, for debugging.
|
// _id_ bit pattern used in initializing registers, for debugging.
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#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
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#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
|
{ \
|
{ \
|
int _i_; \
|
int _i_; \
|
register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \
|
register CYG_WORD _sp_ = ((CYG_WORD)_sparg_); \
|
register HAL_SavedRegisters *_regs_; \
|
register HAL_SavedRegisters *_regs_; \
|
_regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\
|
_regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters)) & ~(CYGARC_ALIGNMENT));\
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_sp_ &= ~(CYGARC_ALIGNMENT); \
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_sp_ &= ~(CYGARC_ALIGNMENT); \
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for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \
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for( _i_ = 1; _i_ < 32; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \
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(_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_); /* SP = top of stack */ \
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(_regs_)->r[1] = (CYG_HAL_OPENRISC_REG)(_sp_); /* SP = top of stack */ \
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(_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_); /* FP = top of stack */ \
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(_regs_)->r[2] = (CYG_HAL_OPENRISC_REG)(_sp_); /* FP = top of stack */ \
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(_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_); /* R3 = arg1 = thread ptr */ \
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(_regs_)->r[3] = (CYG_HAL_OPENRISC_REG)(_thread_); /* R3 = arg1 = thread ptr */ \
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(_regs_)->maclo = 0; /* MACLO = 0 */ \
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(_regs_)->maclo = 0; /* MACLO = 0 */ \
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(_regs_)->machi = 0; /* MACHI = 0 */ \
|
(_regs_)->machi = 0; /* MACHI = 0 */ \
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(_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE); /* Interrupts enabled */ \
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(_regs_)->sr = (SPR_SR_TEE|SPR_SR_IEE); /* Interrupts enabled */ \
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(_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \
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(_regs_)->pc = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \
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(_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \
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(_regs_)->r[9] = (CYG_HAL_OPENRISC_REG)(_entry_); /* PC = entry point */ \
|
_sparg_ = (CYG_ADDRESS)_regs_; \
|
_sparg_ = (CYG_ADDRESS)_regs_; \
|
}
|
}
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Context switch macros.
|
// Context switch macros.
|
|
|
// The arguments to these macros are *pointers* to locations where the
|
// The arguments to these macros are *pointers* to locations where the
|
// stack pointer of the thread is to be stored/retrieved, i.e. *not*
|
// stack pointer of the thread is to be stored/retrieved, i.e. *not*
|
// the value of the stack pointer itself.
|
// the value of the stack pointer itself.
|
|
|
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
|
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
|
externC void hal_thread_load_context( CYG_ADDRESS to )
|
externC void hal_thread_load_context( CYG_ADDRESS to )
|
__attribute__ ((noreturn));
|
__attribute__ ((noreturn));
|
|
|
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
|
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
|
hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \
|
hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \
|
(CYG_ADDRESS)_fspptr_);
|
(CYG_ADDRESS)_fspptr_);
|
|
|
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
|
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
|
hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
|
hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
|
|
|
// Translate a stack pointer as saved by the thread context macros above into
|
// Translate a stack pointer as saved by the thread context macros above into
|
// a pointer to a HAL_SavedRegisters structure.
|
// a pointer to a HAL_SavedRegisters structure.
|
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
|
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
|
(_regs_) = (HAL_SavedRegisters *)(_sp_)
|
(_regs_) = (HAL_SavedRegisters *)(_sp_)
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Execution reorder barrier.
|
// Execution reorder barrier.
|
// When optimizing the compiler can reorder code. In multithreaded systems
|
// When optimizing the compiler can reorder code. In multithreaded systems
|
// where the order of actions is vital, this can sometimes cause problems.
|
// where the order of actions is vital, this can sometimes cause problems.
|
// This macro may be inserted into places where reordering should not happen.
|
// This macro may be inserted into places where reordering should not happen.
|
// The "memory" keyword is potentially unnecessary, but it is harmless to
|
// The "memory" keyword is potentially unnecessary, but it is harmless to
|
// keep it.
|
// keep it.
|
|
|
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
|
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Breakpoint support
|
// Breakpoint support
|
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
|
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
|
// occur if executed.
|
// occur if executed.
|
// HAL_BREAKINST is the value of the breakpoint instruction and...
|
// HAL_BREAKINST is the value of the breakpoint instruction and...
|
// HAL_BREAKINST_SIZE is its size in bytes and...
|
// HAL_BREAKINST_SIZE is its size in bytes and...
|
// HAL_BREAKINST_TYPE is its type.
|
// HAL_BREAKINST_TYPE is its type.
|
|
|
#define HAL_BREAKPOINT(_label_) \
|
#define HAL_BREAKPOINT(_label_) \
|
asm volatile (" .globl _" #_label_ ";" \
|
asm volatile (" .globl " #_label_ ";" \
|
"_" #_label_ ":" \
|
#_label_ ":" \
|
" l.trap 1;" \
|
" l.trap 1;" \
|
);
|
);
|
|
|
#define HAL_BREAKINST (0x21000001) // l.trap 1 instruction
|
#define HAL_BREAKINST (0x21000001) // l.trap 1 instruction
|
|
|
#define HAL_BREAKINST_SIZE 4
|
#define HAL_BREAKINST_SIZE 4
|
|
|
#define HAL_BREAKINST_TYPE cyg_uint32
|
#define HAL_BREAKINST_TYPE cyg_uint32
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// Thread register state manipulation for GDB support.
|
// Thread register state manipulation for GDB support.
|
|
|
// Default to a 32 bit register size for GDB register dumps.
|
// Default to a 32 bit register size for GDB register dumps.
|
#ifndef CYG_HAL_GDB_REG
|
#ifndef CYG_HAL_GDB_REG
|
#define CYG_HAL_GDB_REG CYG_WORD32
|
#define CYG_HAL_GDB_REG CYG_WORD32
|
#endif
|
#endif
|
|
|
// Register layout expected by GDB
|
// Register layout expected by GDB
|
typedef struct
|
typedef struct
|
{
|
{
|
CYG_HAL_OPENRISC_REG r[32]; // GPR regs
|
CYG_HAL_OPENRISC_REG r[32]; // GPR regs
|
CYG_HAL_OPENRISC_REG pc; // Program Counter
|
CYG_HAL_OPENRISC_REG pc; // Program Counter
|
CYG_HAL_OPENRISC_REG sr; // Supervisor/Status Reg
|
CYG_HAL_OPENRISC_REG sr; // Supervisor/Status Reg
|
} GDB_Registers;
|
} GDB_Registers;
|
|
|
// Copy a set of registers from a HAL_SavedRegisters structure into a
|
// Copy a set of registers from a HAL_SavedRegisters structure into a
|
// GDB_Registers structure.
|
// GDB_Registers structure.
|
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
|
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
|
CYG_MACRO_START \
|
CYG_MACRO_START \
|
GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \
|
GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \
|
int _i_; \
|
int _i_; \
|
\
|
\
|
for( _i_ = 0; _i_ < 32; _i_++ ) { \
|
for( _i_ = 0; _i_ < 32; _i_++ ) { \
|
_gdb_->r[_i_] = (_regs_)->r[_i_]; \
|
_gdb_->r[_i_] = (_regs_)->r[_i_]; \
|
} \
|
} \
|
\
|
\
|
_gdb_->pc = (_regs_)->pc; \
|
_gdb_->pc = (_regs_)->pc; \
|
_gdb_->sr = (_regs_)->sr; \
|
_gdb_->sr = (_regs_)->sr; \
|
CYG_MACRO_END
|
CYG_MACRO_END
|
|
|
// Copy a set of registers from a GDB_Registers structure into a
|
// Copy a set of registers from a GDB_Registers structure into a
|
// HAL_SavedRegisters structure.
|
// HAL_SavedRegisters structure.
|
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
|
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
|
CYG_MACRO_START \
|
CYG_MACRO_START \
|
GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \
|
GDB_Registers *_gdb_ = (GDB_Registers *)(_aregval_); \
|
int _i_; \
|
int _i_; \
|
\
|
\
|
for( _i_ = 0; _i_ < 32; _i_++ ) \
|
for( _i_ = 0; _i_ < 32; _i_++ ) \
|
(_regs_)->r[_i_] = _gdb_->r[_i_]; \
|
(_regs_)->r[_i_] = _gdb_->r[_i_]; \
|
\
|
\
|
(_regs_)->pc = _gdb_->pc; \
|
(_regs_)->pc = _gdb_->pc; \
|
(_regs_)->sr = _gdb_->sr; \
|
(_regs_)->sr = _gdb_->sr; \
|
CYG_MACRO_END
|
CYG_MACRO_END
|
|
|
//--------------------------------------------------------------------------
|
//--------------------------------------------------------------------------
|
// HAL setjmp
|
// HAL setjmp
|
// Note: These definitions are repeated in context.S. If changes are
|
// Note: These definitions are repeated in context.S. If changes are
|
// required remember to update both sets.
|
// required remember to update both sets.
|
|
|
#define CYGARC_JMP_BUF_R1 0
|
#define CYGARC_JMP_BUF_R1 0
|
#define CYGARC_JMP_BUF_R2 1
|
#define CYGARC_JMP_BUF_R2 1
|
#define CYGARC_JMP_BUF_R9 2
|
#define CYGARC_JMP_BUF_R9 2
|
#define CYGARC_JMP_BUF_R10 3
|
#define CYGARC_JMP_BUF_R10 3
|
#define CYGARC_JMP_BUF_R12 4
|
#define CYGARC_JMP_BUF_R12 4
|
#define CYGARC_JMP_BUF_R14 5
|
#define CYGARC_JMP_BUF_R14 5
|
#define CYGARC_JMP_BUF_R16 6
|
#define CYGARC_JMP_BUF_R16 6
|
#define CYGARC_JMP_BUF_R18 7
|
#define CYGARC_JMP_BUF_R18 7
|
#define CYGARC_JMP_BUF_R20 8
|
#define CYGARC_JMP_BUF_R20 8
|
#define CYGARC_JMP_BUF_R22 9
|
#define CYGARC_JMP_BUF_R22 9
|
#define CYGARC_JMP_BUF_R24 10
|
#define CYGARC_JMP_BUF_R24 10
|
#define CYGARC_JMP_BUF_R26 11
|
#define CYGARC_JMP_BUF_R26 11
|
#define CYGARC_JMP_BUF_R28 12
|
#define CYGARC_JMP_BUF_R28 12
|
#define CYGARC_JMP_BUF_R30 13
|
#define CYGARC_JMP_BUF_R30 13
|
|
|
#define CYGARC_JMP_BUF_SIZE 14
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#define CYGARC_JMP_BUF_SIZE 14
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typedef CYG_HAL_OPENRISC_REG hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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typedef CYG_HAL_OPENRISC_REG hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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externC int hal_setjmp(hal_jmp_buf env);
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externC int hal_setjmp(hal_jmp_buf env);
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externC void hal_longjmp(hal_jmp_buf env, int val);
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externC void hal_longjmp(hal_jmp_buf env, int val);
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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// Idle thread code.
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// Idle thread code.
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// This macro is called in the idle thread loop, and gives the HAL the
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// This macro is called in the idle thread loop, and gives the HAL the
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// chance to run code when no threads are runnable. Typical idle
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// chance to run code when no threads are runnable. Typical idle
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// thread behaviour might be to halt the processor.
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// thread behaviour might be to halt the processor.
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externC void hal_idle_thread_action(cyg_uint32 loop_count);
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externC void hal_idle_thread_action(cyg_uint32 loop_count);
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#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Minimal and sensible stack sizes: the intention is that applications
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// Minimal and sensible stack sizes: the intention is that applications
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// will use these to provide a stack size in the first instance prior to
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// will use these to provide a stack size in the first instance prior to
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// proper analysis. Idle thread stack should be this big.
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// proper analysis. Idle thread stack should be this big.
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// *** THESE ARE NOT INTENDED TO BE GUARANTEED SUFFICIENT STACK SIZES ***
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// *** THESE ARE NOT INTENDED TO BE GUARANTEED SUFFICIENT STACK SIZES ***
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// They are, however, enough to start programming.
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// They are, however, enough to start programming.
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// You might, for example, need to make your stacks larger if you have
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// You might, for example, need to make your stacks larger if you have
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// large "auto" variables.
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// large "auto" variables.
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// This is not a config option because it should not be adjusted except
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// This is not a config option because it should not be adjusted except
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// under "enough rope to hang yourself" sort of disclaimers.
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// under "enough rope to hang yourself" sort of disclaimers.
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// Typical case stack frame size: return link + 10 caller-saved temporaries + 4 locals.
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// Typical case stack frame size: return link + 10 caller-saved temporaries + 4 locals.
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#define CYGNUM_HAL_STACK_FRAME_SIZE (15 * CYG_HAL_OPENRISC_REG_SIZE)
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#define CYGNUM_HAL_STACK_FRAME_SIZE (15 * CYG_HAL_OPENRISC_REG_SIZE)
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// Stack needed for a context switch:
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// Stack needed for a context switch:
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#define CYGNUM_HAL_STACK_CONTEXT_SIZE (38 * 4) // sizeof(HAL_SavedRegisters)
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#define CYGNUM_HAL_STACK_CONTEXT_SIZE (38 * 4) // sizeof(HAL_SavedRegisters)
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// Interrupt + call to ISR, interrupt_end() and the DSR
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// Interrupt + call to ISR, interrupt_end() and the DSR
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#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2*CYGNUM_HAL_STACK_FRAME_SIZE)
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#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (CYGNUM_HAL_STACK_CONTEXT_SIZE + 2*CYGNUM_HAL_STACK_FRAME_SIZE)
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// We define a minimum stack size as the minimum any thread could ever
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// We define a minimum stack size as the minimum any thread could ever
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// legitimately get away with. We can throw asserts if users ask for less
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// legitimately get away with. We can throw asserts if users ask for less
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// than this. Allow enough for three interrupt sources - clock, serial and
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// than this. Allow enough for three interrupt sources - clock, serial and
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// one other
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// one other
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// If interrupts are segregated onto their own stack...
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// If interrupts are segregated onto their own stack...
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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// An interrupt stack which is large enough for all possible interrupt
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// An interrupt stack which is large enough for all possible interrupt
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// conditions (and only used for that purpose) exists. "User" stacks
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// conditions (and only used for that purpose) exists. "User" stacks
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// can therefore be much smaller
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// can therefore be much smaller
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// NOTE - interrupt stack sizes can be smaller if we don't allow interrupts
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// NOTE - interrupt stack sizes can be smaller if we don't allow interrupts
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// to nest.
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// to nest.
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# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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((3 * 5)*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
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((3 * 5)*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
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#else
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#else
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// No separate interrupt stack exists. Make sure all threads contain
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// No separate interrupt stack exists. Make sure all threads contain
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// a stack sufficiently large
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// a stack sufficiently large
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# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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# define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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(( 3*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \
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(( 3*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \
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(25*CYGNUM_HAL_STACK_FRAME_SIZE))
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(25*CYGNUM_HAL_STACK_FRAME_SIZE))
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#endif
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#endif
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// Now make a reasonable choice for a typical thread size. Pluck figures
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// Now make a reasonable choice for a typical thread size. Pluck figures
|
// from thin air and say 40 call frames
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// from thin air and say 40 call frames
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#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
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#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
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(CYGNUM_HAL_STACK_SIZE_MINIMUM + \
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(CYGNUM_HAL_STACK_SIZE_MINIMUM + \
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40 * (CYGNUM_HAL_STACK_FRAME_SIZE))
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40 * (CYGNUM_HAL_STACK_FRAME_SIZE))
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#endif /* __ASSEMBLER__ */
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#endif /* __ASSEMBLER__ */
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Macros for switching context between two eCos instances (jump from
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// Macros for switching context between two eCos instances (jump from
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// code in ROM to code in RAM or vice versa).
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// code in ROM to code in RAM or vice versa).
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// These are NOP's in the case of OpenRISC.
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// These are NOP's in the case of OpenRISC.
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#define CYGARC_HAL_SAVE_GP()
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#define CYGARC_HAL_SAVE_GP()
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#define CYGARC_HAL_RESTORE_GP()
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#define CYGARC_HAL_RESTORE_GP()
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Macro for finding return address of current function
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// Macro for finding return address of current function
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#define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
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#define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
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asm volatile ( "l.ori %0,r9,0;" : "=r" (_x_) )
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asm volatile ( "l.ori %0,r9,0;" : "=r" (_x_) )
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#define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
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#define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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#endif // CYGONCE_HAL_HAL_ARCH_H
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#endif // CYGONCE_HAL_HAL_ARCH_H
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// End of hal_arch.h
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// End of hal_arch.h
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