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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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Rev 623 |
#ifndef _BOARD_H_
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#define _BOARD_H_
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#define MC_ENABLED 0
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#define MC_ENABLED 0
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#define IC_ENABLE 1
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#define IC_ENABLE 0
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#define IC_SIZE 8192
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#define IC_SIZE 8192
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#define DC_ENABLE 1
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#define DC_ENABLE 0
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#define DC_SIZE 8192
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#define DC_SIZE 8192
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#define SYS_CLK 25000000
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#define SYS_CLK 25000000
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#define IN_CLK 25000000
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#define IN_CLK 25000000
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#define TICKS_PER_SEC 100
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#define UART_BAUD_RATE 115200
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//#define UART_NUM_CORES 2
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#undef UART_NUM_CORES
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#define UART_BASE 0x90000000
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#define UART0_BAUD_RATE 115200
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#define UART0_BASE 0x90000000
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#define UART0_IRQ 2
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#define UART_IRQ 2
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//#define GPIO_NUM_CORES 2
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#undef GPIO_NUM_CORES
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#define GPIO0_BASE 0x91000000
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#define GPIO0_IRQ 3
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#endif
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#endif
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