/* sim.cfg -- Simulator configuration script file
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/* sim.cfg -- Simulator configuration script file
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Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
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Copyright (C) 2010, Embecosm Limited
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Copyright (C) 2010, Embecosm Limited
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/* The Ork1sim has various parameters, that can be set in configuration files
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/* The Ork1sim has various parameters, that can be set in configuration files
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like this one. The user can specify a configuration file at startu[ with
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like this one. The user can specify a configuration file at startu[ with
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the -f option.
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the -f option.
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The user guide (see the 'doc' directory) gives full details on
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The user guide (see the 'doc' directory) gives full details on
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configuration files. This is a reference configuration, which may be used
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configuration files. This is a reference configuration, which may be used
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as a starting point for customization.
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as a starting point for customization.
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A number of peripherals are mapped at standard addresses (above 0x80000000)
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A number of peripherals are mapped at standard addresses (above 0x80000000)
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in the Verilog RTL of ORPSoC standard sitribution. The same values should
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in the Verilog RTL of ORPSoC standard sitribution. The same values should
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be used in Or1ksim section definitions to match the behavior of the Verilog
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be used in Or1ksim section definitions to match the behavior of the Verilog
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0x90000000 UART
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0x90000000 UART
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0x91000000 GPIO
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0x91000000 GPIO
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0x92000000 Ethernet
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0x92000000 Ethernet
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0x93000000 Memory controller
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0x93000000 Memory controller
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0x94000000 PS2 keyboard
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0x94000000 PS2 keyboard
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0x97000000 Frame buffer
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0x97000000 Frame buffer
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0x97100000 VGA
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0x97100000 VGA
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0x9a000000 DMA controller
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0x9a000000 DMA controller
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0x9e000000 ATA disc
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0x9e000000 ATA disc
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Section ordering matches that in the user guide. All optional peripherals
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Section ordering matches that in the user guide. All optional peripherals
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and functionality is disabled. Comments only list the possible entries and
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and functionality is disabled. Comments only list the possible entries and
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values. Consult the user guide for their meaning.
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values. Consult the user guide for their meaning.
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Unless otherwise indicated, the first named option is the default. */
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Unless otherwise indicated, the first named option is the default. */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/* Simulator section
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/* Simulator section
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verbose = 0|1
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verbose = 0|1
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debug = 0-9
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debug = 0-9
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profile = 0|1
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profile = 0|1
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prof_file = "" (default: "sim.profile")
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prof_file = "" (default: "sim.profile")
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mprofile = 0|1
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mprofile = 0|1
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mprof_file = "" (default: "sim.mprofile")
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mprof_file = "" (default: "sim.mprofile")
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history = 0|1
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history = 0|1
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exe_log = 0|1
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exe_log = 0|1
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exe_log_type = hardware|simple|software|default
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exe_log_type = hardware|simple|software|default
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exe_log_start = (default: 0)
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exe_log_start = (default: 0)
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exe_log_end = (default: never end)
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exe_log_end = (default: never end)
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exe_log_marker = (default: no markers)
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exe_log_marker = (default: no markers)
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exe_log_file = "" (default: "executed.log")
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exe_log_file = "" (default: "executed.log")
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exe_bin_insn_log = 0|1
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exe_bin_insn_log = 0|1
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exe_bin_insn_log_file = "" (default: "exe-insn.bin")
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exe_bin_insn_log_file = "" (default: "exe-insn.bin")
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clkcycle = [ps|ns|us|ms]
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clkcycle = [ps|ns|us|ms]
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*/
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*/
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section sim
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section sim
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clkcycle = 1ns
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clkcycle = 1ns
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end
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end
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/* VAPI section
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/* VAPI section
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enabled = 0|1
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enabled = 0|1
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server_port = (default: 50000)
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server_port = (default: 50000)
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log_enabled = 0|1
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log_enabled = 0|1
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hide_device_id = 0|1
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hide_device_id = 0|1
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vapi_log_file = "" (default "vapi.log")
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vapi_log_file = "" (default "vapi.log")
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*/
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*/
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section VAPI
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section VAPI
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server_port = 50000
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server_port = 50000
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log_enabled = 0
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log_enabled = 0
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vapi_log_file = "vapi.log"
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vapi_log_file = "vapi.log"
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end
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end
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/* CUC section
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/* CUC section
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memory_order = none|weak|strong|exact (default: strong)
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memory_order = none|weak|strong|exact (default: strong)
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calling_convention = 0|1
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calling_convention = 0|1
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enable_bursts = 0|1
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enable_bursts = 0|1
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no_multicycle = 0|1
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no_multicycle = 0|1
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timings_file = "" (default: virtex.tim)
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timings_file = "" (default: virtex.tim)
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*/
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*/
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section cuc
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section cuc
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memory_order = weak
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memory_order = weak
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calling_convention = 1
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calling_convention = 1
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enable_bursts = 1
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enable_bursts = 1
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no_multicycle = 1
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no_multicycle = 1
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end
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end
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/* CPU section
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/* CPU section
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ver = (default: 0)
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ver = (default: 0)
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cfg = (default: 0)
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cfg = (default: 0)
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rev = (default: 0)
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rev = (default: 0)
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upr = (see user manual for default settings)
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upr = (see user manual for default settings)
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cfgr = (default: 0x00000020)
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cfgr = (default: 0x00000020)
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sr = (default: 0x00008001)
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sr = (default: 0x00008001)
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superscalar = 0|1
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superscalar = 0|1
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hazards = 0|1
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hazards = 0|1
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dependstats = 0|1
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dependstats = 0|1
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sbuf_len = (default: 0)
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sbuf_len = (default: 0)
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hardfloat = 0|1
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hardfloat = 0|1
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*/
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*/
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section cpu
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section cpu
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ver = 0x12
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ver = 0x12
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cfg = 0x00
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cfg = 0x00
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rev = 0x0001
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rev = 0x0001
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end
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end
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/* Memory section
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/* Memory section
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type = unknown|random|unknown|pattern
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type = unknown|random|unknown|pattern
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random_seed = (default: -1)
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random_seed = (default: -1)
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pattern = (default: 0)
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pattern = (default: 0)
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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size = (default: 1024)
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size = (default: 1024)
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name = "" (default: "anonymous memory block")
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name = "" (default: "anonymous memory block")
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ce = (default: -1)
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ce = (default: -1)
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mc = (default: 0)
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mc = (default: 0)
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delayr = (default: 1)
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delayr = (default: 1)
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delayw = (default: 1)
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delayw = (default: 1)
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log = "" (default: NULL)
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log = "" (default: NULL)
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*/
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*/
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section memory
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section memory
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name = "RAM"
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name = "RAM"
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type = unknown
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type = unknown
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baseaddr = 0x00000000
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baseaddr = 0x00000000
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size = 0x00080000
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size = 0x00080000
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delayr = 1
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delayr = 1
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delayw = 2
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delayw = 2
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end
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end
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/* Data MMU section
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/* Data MMU section
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enabled = 0|1
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enabled = 0|1
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nsets = (default: 1)
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nsets = (default: 1)
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nways = (default: 1)
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nways = (default: 1)
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pagesize = (default: 8192)
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pagesize = (default: 8192)
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entrysize = (default: 1)
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entrysize = (default: 1)
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ustates = (default: 1)
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ustates = (default: 1)
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hitdelay = (default: 1)
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hitdelay = (default: 1)
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missdelay = (default: 1)
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missdelay = (default: 1)
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*/
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*/
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section dmmu
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section dmmu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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pagesize = 8192
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pagesize = 8192
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hitdelay = 0
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hitdelay = 0
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missdelay = 0
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missdelay = 0
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end
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end
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/* Instruction MMU section
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/* Instruction MMU section
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enabled = 0|1
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enabled = 0|1
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nsets = (default: 1)
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nsets = (default: 1)
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nways = (default: 1)
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nways = (default: 1)
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pagesize = (default: 8192)
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pagesize = (default: 8192)
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entrysize = (default: 1)
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entrysize = (default: 1)
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ustates = (default: 1)
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ustates = (default: 1)
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hitdelay = (default: 1)
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hitdelay = (default: 1)
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missdelay = (default: 1)
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missdelay = (default: 1)
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*/
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*/
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section immu
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section immu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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pagesize = 8192
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pagesize = 8192
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hitdelay = 0
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hitdelay = 0
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missdelay = 0
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missdelay = 0
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end
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end
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/* Data cache section
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/* Data cache section
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enabled = 0|1
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enabled = 0|1
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nsets = (default: 1)
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nsets = (default: 1)
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nways = (default: 1)
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nways = (default: 1)
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blocksize = (default: 16)
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blocksize = (default: 16)
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ustates = (default: 2)
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ustates = (default: 2)
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load_hitdelay = (default: 2)
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load_hitdelay = (default: 2)
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load_missdelay = (default: 2)
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load_missdelay = (default: 2)
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store_hitdelay = (default: 0)
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store_hitdelay = (default: 0)
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store_missdelay = (default: 0)
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store_missdelay = (default: 0)
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*/
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*/
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section dc
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section dc
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enabled = 1
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enabled = 1
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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blocksize = 16
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blocksize = 16
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load_hitdelay = 0
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load_hitdelay = 0
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load_missdelay = 0
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load_missdelay = 0
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store_hitdelay = 0
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store_hitdelay = 0
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store_missdelay = 0
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store_missdelay = 0
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end
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end
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/* Instruction cache section
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/* Instruction cache section
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enabled = 0|1
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enabled = 0|1
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nsets = (default: 1)
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nsets = (default: 1)
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nways = (default: 1)
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nways = (default: 1)
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blocksize = (default: 16)
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blocksize = (default: 16)
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ustates = (default: 2)
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ustates = (default: 2)
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hitdelay = (default: 1)
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hitdelay = (default: 1)
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missdelay = (default: 1)
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missdelay = (default: 1)
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*/
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*/
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section ic
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section ic
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enabled = 1
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enabled = 1
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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blocksize = 16
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blocksize = 16
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hitdelay = 0
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hitdelay = 0
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missdelay = 0
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missdelay = 0
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end
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end
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/* Programmable interrupt controller section
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/* Programmable interrupt controller section
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enabled = 0|1
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enabled = 0|1
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edge_trigger = 0|1 (default: 1)
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edge_trigger = 0|1 (default: 1)
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*/
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*/
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section pic
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section pic
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enabled = 1
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enabled = 1
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end
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end
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/* Power management section
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/* Power management section
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enabled = 0|1
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enabled = 0|1
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*/
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*/
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section pm
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section pm
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enabled = 0
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enabled = 0
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end
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end
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/* Branch prediction section
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/* Branch prediction section
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enabled = 0|1
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enabled = 0|1
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btic = 0|1
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btic = 0|1
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sbp_bf_fwd = 0|1
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sbp_bf_fwd = 0|1
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sbp_bnf_fwd = 0|1
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sbp_bnf_fwd = 0|1
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hitdelay = (default: 0)
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hitdelay = (default: 0)
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missdelay = (default: 0)
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missdelay = (default: 0)
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*/
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*/
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section bpb
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section bpb
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enabled = 0
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enabled = 0
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end
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end
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/* Debug unit section
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/* Debug unit section
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enabled = 0|1
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enabled = 0|1
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rsp_enabled = 0|1
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rsp_enabled = 0|1
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rsp_port = (default: 51000)
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rsp_port = (default: 51000)
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vapi_id = (default: 0)
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vapi_id = (default: 0)
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*/
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*/
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section debug
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section debug
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enabled = 1
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enabled = 1
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rsp_enabled = 1
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rsp_enabled = 1
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rsp_port = 9999
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rsp_port = 9999
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end
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end
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/* Memory controller section
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/* Memory controller section
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enabled = 0|1
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enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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POC = (default: 0)
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POC = (default: 0)
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index = (default: 0)
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index = (default: 0)
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*/
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*/
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section mc
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section mc
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enabled = 0
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enabled = 0
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baseaddr = 0x93000000
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baseaddr = 0x93000000
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POC = 0x0000000a /* 32 bit SSRAM */
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POC = 0x0000000a /* 32 bit SSRAM */
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index = 0
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index = 0
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end
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end
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/* UART section
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/* UART section
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enabled = 0|1
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enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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channel = "value>" (default: "xterm:")
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channel = "value>" (default: "xterm:")
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irq = (default: 0)
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irq = (default: 0)
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16550 = 0|1
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16550 = 0|1
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jitter = (default: 0)
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jitter = (default: 0)
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vapi_id = (default: 0)
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vapi_id = (default: 0)
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*/
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*/
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section uart
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section uart
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enabled = 1
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enabled = 1
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baseaddr = 0x90000000
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baseaddr = 0x90000000
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irq = 2
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irq = 2
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16550 = 1
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16550 = 1
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end
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end
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/* DMA section
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/* DMA section
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enabled = 0|1
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enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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irq = (default: 0)
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irq = (default: 0)
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vapi_id = (default: 0)
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vapi_id = (default: 0)
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*/
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*/
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section dma
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section dma
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enabled = 0
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enabled = 1
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baseaddr = 0x9a000000
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baseaddr = 0x9a000000
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irq = 11
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irq = 11
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end
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end
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/* Ethernet section
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/* Ethernet section
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enabled = 0|1
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enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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dma = (default: 0)
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dma = (default: 0)
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irq = (default: 0)
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irq = (default: 0)
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rtx_type = 0|1
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rtx_type = 0|1
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rx_channel = (default: 0)
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rx_channel = (default: 0)
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tx_channel = (default: 0)
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tx_channel = (default: 0)
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rxfile = "" (default: "eth_rx")
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rxfile = "" (default: "eth_rx")
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txfile = "" (default: "eth_rx")
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txfile = "" (default: "eth_rx")
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sockif = "" (default: "or1ksim_eth")
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sockif = "" (default: "or1ksim_eth")
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vapi_id = (default: 0)
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vapi_id = (default: 0)
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*/
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*/
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section ethernet
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section ethernet
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enabled = 0
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enabled = 0
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baseaddr = 0x92000000
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baseaddr = 0x92000000
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irq = 4
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irq = 4
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rtx_type = 0
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rtx_type = 0
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end
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end
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/* GPIO section
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/* GPIO section
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enabled = 0|1
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enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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irq = (default: 0)
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irq = (default: 0)
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base_vapi_id = (default: 0)
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base_vapi_id = (default: 0)
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*/
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*/
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/*
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/*
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current version of Or1ksim does not supprot newest version of gpio
|
current version of Or1ksim does not supprot newest version of gpio
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controller. So, we are use memory instead of gpio controller model.
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controller. So, we are use memory instead of gpio controller model.
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*/
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*/
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/*
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/*
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section gpio
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section gpio
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enabled = 0
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enabled = 0
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baseaddr = 0x91000000
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baseaddr = 0x91000000
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irq = 3
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irq = 3
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base_vapi_id = 0x0200
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base_vapi_id = 0x0200
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end
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end
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*/
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*/
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section memory
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section memory
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name = "gpio_dummystub"
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name = "gpio_dummystub"
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type = unknown
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type = unknown
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baseaddr = 0x91000000
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baseaddr = 0x91000000
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size = 0x00010000
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size = 0x00010000
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delayr = 1
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delayr = 1
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delayw = 2
|
delayw = 2
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end
|
end
|
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/* VGA section
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/* VGA section
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|
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enabled = 0|1
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enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
|
irq = (default: 0)
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irq = (default: 0)
|
refresh_rate = (default: cycles equivalent to 50Hz)
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refresh_rate = (default: cycles equivalent to 50Hz)
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filename = "" (default: "vga_out))
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filename = "" (default: "vga_out))
|
*/
|
*/
|
section vga
|
section vga
|
enabled = 0
|
enabled = 0
|
baseaddr = 0x97100000
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baseaddr = 0x97100000
|
irq = 8
|
irq = 8
|
end
|
end
|
|
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/* Frame buffer section
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/* Frame buffer section
|
|
|
enabled = 0|1
|
enabled = 0|1
|
baseaddr = (default: 0)
|
baseaddr = (default: 0)
|
refresh_rate = (default: cycles equivalent to 50Hz)
|
refresh_rate = (default: cycles equivalent to 50Hz)
|
filename = "" (default: "fb_out))
|
filename = "" (default: "fb_out))
|
*/
|
*/
|
section fb
|
section fb
|
enabled = 0
|
enabled = 0
|
baseaddr = 0x97000000
|
baseaddr = 0x97000000
|
end
|
end
|
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|
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/* PS2 keyboard section
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/* PS2 keyboard section
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|
|
This section configures the PS/2 compatible keyboard
|
This section configures the PS/2 compatible keyboard
|
|
|
enabled = 0|1
|
enabled = 0|1
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baseaddr = (default: 0)
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baseaddr = (default: 0)
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irq = (default: 0)
|
irq = (default: 0)
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rxfile = "" (default: "kbd_in")
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rxfile = "" (default: "kbd_in")
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*/
|
*/
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section kbd
|
section kbd
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enabled = 0
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enabled = 0
|
baseaddr = 0x94000000
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baseaddr = 0x94000000
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irq = 5
|
irq = 5
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end
|
end
|
|
|
|
|
/* ATA disc section
|
/* ATA disc section
|
|
|
enabled = 0|1
|
enabled = 0|1
|
baseaddr = (default: 0)
|
baseaddr = (default: 0)
|
irq = (default: 0)
|
irq = (default: 0)
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dev_id = 1|2|3
|
dev_id = 1|2|3
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rev = 0-15 (default: 1)
|
rev = 0-15 (default: 1)
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pio_mode0_t1 = 0-255 (default: 6)
|
pio_mode0_t1 = 0-255 (default: 6)
|
pio_mode0_t2 = 0-255 (default: 28)
|
pio_mode0_t2 = 0-255 (default: 28)
|
pio_mode0_t4 = 0-255 (default: 2)
|
pio_mode0_t4 = 0-255 (default: 2)
|
pio_mode0_teoc = 0-255 (default: 23)
|
pio_mode0_teoc = 0-255 (default: 23)
|
dma_mode0_tm = 0-255 (default: 4)
|
dma_mode0_tm = 0-255 (default: 4)
|
dma_mode0_td = 0-255 (default: 21)
|
dma_mode0_td = 0-255 (default: 21)
|
dma_mode0_teoc = 0-255 (default: 21)
|
dma_mode0_teoc = 0-255 (default: 21)
|
device = 0|1
|
device = 0|1
|
|
|
Device specific:
|
Device specific:
|
|
|
type = 0|1|2
|
type = 0|1|2
|
file = "" (default: "ata_file")
|
file = "" (default: "ata_file")
|
size = (default: 0)
|
size = (default: 0)
|
packet = 0|1
|
packet = 0|1
|
firmware = "" (default: "02207031")
|
firmware = "" (default: "02207031")
|
heads = (default: 7)
|
heads = (default: 7)
|
sectors = (default: 32)
|
sectors = (default: 32)
|
mwdma = 2|1|0|-1
|
mwdma = 2|1|0|-1
|
pio = 4|3|2|1|0
|
pio = 4|3|2|1|0
|
*/
|
*/
|
section ata
|
section ata
|
enabled = 0
|
enabled = 0
|
baseaddr = 0x9e000000
|
baseaddr = 0x9e000000
|
irq = 15
|
irq = 15
|
|
|
device 0
|
device 0
|
type = 1
|
type = 1
|
size = 1
|
size = 1
|
enddevice
|
enddevice
|
end
|
end
|
|
|
|
|
/* Generic peripheral section
|
/* Generic peripheral section
|
|
|
enabled = 0|1
|
enabled = 0|1
|
baseaddr = (default: 0)
|
baseaddr = (default: 0)
|
size = (default: 0)
|
size = (default: 0)
|
name = "" (default: "anonymous external peripheral")
|
name = "" (default: "anonymous external peripheral")
|
byte_enabled = 1|0
|
byte_enabled = 1|0
|
hw_enabled = 1|0
|
hw_enabled = 1|0
|
word_enabled = 1|0
|
word_enabled = 1|0
|
*/
|
*/
|
section generic
|
section generic
|
enabled = 0
|
enabled = 0
|
end
|
end
|
|
|
