/*
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/*
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* RTEMS CANBUS driver for eth-comm BSP
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* RTEMS CANBUS driver for eth-comm BSP
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*
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*
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* Written by Jay Monkman (jmonkman@frasca.com)
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* Written by Jay Monkman (jmonkman@frasca.com)
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*
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*
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* COPYRIGHT (c) 1998
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* COPYRIGHT (c) 1998
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* Frasca International, Inc.
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* Frasca International, Inc.
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*
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*
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* The license and distribution terms for this file may be
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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* http://www.OARcorp.com/rtems/license.html.
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*
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*
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* Note: All of this code assumes a 10Mhz clock input to the 82527
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* Note: All of this code assumes a 10Mhz clock input to the 82527
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*
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*
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* $Id: canbus.c,v 1.2 2001-09-27 12:00:35 chris Exp $
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* $Id: canbus.c,v 1.2 2001-09-27 12:00:35 chris Exp $
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <bsp.h>
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#include <bsp.h>
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#include <mpc860.h>
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#include <mpc860.h>
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#include <rtems/error.h>
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#include <rtems/error.h>
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#include <canbus.h>
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#include <canbus.h>
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/* How many CAN interfaces are there? */
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/* How many CAN interfaces are there? */
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#define NUM_CAN_DEVS 3
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#define NUM_CAN_DEVS 3
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/* How many received messages should be buffered for each channel */
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/* How many received messages should be buffered for each channel */
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#define RX_CAN_BUF_SIZE 16
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#define RX_CAN_BUF_SIZE 16
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int rxMsgBufHead[NUM_CAN_DEVS];
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int rxMsgBufHead[NUM_CAN_DEVS];
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int rxMsgBufTail[NUM_CAN_DEVS];
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int rxMsgBufTail[NUM_CAN_DEVS];
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i82527_msg_t rxMsgBuf[NUM_CAN_DEVS][RX_CAN_BUF_SIZE];
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i82527_msg_t rxMsgBuf[NUM_CAN_DEVS][RX_CAN_BUF_SIZE];
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volatile i82527_t *candev[NUM_CAN_DEVS];
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volatile i82527_t *candev[NUM_CAN_DEVS];
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static rtems_isr
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static rtems_isr
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canInterruptHandler (rtems_vector_number v)
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canInterruptHandler (rtems_vector_number v)
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{
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{
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int dev;
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int dev;
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int tmpTail;
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int tmpTail;
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switch (v) {
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switch (v) {
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case PPC_IRQ_IRQ3: dev = 0; break;
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case PPC_IRQ_IRQ3: dev = 0; break;
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case PPC_IRQ_IRQ4: dev = 1; break;
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case PPC_IRQ_IRQ4: dev = 1; break;
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case PPC_IRQ_IRQ2: dev = 2; break;
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case PPC_IRQ_IRQ2: dev = 2; break;
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default: return; /* something screwed up */
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default: return; /* something screwed up */
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}
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}
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/* we only do rx interrupts right now */
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/* we only do rx interrupts right now */
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if (!(candev[dev]->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
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if (!(candev[dev]->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
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/* Hmmm, that's odd. Why were we triggered? */
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/* Hmmm, that's odd. Why were we triggered? */
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candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_INTPND_CLR |
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candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_INTPND_CLR |
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I82527_MSG_CTRL_MSGVAL_SET);
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I82527_MSG_CTRL_MSGVAL_SET);
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candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_RMTPND_CLR |
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candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_RMTPND_CLR |
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I82527_MSG_CTRL_MSGLST_CLR |
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I82527_MSG_CTRL_MSGLST_CLR |
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I82527_MSG_CTRL_NEWDAT_CLR);
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I82527_MSG_CTRL_NEWDAT_CLR);
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return;
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return;
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}
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}
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tmpTail = rxMsgBufTail[dev];
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tmpTail = rxMsgBufTail[dev];
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while (1) {
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while (1) {
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if ((tmpTail == rxMsgBufHead[dev]) &&
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if ((tmpTail == rxMsgBufHead[dev]) &&
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(rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
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(rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
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break; /* Buf is full */
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break; /* Buf is full */
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}
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}
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if (!(rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
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if (!(rxMsgBuf[dev][tmpTail].ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
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int pkt_len;
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int pkt_len;
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int i;
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int i;
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rxMsgBuf[dev][tmpTail].ctrl0 = candev[dev]->msg15.ctrl0;
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rxMsgBuf[dev][tmpTail].ctrl0 = candev[dev]->msg15.ctrl0;
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rxMsgBuf[dev][tmpTail].ctrl1 = candev[dev]->msg15.ctrl1;
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rxMsgBuf[dev][tmpTail].ctrl1 = candev[dev]->msg15.ctrl1;
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rxMsgBuf[dev][tmpTail].arb = candev[dev]->msg15.arb;
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rxMsgBuf[dev][tmpTail].arb = candev[dev]->msg15.arb;
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rxMsgBuf[dev][tmpTail].cfg = candev[dev]->msg15.cfg;
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rxMsgBuf[dev][tmpTail].cfg = candev[dev]->msg15.cfg;
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pkt_len = (rxMsgBuf[dev][tmpTail].cfg >> 4) & 0xf;
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pkt_len = (rxMsgBuf[dev][tmpTail].cfg >> 4) & 0xf;
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for (i=0; i<pkt_len; i++) {
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for (i=0; i<pkt_len; i++) {
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rxMsgBuf[dev][tmpTail].data[i] = candev[dev]->msg15.data[i];
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rxMsgBuf[dev][tmpTail].data[i] = candev[dev]->msg15.data[i];
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}
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}
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tmpTail++;
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tmpTail++;
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if (tmpTail == RX_CAN_BUF_SIZE) {
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if (tmpTail == RX_CAN_BUF_SIZE) {
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tmpTail = 0;
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tmpTail = 0;
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}
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}
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rxMsgBufTail[dev] = tmpTail;
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rxMsgBufTail[dev] = tmpTail;
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break;
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break;
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}
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}
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tmpTail++;
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tmpTail++;
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if (tmpTail == RX_CAN_BUF_SIZE) {
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if (tmpTail == RX_CAN_BUF_SIZE) {
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tmpTail = 0;
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tmpTail = 0;
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}
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}
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if (tmpTail == rxMsgBufTail[dev]) {
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if (tmpTail == rxMsgBufTail[dev]) {
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break;
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break;
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}
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}
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}
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}
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candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET |
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candev[dev]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET |
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I82527_MSG_CTRL_INTPND_CLR);
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I82527_MSG_CTRL_INTPND_CLR);
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candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR |
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candev[dev]->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR |
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I82527_MSG_CTRL_RMTPND_CLR);
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I82527_MSG_CTRL_RMTPND_CLR);
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candev[dev]->status = 0x0;
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candev[dev]->status = 0x0;
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}
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}
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rtems_device_driver canbus_initialize(
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rtems_device_driver canbus_initialize(
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rtems_device_major_number major,
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rtems_device_major_number major,
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rtems_device_minor_number minor,
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rtems_device_minor_number minor,
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void *arg
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void *arg
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)
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)
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{
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{
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int i,j;
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int i,j;
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char dev_str[16]; /* This allows us to have a device name up to */
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char dev_str[16]; /* This allows us to have a device name up to */
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/* 15 chars long. If we only use names like */
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/* 15 chars long. If we only use names like */
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/* /dev/can0 (9 chars) we will be fine up to */
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/* /dev/can0 (9 chars) we will be fine up to */
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/* /dev/can9999999 */
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/* /dev/can9999999 */
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rtems_status_code status;
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rtems_status_code status;
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rtems_isr_entry old_handler;
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rtems_isr_entry old_handler;
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#if (NUM_CAN_DEVS > 0)
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#if (NUM_CAN_DEVS > 0)
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candev[0]=&canbus0;
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candev[0]=&canbus0;
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rtems_interrupt_catch (canInterruptHandler,
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rtems_interrupt_catch (canInterruptHandler,
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PPC_IRQ_IRQ3,
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PPC_IRQ_IRQ3,
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&old_handler);
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&old_handler);
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#if (NUM_CAN_DEVS > 1)
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#if (NUM_CAN_DEVS > 1)
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candev[1]=&canbus1;
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candev[1]=&canbus1;
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rtems_interrupt_catch (canInterruptHandler,
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rtems_interrupt_catch (canInterruptHandler,
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PPC_IRQ_IRQ4,
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PPC_IRQ_IRQ4,
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&old_handler);
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&old_handler);
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#if (NUM_CAN_DEVS > 2)
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#if (NUM_CAN_DEVS > 2)
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candev[2]=&canbus2;
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candev[2]=&canbus2;
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rtems_interrupt_catch (canInterruptHandler,
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rtems_interrupt_catch (canInterruptHandler,
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PPC_IRQ_IRQ2,
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PPC_IRQ_IRQ2,
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&old_handler);
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&old_handler);
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/* Right now, we only support 3 CAN interfaces */
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/* Right now, we only support 3 CAN interfaces */
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#else
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#else
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#error NUM_CAN_DEVS is too big. Fix it, damnit!
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#error NUM_CAN_DEVS is too big. Fix it, damnit!
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#endif /* NUM_CAN_DEVS > 2 */
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#endif /* NUM_CAN_DEVS > 2 */
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#endif /* NUM_CAN_DEVS > 1 */
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#endif /* NUM_CAN_DEVS > 1 */
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#else
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#else
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#error NUM_CAN_DEVS is 0. It needs to be at least 1
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#error NUM_CAN_DEVS is 0. It needs to be at least 1
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#endif /* NUM_CAN_DEVS > 0 */
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#endif /* NUM_CAN_DEVS > 0 */
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for (i=0; i < NUM_CAN_DEVS; i++) {
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for (i=0; i < NUM_CAN_DEVS; i++) {
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/* clear rx buffers */
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/* clear rx buffers */
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rxMsgBufHead[i] = 0;
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rxMsgBufHead[i] = 0;
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rxMsgBufTail[i] = 0;
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rxMsgBufTail[i] = 0;
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for (j=0; j < RX_CAN_BUF_SIZE; j++) {
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for (j=0; j < RX_CAN_BUF_SIZE; j++) {
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rxMsgBuf[i][j].ctrl0 = 0x55; /* all flags are cleared */
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rxMsgBuf[i][j].ctrl0 = 0x55; /* all flags are cleared */
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rxMsgBuf[i][j].ctrl1 = 0x55; /* all flags are cleared */
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rxMsgBuf[i][j].ctrl1 = 0x55; /* all flags are cleared */
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}
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}
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candev[i]->ctrl = I82527_CTRL_CCE | /* Enable cfg reg writes */
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candev[i]->ctrl = I82527_CTRL_CCE | /* Enable cfg reg writes */
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I82527_CTRL_INIT; /* Disable external xfers */
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I82527_CTRL_INIT; /* Disable external xfers */
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candev[i]->cir = I82527_CIR_DMC; /* Divide memory clock by 2 */
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candev[i]->cir = I82527_CIR_DMC; /* Divide memory clock by 2 */
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/* We want 250 kbps so assuming an input clock rate of 10 MHz:
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/* We want 250 kbps so assuming an input clock rate of 10 MHz:
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* DSC = 0 => SCLK = 10 MHz, tSCLK = 100ns
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* DSC = 0 => SCLK = 10 MHz, tSCLK = 100ns
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* BRP = 1 => tq = 200ns
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* BRP = 1 => tq = 200ns
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* tSYNC_SEG = 1 tq
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* tSYNC_SEG = 1 tq
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* tSEG1 = TSEG1+1 = 14+1 = 15
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* tSEG1 = TSEG1+1 = 14+1 = 15
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* tSEG2 = TSEG2+1 = 3+1 = 4
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* tSEG2 = TSEG2+1 = 3+1 = 4
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*
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*
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* bittime = tSYNC_SEG + tSEG1 + tSEG2
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* bittime = tSYNC_SEG + tSEG1 + tSEG2
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* = 1 + 15 + 4 = 20
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* = 1 + 15 + 4 = 20
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* baudrate = 1/(bittime * tq) = 1/(20 * 200ns) = 1/(4000ns) = 250 kbps
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* baudrate = 1/(bittime * tq) = 1/(20 * 200ns) = 1/(4000ns) = 250 kbps
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*/
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*/
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candev[i]->btr0 = 0xc1; /* Baud rate prescaler=0, Sync jump width=3 */
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candev[i]->btr0 = 0xc1; /* Baud rate prescaler=0, Sync jump width=3 */
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candev[i]->btr1 = I82527_BTR1_SPL | /* go for noise immunity */
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candev[i]->btr1 = I82527_BTR1_SPL | /* go for noise immunity */
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(0x3 << 4) | /* TSEG2 = 3 */
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(0x3 << 4) | /* TSEG2 = 3 */
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(0xe); /* TSEG1 = 14 */
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(0xe); /* TSEG1 = 14 */
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candev[i]->gms = 0xffff; /* addresses must match exactly */
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candev[i]->gms = 0xffff; /* addresses must match exactly */
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candev[i]->gml = 0xffffffff; /* addresses must match exactly */
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candev[i]->gml = 0xffffffff; /* addresses must match exactly */
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candev[i]->mlm = 0x0; /* all addresses accepted */
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candev[i]->mlm = 0x0; /* all addresses accepted */
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candev[i]->p2conf = 0xff; /* make all outputs */
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candev[i]->p2conf = 0xff; /* make all outputs */
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candev[i]->msg1.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg1.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg1.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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candev[i]->msg1.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_INTPND_CLR;
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I82527_MSG_CTRL_INTPND_CLR;
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|
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candev[i]->msg2.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg2.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg2.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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candev[i]->msg2.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_INTPND_CLR;
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I82527_MSG_CTRL_INTPND_CLR;
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candev[i]->msg3.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg3.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg3.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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candev[i]->msg3.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_INTPND_CLR;
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I82527_MSG_CTRL_INTPND_CLR;
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candev[i]->msg4.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg4.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg4.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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candev[i]->msg4.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */
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I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */
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I82527_MSG_CTRL_INTPND_CLR;
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I82527_MSG_CTRL_INTPND_CLR;
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|
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candev[i]->msg5.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg5.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg5.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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candev[i]->msg5.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
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I82527_MSG_CTRL_INTPND_CLR;
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I82527_MSG_CTRL_INTPND_CLR;
|
|
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candev[i]->msg6.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg6.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg6.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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candev[i]->msg6.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
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I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
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I82527_MSG_CTRL_INTPND_CLR;
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|
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candev[i]->msg7.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg7.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
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candev[i]->msg7.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg7.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg8.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg8.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg8.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg8.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg9.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg9.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg9.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg9.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg10.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg10.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg10.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg10.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR | /* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg11.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg11.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg11.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg11.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg12.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg12.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg12.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg12.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg13.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg13.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg13.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg13.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg14.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg14.cfg = I82527_MSG_CFG_DIR ; /* dir is xmit */
|
candev[i]->msg14.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg14.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
|
|
candev[i]->msg15.cfg = 0 ; /* dir is rcv */
|
candev[i]->msg15.cfg = 0 ; /* dir is rcv */
|
candev[i]->msg15.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
candev[i]->msg15.ctrl0 = I82527_MSG_CTRL_MSGVAL_CLR |/* this msg invalid */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_TXIE_CLR |/* no tx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_RXIE_CLR |/* no rx interrupts */
|
I82527_MSG_CTRL_INTPND_CLR;
|
I82527_MSG_CTRL_INTPND_CLR;
|
candev[i]->msg15.ctrl1 = I82527_MSG_CTRL_RMTPND_CLR |
|
candev[i]->msg15.ctrl1 = I82527_MSG_CTRL_RMTPND_CLR |
|
I82527_MSG_CTRL_TXRQ_CLR |
|
I82527_MSG_CTRL_TXRQ_CLR |
|
I82527_MSG_CTRL_MSGLST_CLR |
|
I82527_MSG_CTRL_MSGLST_CLR |
|
I82527_MSG_CTRL_NEWDAT_CLR;
|
I82527_MSG_CTRL_NEWDAT_CLR;
|
|
|
}
|
}
|
|
|
if ((status=rtems_io_register_name ("/dev/can0", major, 0)) !=
|
if ((status=rtems_io_register_name ("/dev/can0", major, 0)) !=
|
RTEMS_SUCCESSFUL) {
|
RTEMS_SUCCESSFUL) {
|
rtems_fatal_error_occurred (status);
|
rtems_fatal_error_occurred (status);
|
}
|
}
|
if ((status=rtems_io_register_name ("/dev/can1", major, 1)) !=
|
if ((status=rtems_io_register_name ("/dev/can1", major, 1)) !=
|
RTEMS_SUCCESSFUL) {
|
RTEMS_SUCCESSFUL) {
|
rtems_fatal_error_occurred (status);
|
rtems_fatal_error_occurred (status);
|
}
|
}
|
if ((status=rtems_io_register_name ("/dev/can2", major, 2)) !=
|
if ((status=rtems_io_register_name ("/dev/can2", major, 2)) !=
|
RTEMS_SUCCESSFUL) {
|
RTEMS_SUCCESSFUL) {
|
rtems_fatal_error_occurred (status);
|
rtems_fatal_error_occurred (status);
|
}
|
}
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
}
|
}
|
|
|
rtems_device_driver canbus_open(
|
rtems_device_driver canbus_open(
|
rtems_device_major_number major,
|
rtems_device_major_number major,
|
rtems_device_minor_number minor,
|
rtems_device_minor_number minor,
|
void * arg
|
void * arg
|
)
|
)
|
{
|
{
|
/* msg is in use, rx interrupts are enabled */
|
/* msg is in use, rx interrupts are enabled */
|
candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET |
|
candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET |
|
I82527_MSG_CTRL_RXIE_SET);
|
I82527_MSG_CTRL_RXIE_SET);
|
|
|
candev[minor]->ctrl |= I82527_CTRL_IE;
|
candev[minor]->ctrl |= I82527_CTRL_IE;
|
candev[minor]->ctrl &= ~(I82527_CTRL_CCE | I82527_CTRL_INIT);
|
candev[minor]->ctrl &= ~(I82527_CTRL_CCE | I82527_CTRL_INIT);
|
switch (minor) {
|
switch (minor) {
|
case 0: m860.simask |= M860_SIMASK_IRM3; break;
|
case 0: m860.simask |= M860_SIMASK_IRM3; break;
|
case 1: m860.simask |= M860_SIMASK_IRM4; break;
|
case 1: m860.simask |= M860_SIMASK_IRM4; break;
|
case 2: m860.simask |= M860_SIMASK_IRM2; break;
|
case 2: m860.simask |= M860_SIMASK_IRM2; break;
|
default: return;
|
default: return;
|
}
|
}
|
|
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
}
|
}
|
|
|
rtems_device_driver canbus_close(
|
rtems_device_driver canbus_close(
|
rtems_device_major_number major,
|
rtems_device_major_number major,
|
rtems_device_minor_number minor,
|
rtems_device_minor_number minor,
|
void * arg
|
void * arg
|
)
|
)
|
{
|
{
|
/* msg is not in use, rx & txinterrupts are disbled */
|
/* msg is not in use, rx & txinterrupts are disbled */
|
candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_CLR |
|
candev[minor]->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_CLR |
|
I82527_MSG_CTRL_RXIE_CLR |
|
I82527_MSG_CTRL_RXIE_CLR |
|
I82527_MSG_CTRL_TXIE_CLR);
|
I82527_MSG_CTRL_TXIE_CLR);
|
|
|
/* Take transceiver off the bus, enable cfg. reg. writes */
|
/* Take transceiver off the bus, enable cfg. reg. writes */
|
candev[minor]->ctrl |= (I82527_CTRL_CCE | I82527_CTRL_INIT);
|
candev[minor]->ctrl |= (I82527_CTRL_CCE | I82527_CTRL_INIT);
|
|
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
}
|
}
|
|
|
|
|
rtems_device_driver canbus_read(
|
rtems_device_driver canbus_read(
|
rtems_device_major_number major,
|
rtems_device_major_number major,
|
rtems_device_minor_number minor,
|
rtems_device_minor_number minor,
|
void * arg
|
void * arg
|
)
|
)
|
{
|
{
|
i82527_msg_t *msg;
|
i82527_msg_t *msg;
|
int i;
|
int i;
|
int tmpHead;
|
int tmpHead;
|
|
|
msg = arg;
|
msg = arg;
|
tmpHead = rxMsgBufHead[minor];
|
tmpHead = rxMsgBufHead[minor];
|
|
|
while (1){
|
while (1){
|
if ((tmpHead == rxMsgBufTail[minor]) &&
|
if ((tmpHead == rxMsgBufTail[minor]) &&
|
!(rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
|
!(rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT)) {
|
break;
|
break;
|
}
|
}
|
if (rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT) {
|
if (rxMsgBuf[minor][tmpHead].ctrl1 & I82527_MSG_CTRL_NEWDAT) {
|
int pkt_len;
|
int pkt_len;
|
msg->ctrl0 = rxMsgBuf[minor][tmpHead].ctrl0;
|
msg->ctrl0 = rxMsgBuf[minor][tmpHead].ctrl0;
|
msg->ctrl1 = rxMsgBuf[minor][tmpHead].ctrl1;
|
msg->ctrl1 = rxMsgBuf[minor][tmpHead].ctrl1;
|
msg->arb = rxMsgBuf[minor][tmpHead].arb;
|
msg->arb = rxMsgBuf[minor][tmpHead].arb;
|
msg->cfg = rxMsgBuf[minor][tmpHead].cfg;
|
msg->cfg = rxMsgBuf[minor][tmpHead].cfg;
|
|
|
pkt_len = (msg->cfg >> 4) & 0xf;
|
pkt_len = (msg->cfg >> 4) & 0xf;
|
for (i=0; i<pkt_len; i++) {
|
for (i=0; i<pkt_len; i++) {
|
msg->data[i] = rxMsgBuf[minor][tmpHead].data[i];
|
msg->data[i] = rxMsgBuf[minor][tmpHead].data[i];
|
}
|
}
|
rxMsgBuf[minor][tmpHead].ctrl1 = 0xff & I82527_MSG_CTRL_NEWDAT_CLR;
|
rxMsgBuf[minor][tmpHead].ctrl1 = 0xff & I82527_MSG_CTRL_NEWDAT_CLR;
|
|
|
tmpHead++;
|
tmpHead++;
|
if (tmpHead == RX_CAN_BUF_SIZE) {
|
if (tmpHead == RX_CAN_BUF_SIZE) {
|
tmpHead = 0;
|
tmpHead = 0;
|
}
|
}
|
rxMsgBufHead[minor] = tmpHead;
|
rxMsgBufHead[minor] = tmpHead;
|
|
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
|
|
}
|
}
|
|
|
tmpHead++;
|
tmpHead++;
|
if (tmpHead == RX_CAN_BUF_SIZE) {
|
if (tmpHead == RX_CAN_BUF_SIZE) {
|
tmpHead = 0;
|
tmpHead = 0;
|
}
|
}
|
if (tmpHead == rxMsgBufHead[minor]) {
|
if (tmpHead == rxMsgBufHead[minor]) {
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
return RTEMS_UNSATISFIED;
|
return RTEMS_UNSATISFIED;
|
|
|
}
|
}
|
|
|
rtems_device_driver canbus_write(
|
rtems_device_driver canbus_write(
|
rtems_device_major_number major,
|
rtems_device_major_number major,
|
rtems_device_minor_number minor,
|
rtems_device_minor_number minor,
|
void * arg
|
void * arg
|
)
|
)
|
{
|
{
|
i82527_msg_t *msg;
|
i82527_msg_t *msg;
|
int i;
|
int i;
|
|
|
msg = arg;
|
msg = arg;
|
while(candev[minor]->msg1.ctrl1 & I82527_MSG_CTRL_TXRQ){
|
while(candev[minor]->msg1.ctrl1 & I82527_MSG_CTRL_TXRQ){
|
continue;
|
continue;
|
}
|
}
|
candev[minor]->msg1.ctrl1 = 0xff & I82527_MSG_CTRL_CPUUPD_SET;
|
candev[minor]->msg1.ctrl1 = 0xff & I82527_MSG_CTRL_CPUUPD_SET;
|
|
|
candev[minor]->msg1.cfg = msg->cfg;
|
candev[minor]->msg1.cfg = msg->cfg;
|
candev[minor]->msg1.arb = msg->arb;
|
candev[minor]->msg1.arb = msg->arb;
|
|
|
for (i=0; i < ((msg->cfg >> 4) & 0xff); i++) {
|
for (i=0; i < ((msg->cfg >> 4) & 0xff); i++) {
|
candev[minor]->msg1.data[i] = msg->data[i];
|
candev[minor]->msg1.data[i] = msg->data[i];
|
}
|
}
|
|
|
candev[minor]->msg1.ctrl0 = 0xff & (I82527_MSG_CTRL_INTPND_CLR |
|
candev[minor]->msg1.ctrl0 = 0xff & (I82527_MSG_CTRL_INTPND_CLR |
|
I82527_MSG_CTRL_MSGVAL_SET |
|
I82527_MSG_CTRL_MSGVAL_SET |
|
I82527_MSG_CTRL_TXIE_CLR);
|
I82527_MSG_CTRL_TXIE_CLR);
|
candev[minor]->msg1.cfg |= I82527_MSG_CFG_DIR;
|
candev[minor]->msg1.cfg |= I82527_MSG_CFG_DIR;
|
candev[minor]->msg1.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_SET |
|
candev[minor]->msg1.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_SET |
|
I82527_MSG_CTRL_CPUUPD_CLR |
|
I82527_MSG_CTRL_CPUUPD_CLR |
|
I82527_MSG_CTRL_TXRQ_SET);
|
I82527_MSG_CTRL_TXRQ_SET);
|
|
|
|
|
|
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
}
|
}
|
rtems_device_driver canbus_control(
|
rtems_device_driver canbus_control(
|
rtems_device_major_number major,
|
rtems_device_major_number major,
|
rtems_device_minor_number minor,
|
rtems_device_minor_number minor,
|
void * arg
|
void * arg
|
)
|
)
|
{
|
{
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
}
|
}
|
|
|
|
|
/* part of old canbus_read */
|
/* part of old canbus_read */
|
#if 0
|
#if 0
|
for (i=0; i < RX_CAN_BUF_SIZE) {
|
for (i=0; i < RX_CAN_BUF_SIZE) {
|
if (rxMsgBuf[minor][i].ctrl1 & I82527_MSG_CTRL_NEWDAT)
|
if (rxMsgBuf[minor][i].ctrl1 & I82527_MSG_CTRL_NEWDAT)
|
break;
|
break;
|
}
|
}
|
|
|
if (i < RX_CAN_BUF_SIZE) {
|
if (i < RX_CAN_BUF_SIZE) {
|
int pkt_len;
|
int pkt_len;
|
int j;
|
int j;
|
msg.arb = rxMsgBuf[minor][i].arb;
|
msg.arb = rxMsgBuf[minor][i].arb;
|
msg.cfg = rxMsgBuf[minor][i].cfg;
|
msg.cfg = rxMsgBuf[minor][i].cfg;
|
|
|
pkt_len = (msg.cfg >> 4) & 0xf;
|
pkt_len = (msg.cfg >> 4) & 0xf;
|
|
|
for (j=0; j < pkt_len; j++)
|
for (j=0; j < pkt_len; j++)
|
msg.data[j] = rxMsgBuf[minor][i].data[j];
|
msg.data[j] = rxMsgBuf[minor][i].data[j];
|
|
|
|
|
/* wait until there is a msg */
|
/* wait until there is a msg */
|
while (!(candev->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT))
|
while (!(candev->msg15.ctrl1 & I82527_MSG_CTRL_NEWDAT))
|
continue;
|
continue;
|
|
|
msg->ctrl1 = candev->msg15.ctrl1;
|
msg->ctrl1 = candev->msg15.ctrl1;
|
msg->cfg = candev->msg15.cfg;
|
msg->cfg = candev->msg15.cfg;
|
msg->arb = candev->msg15.arb;
|
msg->arb = candev->msg15.arb;
|
|
|
for (i=0; i < ((candev->msg15.cfg >> 4) & 0xff); i++) {
|
for (i=0; i < ((candev->msg15.cfg >> 4) & 0xff); i++) {
|
msg->data[i] = candev->msg15.data[i];
|
msg->data[i] = candev->msg15.data[i];
|
}
|
}
|
|
|
candev->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET |
|
candev->msg15.ctrl0 = 0xff & (I82527_MSG_CTRL_MSGVAL_SET |
|
I82527_MSG_CTRL_INTPND_CLR);
|
I82527_MSG_CTRL_INTPND_CLR);
|
candev->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR |
|
candev->msg15.ctrl1 = 0xff & (I82527_MSG_CTRL_NEWDAT_CLR |
|
I82527_MSG_CTRL_RMTPND_CLR);
|
I82527_MSG_CTRL_RMTPND_CLR);
|
|
|
candev->status = 0x0;
|
candev->status = 0x0;
|
|
|
|
|
return RTEMS_SUCCESSFUL;
|
return RTEMS_SUCCESSFUL;
|
#endif
|
#endif
|
|
|
|
|
|
|