/* align_h.s 1.1 - 95/12/04
|
/* align_h.s 1.1 - 95/12/04
|
*
|
*
|
* This file contains the assembly code for the PowerPC 403
|
* This file contains the assembly code for the PowerPC 403
|
* alignment exception handler for RTEMS.
|
* alignment exception handler for RTEMS.
|
*
|
*
|
* Based upon IBM provided code with the following release:
|
* Based upon IBM provided code with the following release:
|
*
|
*
|
* This source code has been made available to you by IBM on an AS-IS
|
* This source code has been made available to you by IBM on an AS-IS
|
* basis. Anyone receiving this source is licensed under IBM
|
* basis. Anyone receiving this source is licensed under IBM
|
* copyrights to use it in any way he or she deems fit, including
|
* copyrights to use it in any way he or she deems fit, including
|
* copying it, modifying it, compiling it, and redistributing it either
|
* copying it, modifying it, compiling it, and redistributing it either
|
* with or without modifications. No license under IBM patents or
|
* with or without modifications. No license under IBM patents or
|
* patent applications is to be implied by the copyright license.
|
* patent applications is to be implied by the copyright license.
|
*
|
*
|
* Any user of this software should understand that IBM cannot provide
|
* Any user of this software should understand that IBM cannot provide
|
* technical support for this software and will not be responsible for
|
* technical support for this software and will not be responsible for
|
* any consequences resulting from the use of this software.
|
* any consequences resulting from the use of this software.
|
*
|
*
|
* Any person who transfers this source code or any derivative work
|
* Any person who transfers this source code or any derivative work
|
* must include the IBM copyright notice, this paragraph, and the
|
* must include the IBM copyright notice, this paragraph, and the
|
* preceding two paragraphs in the transferred software.
|
* preceding two paragraphs in the transferred software.
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*
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*
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* COPYRIGHT I B M CORPORATION 1995
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* COPYRIGHT I B M CORPORATION 1995
|
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*
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*
|
* Modifications:
|
* Modifications:
|
*
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*
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* Author: Andrew Bray
|
* Author: Andrew Bray
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*
|
*
|
* COPYRIGHT (c) 1995 by i-cubed ltd.
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* COPYRIGHT (c) 1995 by i-cubed ltd.
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*
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* To anyone who acknowledges that this file is provided "AS IS"
|
* without any express or implied warranty:
|
* without any express or implied warranty:
|
* permission to use, copy, modify, and distribute this file
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
|
* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
|
* the above copyright notice and this notice appears in all
|
* copies, and that the name of i-cubed limited not be used in
|
* copies, and that the name of i-cubed limited not be used in
|
* advertising or publicity pertaining to distribution of the
|
* advertising or publicity pertaining to distribution of the
|
* software without specific, written prior permission.
|
* software without specific, written prior permission.
|
* i-cubed limited makes no representations about the suitability
|
* i-cubed limited makes no representations about the suitability
|
* of this software for any purpose.
|
* of this software for any purpose.
|
*
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*
|
* $Id: align_h.S,v 1.2 2001-09-27 12:01:03 chris Exp $
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* $Id: align_h.S,v 1.2 2001-09-27 12:01:03 chris Exp $
|
*/
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*/
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|
|
#include "asm.h"
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#include "asm.h"
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#include "bsp.h"
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#include "bsp.h"
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|
|
.set CACHE_SIZE,16 # cache line size of 32 bytes
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.set CACHE_SIZE,16 # cache line size of 32 bytes
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.set CACHE_SIZE_L2,4 # cache line size, log 2
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.set CACHE_SIZE_L2,4 # cache line size, log 2
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|
|
.set Open_gpr0,0
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.set Open_gpr0,0
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.set Open_gpr1,4
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.set Open_gpr1,4
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.set Open_gpr2,8
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.set Open_gpr2,8
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.set Open_gpr3,12
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.set Open_gpr3,12
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.set Open_gpr4,16
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.set Open_gpr4,16
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.set Open_gpr5,20
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.set Open_gpr5,20
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.set Open_gpr6,24
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.set Open_gpr6,24
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.set Open_gpr7,28
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.set Open_gpr7,28
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.set Open_gpr8,32
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.set Open_gpr8,32
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.set Open_gpr9,36
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.set Open_gpr9,36
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.set Open_gpr10,40
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.set Open_gpr10,40
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.set Open_gpr11,44
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.set Open_gpr11,44
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.set Open_gpr12,48
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.set Open_gpr12,48
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.set Open_gpr13,52
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.set Open_gpr13,52
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.set Open_gpr14,56
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.set Open_gpr14,56
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.set Open_gpr15,60
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.set Open_gpr15,60
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.set Open_gpr16,64
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.set Open_gpr16,64
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.set Open_gpr17,68
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.set Open_gpr17,68
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.set Open_gpr18,72
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.set Open_gpr18,72
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.set Open_gpr19,76
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.set Open_gpr19,76
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.set Open_gpr20,80
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.set Open_gpr20,80
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.set Open_gpr21,84
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.set Open_gpr21,84
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.set Open_gpr22,88
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.set Open_gpr22,88
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.set Open_gpr23,92
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.set Open_gpr23,92
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.set Open_gpr24,96
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.set Open_gpr24,96
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.set Open_gpr25,100
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.set Open_gpr25,100
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.set Open_gpr26,104
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.set Open_gpr26,104
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.set Open_gpr27,108
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.set Open_gpr27,108
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.set Open_gpr28,112
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.set Open_gpr28,112
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.set Open_gpr29,116
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.set Open_gpr29,116
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.set Open_gpr30,120
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.set Open_gpr30,120
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.set Open_gpr31,124
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.set Open_gpr31,124
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.set Open_xer,128
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.set Open_xer,128
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.set Open_lr,132
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.set Open_lr,132
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.set Open_ctr,136
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.set Open_ctr,136
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.set Open_cr,140
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.set Open_cr,140
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.set Open_srr2,144
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.set Open_srr2,144
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.set Open_srr3,148
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.set Open_srr3,148
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.set Open_srr0,152
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.set Open_srr0,152
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.set Open_srr1,156
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.set Open_srr1,156
|
|
|
|
|
/*
|
/*
|
* This code makes several assumptions for processing efficiency
|
* This code makes several assumptions for processing efficiency
|
* * General purpose registers are continuous in the image, beginning with
|
* * General purpose registers are continuous in the image, beginning with
|
* Open_gpr0
|
* Open_gpr0
|
* * Hash table is highly dependent on opcodes - opcode changes *will*
|
* * Hash table is highly dependent on opcodes - opcode changes *will*
|
* require rework of the instruction decode mechanism.
|
* require rework of the instruction decode mechanism.
|
*/
|
*/
|
|
|
.text
|
.text
|
.globl align_h
|
.globl align_h
|
|
|
.align CACHE_SIZE_L2
|
.align CACHE_SIZE_L2
|
align_h:
|
align_h:
|
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
* Store GPRs in Open Reg save area
|
* Store GPRs in Open Reg save area
|
* Set up r2 as base reg, r1 pointing to Open Reg save area
|
* Set up r2 as base reg, r1 pointing to Open Reg save area
|
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
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stmw r0,ALIGN_REGS(r0)
|
stmw r0,ALIGN_REGS(r0)
|
li r1,ALIGN_REGS
|
li r1,ALIGN_REGS
|
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
* Store special purpose registers in reg save area
|
* Store special purpose registers in reg save area
|
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
mfxer r7
|
mfxer r7
|
mflr r8
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mflr r8
|
mfcr r9
|
mfcr r9
|
mfctr r10
|
mfctr r10
|
stw r7,Open_xer(r1)
|
stw r7,Open_xer(r1)
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stw r8,Open_lr(r1)
|
stw r8,Open_lr(r1)
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stw r9,Open_cr(r1)
|
stw r9,Open_cr(r1)
|
stw r10,Open_ctr(r1)
|
stw r10,Open_ctr(r1)
|
mfspr r7, srr2 /* SRR 2 */
|
mfspr r7, srr2 /* SRR 2 */
|
mfspr r8, srr3 /* SRR 3 */
|
mfspr r8, srr3 /* SRR 3 */
|
mfspr r9, srr0 /* SRR 0 */
|
mfspr r9, srr0 /* SRR 0 */
|
mfspr r10, srr1 /* SRR 1 */
|
mfspr r10, srr1 /* SRR 1 */
|
stw r7,Open_srr2(r1)
|
stw r7,Open_srr2(r1)
|
stw r8,Open_srr3(r1)
|
stw r8,Open_srr3(r1)
|
stw r9,Open_srr0(r1)
|
stw r9,Open_srr0(r1)
|
stw r10,Open_srr1(r1)
|
stw r10,Open_srr1(r1)
|
|
|
/* Set up common registers */
|
/* Set up common registers */
|
mfspr r5, dear /* DEAR: R5 is data exception address */
|
mfspr r5, dear /* DEAR: R5 is data exception address */
|
lwz r9,Open_srr0(r1) /* get faulting instruction */
|
lwz r9,Open_srr0(r1) /* get faulting instruction */
|
addi r7,r9,4 /* bump instruction */
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addi r7,r9,4 /* bump instruction */
|
stw r7,Open_srr0(r1) /* restore to image */
|
stw r7,Open_srr0(r1) /* restore to image */
|
lwz r9, 0(r9) /* retrieve actual instruction */
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lwz r9, 0(r9) /* retrieve actual instruction */
|
rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
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rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */
|
rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
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rlwinm r7,r9,6,26,31 /* r7 is primary opcode */
|
bl ref_point /* establish addressibility */
|
bl ref_point /* establish addressibility */
|
ref_point:
|
ref_point:
|
mflr r11 /* r11 is the anchor point for ref_point */
|
mflr r11 /* r11 is the anchor point for ref_point */
|
addi r10, r7, -31 /* r10 = r7 - 31 */
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addi r10, r7, -31 /* r10 = r7 - 31 */
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rlwinm r10,r10,2,2,31 /* r10 *= 4 */
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rlwinm r10,r10,2,2,31 /* r10 *= 4 */
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add r10, r10, r11 /* r10 += anchor point */
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add r10, r10, r11 /* r10 += anchor point */
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lwz r10, primary_jt-ref_point(r10)
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lwz r10, primary_jt-ref_point(r10)
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mtlr r10
|
mtlr r10
|
rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
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rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
|
la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
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la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
|
blr
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blr
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primary_jt:
|
primary_jt:
|
.long xform
|
.long xform
|
.long lwz
|
.long lwz
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.long lwzu
|
.long lwzu
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.long 0
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.long 0
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.long 0
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.long 0
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.long stw
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.long stw
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.long stwu
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.long stwu
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.long 0
|
.long 0
|
.long 0
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.long 0
|
.long lhz
|
.long lhz
|
.long lhzu
|
.long lhzu
|
.long lha
|
.long lha
|
.long lhau
|
.long lhau
|
.long sth
|
.long sth
|
.long sthu
|
.long sthu
|
.long lmw
|
.long lmw
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.long stmw
|
.long stmw
|
/*
|
/*
|
* handlers
|
* handlers
|
*/
|
*/
|
/*
|
/*
|
* xform instructions require an additional decode. Fortunately, a relatively
|
* xform instructions require an additional decode. Fortunately, a relatively
|
* simple hash step breaks the instructions out with no collisions
|
* simple hash step breaks the instructions out with no collisions
|
*/
|
*/
|
xform:
|
xform:
|
rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
|
rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */
|
rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
|
rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */
|
add r10,r7,r10 /* r10 = r7 + r10 */
|
add r10,r7,r10 /* r10 = r7 + r10 */
|
rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
|
rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */
|
add r10,r10,r11 /* r10 += anchor point */
|
add r10,r10,r11 /* r10 += anchor point */
|
lwz r10, secondary_ht-ref_point(r10)
|
lwz r10, secondary_ht-ref_point(r10)
|
mtlr r10
|
mtlr r10
|
la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
|
la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */
|
rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
|
rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */
|
blrl
|
blrl
|
|
|
secondary_ht:
|
secondary_ht:
|
.long lhzux /* b 0 0x137 */
|
.long lhzux /* b 0 0x137 */
|
.long lhax /* b 1 0x157 */
|
.long lhax /* b 1 0x157 */
|
.long lhaux /* b 2 0x177 */
|
.long lhaux /* b 2 0x177 */
|
.long sthx /* b 3 0x197 */
|
.long sthx /* b 3 0x197 */
|
.long sthux /* b 4 0x1b7 */
|
.long sthux /* b 4 0x1b7 */
|
.long 0 /* b 5 */
|
.long 0 /* b 5 */
|
.long lwbrx /* b 6 0x216 */
|
.long lwbrx /* b 6 0x216 */
|
.long 0 /* b 7 */
|
.long 0 /* b 7 */
|
.long 0 /* b 8 */
|
.long 0 /* b 8 */
|
.long 0 /* b 9 */
|
.long 0 /* b 9 */
|
.long stwbrx /* b A 0x296 */
|
.long stwbrx /* b A 0x296 */
|
.long 0 /* b B */
|
.long 0 /* b B */
|
.long 0 /* b C */
|
.long 0 /* b C */
|
.long 0 /* b D */
|
.long 0 /* b D */
|
.long lhbrx /* b E 0x316 */
|
.long lhbrx /* b E 0x316 */
|
.long 0 /* b F */
|
.long 0 /* b F */
|
.long 0 /* b 10 */
|
.long 0 /* b 10 */
|
.long 0 /* b 11 */
|
.long 0 /* b 11 */
|
.long sthbrx /* b 12 0x396 */
|
.long sthbrx /* b 12 0x396 */
|
.long 0 /* b 13 */
|
.long 0 /* b 13 */
|
.long lwarx /* b 14 0x014 */
|
.long lwarx /* b 14 0x014 */
|
.long dcbz /* b 15 0x3f6 */
|
.long dcbz /* b 15 0x3f6 */
|
.long 0 /* b 16 */
|
.long 0 /* b 16 */
|
.long lwzx /* b 17 0x017 */
|
.long lwzx /* b 17 0x017 */
|
.long lwzux /* b 18 0x037 */
|
.long lwzux /* b 18 0x037 */
|
.long 0 /* b 19 */
|
.long 0 /* b 19 */
|
.long stwcx /* b 1A 0x096 */
|
.long stwcx /* b 1A 0x096 */
|
.long stwx /* b 1B 0x097 */
|
.long stwx /* b 1B 0x097 */
|
.long stwux /* b 1C 0x0B7 */
|
.long stwux /* b 1C 0x0B7 */
|
.long 0 /* b 1D */
|
.long 0 /* b 1D */
|
.long 0 /* b 1E */
|
.long 0 /* b 1E */
|
.long lhzx /* b 1F 0x117 */
|
.long lhzx /* b 1F 0x117 */
|
|
|
/*
|
/*
|
* for all handlers
|
* for all handlers
|
* r4 - Addressability to interrupt context
|
* r4 - Addressability to interrupt context
|
* r5 - DEAR address (faulting data address)
|
* r5 - DEAR address (faulting data address)
|
* r6 - RA field * 4
|
* r6 - RA field * 4
|
* r7 - Address of GPR 0 in image
|
* r7 - Address of GPR 0 in image
|
* r8 - RD field * 4
|
* r8 - RD field * 4
|
* r9 - Failing instruction
|
* r9 - Failing instruction
|
*/
|
*/
|
|
|
/* Load halfword algebraic with update */
|
/* Load halfword algebraic with update */
|
lhau:
|
lhau:
|
/* Load halfword algebraic with update indexed */
|
/* Load halfword algebraic with update indexed */
|
lhaux:
|
lhaux:
|
stwx r5,r7,r6 /* update RA with effective addr */
|
stwx r5,r7,r6 /* update RA with effective addr */
|
|
|
/* Load halfword algebraic */
|
/* Load halfword algebraic */
|
lha:
|
lha:
|
/* Load halfword algebraic indexed */
|
/* Load halfword algebraic indexed */
|
lhax:
|
lhax:
|
lswi r10,r5,2 /* load two bytes into r10 */
|
lswi r10,r5,2 /* load two bytes into r10 */
|
srawi r10,r10,16 /* shift right 2 bytes, extending sign */
|
srawi r10,r10,16 /* shift right 2 bytes, extending sign */
|
stwx r10,r7,r8 /* update reg image */
|
stwx r10,r7,r8 /* update reg image */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* Load Half Word Byte-Reversed Indexed */
|
/* Load Half Word Byte-Reversed Indexed */
|
lhbrx:
|
lhbrx:
|
lswi r10,r5,2 /* load two bytes from DEAR into r10 */
|
lswi r10,r5,2 /* load two bytes from DEAR into r10 */
|
rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
|
rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */
|
stwbrx r10,r7,r8 /* store reversed in reg image */
|
stwbrx r10,r7,r8 /* store reversed in reg image */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* Load Half Word and Zero with Update */
|
/* Load Half Word and Zero with Update */
|
lhzu:
|
lhzu:
|
/* Load Half Word and Zero with Update Indexed */
|
/* Load Half Word and Zero with Update Indexed */
|
lhzux:
|
lhzux:
|
stwx r5,r7,r6 /* update RA with effective addr */
|
stwx r5,r7,r6 /* update RA with effective addr */
|
|
|
/* Load Half Word and Zero */
|
/* Load Half Word and Zero */
|
lhz:
|
lhz:
|
/* Load Half Word and Zero Indexed */
|
/* Load Half Word and Zero Indexed */
|
lhzx:
|
lhzx:
|
lswi r10,r5,2 /* load two bytes from DEAR into r10 */
|
lswi r10,r5,2 /* load two bytes from DEAR into r10 */
|
rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
|
rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */
|
stwx r10,r7,r8 /* update reg image */
|
stwx r10,r7,r8 /* update reg image */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/*
|
/*
|
* Load Multiple Word
|
* Load Multiple Word
|
*/
|
*/
|
lmw:
|
lmw:
|
lwzx r9,r6,r7 /* R9 contains saved value of RA */
|
lwzx r9,r6,r7 /* R9 contains saved value of RA */
|
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
|
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
|
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
|
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
|
subfic r8,r8,32 /* r8 is reg count to load */
|
subfic r8,r8,32 /* r8 is reg count to load */
|
mtctr r8 /* load counter */
|
mtctr r8 /* load counter */
|
addi r8,r8,-1 /* r8-- */
|
addi r8,r8,-1 /* r8-- */
|
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
|
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
|
add r5,r5,r8 /* update DEAR to point to last reg */
|
add r5,r5,r8 /* update DEAR to point to last reg */
|
lwmloop:
|
lwmloop:
|
lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
|
lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */
|
stwu r11,-4(r10) /* load image and decrement pointer */
|
stwu r11,-4(r10) /* load image and decrement pointer */
|
addi r5,r5,-4 /* decrement effective address */
|
addi r5,r5,-4 /* decrement effective address */
|
bdnz lwmloop
|
bdnz lwmloop
|
stwx r9,r6,r7 /* restore RA (in case it was trashed) */
|
stwx r9,r6,r7 /* restore RA (in case it was trashed) */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/*
|
/*
|
* Load Word and Reserve Indexed
|
* Load Word and Reserve Indexed
|
*/
|
*/
|
lwarx:
|
lwarx:
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
stwx r10,r7,r8 /* update reg image */
|
stwx r10,r7,r8 /* update reg image */
|
rlwinm r5,r5,0,0,29 /* Word align address */
|
rlwinm r5,r5,0,0,29 /* Word align address */
|
lwarx r10,0,r5 /* Set reservation */
|
lwarx r10,0,r5 /* Set reservation */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/*
|
/*
|
* Load Word Byte-Reversed Indexed
|
* Load Word Byte-Reversed Indexed
|
*/
|
*/
|
lwbrx:
|
lwbrx:
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
stwbrx r10,r7,r8 /* store reversed in reg image */
|
stwbrx r10,r7,r8 /* store reversed in reg image */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* Load Word and Zero with Update */
|
/* Load Word and Zero with Update */
|
lwzu:
|
lwzu:
|
/* Load Word and Zero with Update Indexed */
|
/* Load Word and Zero with Update Indexed */
|
lwzux:
|
lwzux:
|
stwx r5,r7,r6 /* update RA with effective addr */
|
stwx r5,r7,r6 /* update RA with effective addr */
|
|
|
/* Load Word and Zero */
|
/* Load Word and Zero */
|
lwz:
|
lwz:
|
/* Load Word and Zero Indexed */
|
/* Load Word and Zero Indexed */
|
lwzx:
|
lwzx:
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
lswi r10,r5,4 /* load four bytes from DEAR into r10 */
|
stwx r10,r7,r8 /* update reg image */
|
stwx r10,r7,r8 /* update reg image */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* Store instructions */
|
/* Store instructions */
|
|
|
/* */
|
/* */
|
/* Store Half Word and Update */
|
/* Store Half Word and Update */
|
sthu:
|
sthu:
|
/* Store Half Word and Update Indexed */
|
/* Store Half Word and Update Indexed */
|
sthux:
|
sthux:
|
stwx r5,r7,r6 /* Update RA with effective address */
|
stwx r5,r7,r6 /* Update RA with effective address */
|
|
|
/* Store Half Word */
|
/* Store Half Word */
|
sth:
|
sth:
|
/* Store Half Word Indexed */
|
/* Store Half Word Indexed */
|
sthx:
|
sthx:
|
lwzx r10,r8,r7 /* retrieve source register value */
|
lwzx r10,r8,r7 /* retrieve source register value */
|
rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
|
rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */
|
stswi r10,r5,2 /* store bytes to DEAR address */
|
stswi r10,r5,2 /* store bytes to DEAR address */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* */
|
/* */
|
/* Store Half Word Byte-Reversed Indexed */
|
/* Store Half Word Byte-Reversed Indexed */
|
sthbrx:
|
sthbrx:
|
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
|
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
|
stswi r10,r5,2 /* move two bytes to DEAR address */
|
stswi r10,r5,2 /* move two bytes to DEAR address */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* */
|
/* */
|
/* Store Multiple Word */
|
/* Store Multiple Word */
|
stmw:
|
stmw:
|
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
|
addi r10,r7,32*4 /* r10 points to r31 in image + 4 */
|
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
|
rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */
|
subfic r8,r8,32 /* r8 is reg count to load */
|
subfic r8,r8,32 /* r8 is reg count to load */
|
mtctr r8 /* load counter */
|
mtctr r8 /* load counter */
|
addi r8,r8,-1 /* r8-- */
|
addi r8,r8,-1 /* r8-- */
|
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
|
rlwinm r8,r8,2,2,31 /* r8 *= 4 */
|
add r5,r5,r8 /* update DEAR to point to last reg */
|
add r5,r5,r8 /* update DEAR to point to last reg */
|
stmloop:
|
stmloop:
|
lwzu r11,-4(r10) /* get register value */
|
lwzu r11,-4(r10) /* get register value */
|
stswi r11,r5,4 /* output to DEAR address */
|
stswi r11,r5,4 /* output to DEAR address */
|
addi r5,r5,-4 /* decrement effective address */
|
addi r5,r5,-4 /* decrement effective address */
|
bdnz stmloop
|
bdnz stmloop
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* */
|
/* */
|
/* Store Word and Update */
|
/* Store Word and Update */
|
stwu:
|
stwu:
|
/* Store Word and Update Indexed */
|
/* Store Word and Update Indexed */
|
stwux:
|
stwux:
|
stwx r5,r7,r6 /* Update RA with effective address */
|
stwx r5,r7,r6 /* Update RA with effective address */
|
|
|
/* Store Word */
|
/* Store Word */
|
stw:
|
stw:
|
/* Store Word Indexed */
|
/* Store Word Indexed */
|
stwx:
|
stwx:
|
lwzx r10,r8,r7 /* retrieve source register value */
|
lwzx r10,r8,r7 /* retrieve source register value */
|
stswi r10,r5,4 /* store bytes to DEAR address */
|
stswi r10,r5,4 /* store bytes to DEAR address */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* */
|
/* */
|
/* Store Word Byte-Reversed Indexed */
|
/* Store Word Byte-Reversed Indexed */
|
stwbrx:
|
stwbrx:
|
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
|
lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */
|
stswi r10,r5,4 /* move two bytes to DEAR address */
|
stswi r10,r5,4 /* move two bytes to DEAR address */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* */
|
/* */
|
/* Store Word Conditional Indexed */
|
/* Store Word Conditional Indexed */
|
stwcx:
|
stwcx:
|
rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
|
rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */
|
lwz r11,0(r10) /* save original value of store */
|
lwz r11,0(r10) /* save original value of store */
|
stwcx. r11,r0,r10 /* attempt store to address */
|
stwcx. r11,r0,r10 /* attempt store to address */
|
bne stwcx_moveon /* store failed, move on */
|
bne stwcx_moveon /* store failed, move on */
|
stw r11,0(r10) /* repair damage */
|
stw r11,0(r10) /* repair damage */
|
lwzx r9,r7,r8 /* get register value */
|
lwzx r9,r7,r8 /* get register value */
|
stswi r10,r5,4 /* store bytes to DEAR address */
|
stswi r10,r5,4 /* store bytes to DEAR address */
|
stwcx_moveon:
|
stwcx_moveon:
|
mfcr r11 /* get condition reg */
|
mfcr r11 /* get condition reg */
|
lwz r9,Open_cr(r1) /* get condition reg image */
|
lwz r9,Open_cr(r1) /* get condition reg image */
|
rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
|
rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */
|
lwz r11,Open_xer(r1) /* get XER reg */
|
lwz r11,Open_xer(r1) /* get XER reg */
|
rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
|
rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */
|
stw r9,Open_cr(r1) /* store cr image */
|
stw r9,Open_cr(r1) /* store cr image */
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
/* */
|
/* */
|
/* Data Cache Block Zero */
|
/* Data Cache Block Zero */
|
dcbz:
|
dcbz:
|
rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
|
rlwinm r5,r5,0,0,31-CACHE_SIZE_L2
|
/* get address to nearest Cache line */
|
/* get address to nearest Cache line */
|
addi r5,r5,-4 /* adjust by a word */
|
addi r5,r5,-4 /* adjust by a word */
|
addi r10,r0,CACHE_SIZE/4 /* set counter value */
|
addi r10,r0,CACHE_SIZE/4 /* set counter value */
|
mtctr r10
|
mtctr r10
|
addi r11,r0,0 /* r11 = 0 */
|
addi r11,r0,0 /* r11 = 0 */
|
dcbz_loop:
|
dcbz_loop:
|
stwu r11,4(r5) /* store a word and update EA */
|
stwu r11,4(r5) /* store a word and update EA */
|
bdnz dcbz_loop
|
bdnz dcbz_loop
|
b align_complete /* return */
|
b align_complete /* return */
|
|
|
align_complete:
|
align_complete:
|
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
* Restore regs and return from the interrupt
|
* Restore regs and return from the interrupt
|
*----------------------------------------------------------------------*/
|
*----------------------------------------------------------------------*/
|
lmw r24,Open_xer+ALIGN_REGS(r0)
|
lmw r24,Open_xer+ALIGN_REGS(r0)
|
mtxer r24
|
mtxer r24
|
mtlr r25
|
mtlr r25
|
mtctr r26
|
mtctr r26
|
mtcrf 0xFF, r27
|
mtcrf 0xFF, r27
|
mtspr srr2, r28 /* SRR 2 */
|
mtspr srr2, r28 /* SRR 2 */
|
mtspr srr3, r29 /* SRR 3 */
|
mtspr srr3, r29 /* SRR 3 */
|
mtspr srr0, r30 /* SRR 0 */
|
mtspr srr0, r30 /* SRR 0 */
|
mtspr srr1, r31 /* SRR 1 */
|
mtspr srr1, r31 /* SRR 1 */
|
lmw r1,Open_gpr1+ALIGN_REGS(r0)
|
lmw r1,Open_gpr1+ALIGN_REGS(r0)
|
lwz r0,Open_gpr0+ALIGN_REGS(r0)
|
lwz r0,Open_gpr0+ALIGN_REGS(r0)
|
rfi
|
rfi
|
|
|
