/*
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/*
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* This file contains the console driver chip level routines for the
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* This file contains the console driver chip level routines for the
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* z85c30 chip.
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* z85c30 chip.
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*
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*
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* Currently only polled mode is supported.
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* Currently only polled mode is supported.
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*
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*
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* COPYRIGHT (c) 1989-1997.
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* COPYRIGHT (c) 1989-1997.
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* On-Line Applications Research Corporation (OAR).
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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* Copyright assigned to U.S. Government, 1994.
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*
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*
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* The license and distribution terms for this file may be
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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* http://www.OARcorp.com/rtems/license.html.
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*
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*
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* $Id:
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* $Id:
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*/
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*/
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|
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#include <rtems.h>
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#include <rtems.h>
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#include <bsp.h>
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#include <bsp.h>
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#include <rtems/libio.h>
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#include <rtems/libio.h>
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#include <assert.h>
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#include <assert.h>
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|
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#include "85c30.h"
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#include "85c30.h"
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#include "consolebsp.h"
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#include "consolebsp.h"
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|
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#define STATUS_REGISTER 0x00
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#define STATUS_REGISTER 0x00
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#define DATA_REGISTER 0x08
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#define DATA_REGISTER 0x08
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|
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|
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#define Z8530_Status_Is_RX_character_available( _status ) \
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#define Z8530_Status_Is_RX_character_available( _status ) \
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( (_status) & 0x01 )
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( (_status) & 0x01 )
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|
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#define Z8530_Status_Is_TX_buffer_empty( _status ) \
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#define Z8530_Status_Is_TX_buffer_empty( _status ) \
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( (_status) & 0x04 )
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( (_status) & 0x04 )
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|
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#define Z8530_Status_Is_break_abort( _status ) \
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#define Z8530_Status_Is_break_abort( _status ) \
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( (_status) & 0x80 )
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( (_status) & 0x80 )
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|
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typedef struct {
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typedef struct {
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unsigned char read_setup;
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unsigned char read_setup;
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unsigned char write_setup;
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unsigned char write_setup;
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unsigned char mask_value;
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unsigned char mask_value;
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} char_size_info;
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} char_size_info;
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|
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static const char_size_info Char_size_85c30[] = {
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static const char_size_info Char_size_85c30[] = {
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{ Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF },
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{ Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF },
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{ Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F },
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{ Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F },
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{ Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F },
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{ Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F },
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{ Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F }
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{ Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F }
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};
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};
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|
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static const unsigned char Clock_speed_85c30[] = {
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static const unsigned char Clock_speed_85c30[] = {
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Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK };
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Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK };
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|
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static const unsigned char Stop_bit_85c30[] = {
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static const unsigned char Stop_bit_85c30[] = {
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Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 };
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Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 };
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|
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static const unsigned char Parity_85c30[] = {
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static const unsigned char Parity_85c30[] = {
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Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN };
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Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN };
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|
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/* PAGE
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/* PAGE
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*
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*
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* Read_85c30_register
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* Read_85c30_register
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*
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*
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* Read a Z85c30 register
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* Read a Z85c30 register
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*/
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*/
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static unsigned char Read_85c30_register(
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static unsigned char Read_85c30_register(
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volatile unsigned char *csr, /* IN */
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volatile unsigned char *csr, /* IN */
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unsigned char register_number /* IN */
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unsigned char register_number /* IN */
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)
|
)
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{
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{
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unsigned char Data;
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unsigned char Data;
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|
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*csr = register_number;
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*csr = register_number;
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|
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delay_in_bus_cycles( 40 );
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delay_in_bus_cycles( 40 );
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|
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Data = *csr;
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Data = *csr;
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|
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delay_in_bus_cycles( 40 );
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delay_in_bus_cycles( 40 );
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|
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return Data;
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return Data;
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}
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}
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|
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/*
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/*
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* Write_85c30_register
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* Write_85c30_register
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*
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*
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* Write a Z85c30 register
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* Write a Z85c30 register
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*/
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*/
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static void Write_85c30_register(
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static void Write_85c30_register(
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volatile unsigned char *csr, /* IN */
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volatile unsigned char *csr, /* IN */
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unsigned char register_number, /* IN */
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unsigned char register_number, /* IN */
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unsigned char data /* IN */
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unsigned char data /* IN */
|
)
|
)
|
{
|
{
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*csr = register_number;
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*csr = register_number;
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|
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delay_in_bus_cycles( 40 );
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delay_in_bus_cycles( 40 );
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|
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*csr = data;
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*csr = data;
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|
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delay_in_bus_cycles( 40 );
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delay_in_bus_cycles( 40 );
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}
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}
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|
|
|
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/* PAGE
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/* PAGE
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*
|
*
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* Reset_85c30_chip
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* Reset_85c30_chip
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*
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*
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* Reset a 85c30 chip. The pointers for the control registers for both
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* Reset a 85c30 chip. The pointers for the control registers for both
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* ports on the chip are used as input.
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* ports on the chip are used as input.
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*/
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*/
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void Reset_85c30_chip(
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void Reset_85c30_chip(
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volatile unsigned char *ctrl_0, /* IN */
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volatile unsigned char *ctrl_0, /* IN */
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volatile unsigned char *ctrl_1 /* IN */
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volatile unsigned char *ctrl_1 /* IN */
|
)
|
)
|
{
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{
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Write_85c30_register( ctrl_0, 0x09, 0x80 );
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Write_85c30_register( ctrl_0, 0x09, 0x80 );
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Write_85c30_register( ctrl_1, 0x09, 0x40 );
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Write_85c30_register( ctrl_1, 0x09, 0x40 );
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}
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}
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|
|
|
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/* PAGE
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/* PAGE
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*
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*
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* initialize_85c30_port
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* initialize_85c30_port
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*
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*
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* initialize a z85c30 Port
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* initialize a z85c30 Port
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*/
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*/
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void initialize_85c30_port(
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void initialize_85c30_port(
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const Port_85C30_info *Port
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const Port_85C30_info *Port
|
)
|
)
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{
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{
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rtems_unsigned16 value;
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rtems_unsigned16 value;
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volatile unsigned char *ctrl;
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volatile unsigned char *ctrl;
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Console_Protocol *Setup;
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Console_Protocol *Setup;
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rtems_unsigned16 baud_constant;
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rtems_unsigned16 baud_constant;
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|
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Setup = Port->Protocol;
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Setup = Port->Protocol;
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ctrl = Port->ctrl;
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ctrl = Port->ctrl;
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|
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baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency,
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baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency,
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Port->Chip->clock_x, Setup->baud_rate );
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Port->Chip->clock_x, Setup->baud_rate );
|
|
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/*
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/*
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* Using register 4
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* Using register 4
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* Set up the clock rate.
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* Set up the clock rate.
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*/
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*/
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value = Clock_speed_85c30[ Port->Chip->clock_speed ] |
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value = Clock_speed_85c30[ Port->Chip->clock_speed ] |
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Stop_bit_85c30[ Setup->stop_bits ] |
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Stop_bit_85c30[ Setup->stop_bits ] |
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Parity_85c30[ Setup->parity ];
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Parity_85c30[ Setup->parity ];
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Write_85c30_register( ctrl, 0x04, value );
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Write_85c30_register( ctrl, 0x04, value );
|
|
|
/*
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/*
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* Set Write Register 1 to disable all interrupts
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* Set Write Register 1 to disable all interrupts
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*/
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*/
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Write_85c30_register( ctrl, 1, 0 );
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Write_85c30_register( ctrl, 1, 0 );
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|
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#if CONSOLE_USE_INTERRUPTS
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#if CONSOLE_USE_INTERRUPTS
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/*
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/*
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* Set Write Register 2 to contain the interrupt vector
|
* Set Write Register 2 to contain the interrupt vector
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*/
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*/
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Write_85c30_register( ctrl, 2, Port->Chip->vector );
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Write_85c30_register( ctrl, 2, Port->Chip->vector );
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#endif
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#endif
|
|
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/*
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/*
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* Set Write Register 3 to disable the Receiver
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* Set Write Register 3 to disable the Receiver
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*/
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*/
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Write_85c30_register( ctrl, 0x03, 0x00 );
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Write_85c30_register( ctrl, 0x03, 0x00 );
|
|
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/*
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/*
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* Set Write Register 5 to disable the Transmitter
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* Set Write Register 5 to disable the Transmitter
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*/
|
*/
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Write_85c30_register( ctrl, 5, 0x00 );
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Write_85c30_register( ctrl, 5, 0x00 );
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|
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/* WR 6 -- unneeded in asynchronous mode */
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/* WR 6 -- unneeded in asynchronous mode */
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|
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/* WR 7 -- unneeded in asynchronous mode */
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/* WR 7 -- unneeded in asynchronous mode */
|
|
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/*
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/*
|
* Set Write Register 9 to disable all interrupt sources
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* Set Write Register 9 to disable all interrupt sources
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*/
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*/
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Write_85c30_register( ctrl, 9, 0x00 );
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Write_85c30_register( ctrl, 9, 0x00 );
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|
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/*
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/*
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* Set Write Register 10 for simple Asynchronous operation
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* Set Write Register 10 for simple Asynchronous operation
|
*/
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*/
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Write_85c30_register( ctrl, 0x0a, 0x00 );
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Write_85c30_register( ctrl, 0x0a, 0x00 );
|
|
|
/*
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/*
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* Setup the source of the receive and xmit
|
* Setup the source of the receive and xmit
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* clock as BRG output and the transmit clock
|
* clock as BRG output and the transmit clock
|
* as the output source for TRxC pin via register 11
|
* as the output source for TRxC pin via register 11
|
*/
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*/
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Write_85c30_register( ctrl, 0x0b, 0x56 );
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Write_85c30_register( ctrl, 0x0b, 0x56 );
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|
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value = baud_constant;
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value = baud_constant;
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|
|
/*
|
/*
|
* Setup the lower 8 bits time constants = 1E.
|
* Setup the lower 8 bits time constants = 1E.
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* If the time constans = 1E, then the desire
|
* If the time constans = 1E, then the desire
|
* baud rate will be equilvalent to 9600, via register 12.
|
* baud rate will be equilvalent to 9600, via register 12.
|
*/
|
*/
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Write_85c30_register( ctrl, 0x0c, value & 0xff );
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Write_85c30_register( ctrl, 0x0c, value & 0xff );
|
|
|
/*
|
/*
|
* using register 13
|
* using register 13
|
* Setup the upper 8 bits time constants = 0
|
* Setup the upper 8 bits time constants = 0
|
*/
|
*/
|
Write_85c30_register( ctrl, 0x0d, value>>8 );
|
Write_85c30_register( ctrl, 0x0d, value>>8 );
|
|
|
/*
|
/*
|
* Set the DTR/REQ pin goes low when transmit
|
* Set the DTR/REQ pin goes low when transmit
|
* buffer becomes empty and enable the baud
|
* buffer becomes empty and enable the baud
|
* rate generator enable with clock from the
|
* rate generator enable with clock from the
|
* SCC's PCLK input via register 14.
|
* SCC's PCLK input via register 14.
|
*/
|
*/
|
Write_85c30_register( ctrl, 0x0e, 0x07 );
|
Write_85c30_register( ctrl, 0x0e, 0x07 );
|
|
|
/*
|
/*
|
* Set Write Register 3 : Base Value is xx00_000x
|
* Set Write Register 3 : Base Value is xx00_000x
|
* D6 - D7 : Receive Character Length (configured)
|
* D6 - D7 : Receive Character Length (configured)
|
* D5 : Auto Enable (forced value)
|
* D5 : Auto Enable (forced value)
|
* D4 : Enter Hunt Phase (forced value)
|
* D4 : Enter Hunt Phase (forced value)
|
* D3 : Receive CRC Enable (forced value)
|
* D3 : Receive CRC Enable (forced value)
|
* D2 : Address Search Mode (0 if not SDLC) (forced value)
|
* D2 : Address Search Mode (0 if not SDLC) (forced value)
|
* D1 : Sync Character Load Inhibit (forced value)
|
* D1 : Sync Character Load Inhibit (forced value)
|
* D0 : Receiver Enable (configured)
|
* D0 : Receiver Enable (configured)
|
*/
|
*/
|
value = 0x01;
|
value = 0x01;
|
value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
|
value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
|
|
|
Write_85c30_register( ctrl, 0x03, value );
|
Write_85c30_register( ctrl, 0x03, value );
|
|
|
/*
|
/*
|
* Set Write Register 5 : Base Value is 0xx0_x000
|
* Set Write Register 5 : Base Value is 0xx0_x000
|
* D7 : Data Terminal Ready (DTR) (forced value)
|
* D7 : Data Terminal Ready (DTR) (forced value)
|
* D5 - D6 : Transmit Character Length (configured)
|
* D5 - D6 : Transmit Character Length (configured)
|
* D4 : Send Break (forced value)
|
* D4 : Send Break (forced value)
|
* D3 : Transmitter Enable (configured)
|
* D3 : Transmitter Enable (configured)
|
* D2 : CRC Select (forced value)
|
* D2 : CRC Select (forced value)
|
* D1 : Request to Send (forced value)
|
* D1 : Request to Send (forced value)
|
* D0 : Transmit CRC Enable (forced value)
|
* D0 : Transmit CRC Enable (forced value)
|
*/
|
*/
|
value = 0x8a;
|
value = 0x8a;
|
value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup;
|
value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup;
|
Write_85c30_register( ctrl, 0x05, value );
|
Write_85c30_register( ctrl, 0x05, value );
|
|
|
/*
|
/*
|
* Reset Tx UNDERRUN/EOM LATCH and ERROR
|
* Reset Tx UNDERRUN/EOM LATCH and ERROR
|
* via register 0
|
* via register 0
|
*/
|
*/
|
Write_85c30_register( ctrl, 0x00, 0xf0 );
|
Write_85c30_register( ctrl, 0x00, 0xf0 );
|
|
|
#if CONSOLE_USE_INTERRUPTS
|
#if CONSOLE_USE_INTERRUPTS
|
/*
|
/*
|
* Set Write Register 1 to interrupt on Rx characters or special condition.
|
* Set Write Register 1 to interrupt on Rx characters or special condition.
|
*/
|
*/
|
Write_85c30_register( ctrl, 1, 0x10 );
|
Write_85c30_register( ctrl, 1, 0x10 );
|
#endif
|
#endif
|
|
|
/*
|
/*
|
* Set Write Register 15 to disable extended functions.
|
* Set Write Register 15 to disable extended functions.
|
*/
|
*/
|
|
|
Write_85c30_register( ctrl, 15, 0x00 );
|
Write_85c30_register( ctrl, 15, 0x00 );
|
|
|
/*
|
/*
|
* Set the Command Register to Reset Ext/STATUS.
|
* Set the Command Register to Reset Ext/STATUS.
|
*/
|
*/
|
Write_85c30_register( ctrl, 0x00, 0x10 );
|
Write_85c30_register( ctrl, 0x00, 0x10 );
|
|
|
#if CONSOLE_USE_INTERRUPTS
|
#if CONSOLE_USE_INTERRUPTS
|
|
|
/*
|
/*
|
* Set Write Register 1 : Base Value is 0001_0110
|
* Set Write Register 1 : Base Value is 0001_0110
|
* Enables Rx interrupt on all characters and special conditions.
|
* Enables Rx interrupt on all characters and special conditions.
|
* Enables parity as a special condition.
|
* Enables parity as a special condition.
|
* Enables Tx interrupt.
|
* Enables Tx interrupt.
|
*/
|
*/
|
Write_85c30_register( ctrl, 1, 0x16 );
|
Write_85c30_register( ctrl, 1, 0x16 );
|
|
|
/*
|
/*
|
* Set Write Register 9 to enable all interrupt sources
|
* Set Write Register 9 to enable all interrupt sources
|
* Changed from 0 to a
|
* Changed from 0 to a
|
*/
|
*/
|
Write_85c30_register( ctrl, 9, 0x0A );
|
Write_85c30_register( ctrl, 9, 0x0A );
|
|
|
|
|
/* XXX */
|
/* XXX */
|
|
|
/*
|
/*
|
* Issue reset highest Interrupt Under Service (IUS) command.
|
* Issue reset highest Interrupt Under Service (IUS) command.
|
*/
|
*/
|
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
|
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
|
|
|
#endif
|
#endif
|
|
|
}
|
}
|
|
|
/* PAGE
|
/* PAGE
|
*
|
*
|
* outbyte_polled_85c30
|
* outbyte_polled_85c30
|
*
|
*
|
* This routine transmits a character using polling.
|
* This routine transmits a character using polling.
|
*/
|
*/
|
|
|
void outbyte_polled_85c30(
|
void outbyte_polled_85c30(
|
volatile unsigned char *csr, /* IN */
|
volatile unsigned char *csr, /* IN */
|
char ch /* IN */
|
char ch /* IN */
|
)
|
)
|
{
|
{
|
unsigned char z8530_status;
|
unsigned char z8530_status;
|
rtems_unsigned32 isrlevel;
|
rtems_unsigned32 isrlevel;
|
|
|
rtems_interrupt_disable( isrlevel );
|
rtems_interrupt_disable( isrlevel );
|
|
|
/*
|
/*
|
* Wait for the Transmit buffer to indicate that it is empty.
|
* Wait for the Transmit buffer to indicate that it is empty.
|
*/
|
*/
|
do {
|
do {
|
z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
|
z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
|
} while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) );
|
} while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) );
|
|
|
/*
|
/*
|
* Write the character.
|
* Write the character.
|
*/
|
*/
|
Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch );
|
Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch );
|
|
|
rtems_interrupt_enable( isrlevel );
|
rtems_interrupt_enable( isrlevel );
|
}
|
}
|
|
|
/* PAGE
|
/* PAGE
|
*
|
*
|
* inbyte_nonblocking_85c30
|
* inbyte_nonblocking_85c30
|
*
|
*
|
* This routine polls for a character.
|
* This routine polls for a character.
|
*/
|
*/
|
|
|
int inbyte_nonblocking_85c30(
|
int inbyte_nonblocking_85c30(
|
const Port_85C30_info *Port
|
const Port_85C30_info *Port
|
)
|
)
|
{
|
{
|
volatile unsigned char *csr;
|
volatile unsigned char *csr;
|
unsigned char z8530_status;
|
unsigned char z8530_status;
|
rtems_unsigned8 data;
|
rtems_unsigned8 data;
|
|
|
csr = Port->ctrl;
|
csr = Port->ctrl;
|
|
|
/*
|
/*
|
* return -1 if a character is not available.
|
* return -1 if a character is not available.
|
*/
|
*/
|
z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
|
z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
|
if ( !Z8530_Status_Is_RX_character_available( z8530_status ) )
|
if ( !Z8530_Status_Is_RX_character_available( z8530_status ) )
|
return -1;
|
return -1;
|
|
|
/*
|
/*
|
* Return the character read.
|
* Return the character read.
|
*/
|
*/
|
data = Read_85c30_register( csr, DATA_REGISTER );
|
data = Read_85c30_register( csr, DATA_REGISTER );
|
data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
|
data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
|
|
|
return data;
|
return data;
|
}
|
}
|
|
|
|
|
/*
|
/*
|
* Interrupt driven console IO
|
* Interrupt driven console IO
|
*/
|
*/
|
|
|
#if CONSOLE_USE_INTERRUPTS
|
#if CONSOLE_USE_INTERRUPTS
|
|
|
/*PAGE
|
/*PAGE
|
*
|
*
|
* Z8530_Async_Channel_ISR
|
* Z8530_Async_Channel_ISR
|
*
|
*
|
*/
|
*/
|
/* RR0 */
|
/* RR0 */
|
|
|
rtems_isr ISR_85c30_Async(
|
rtems_isr ISR_85c30_Async(
|
const Port_85C30_info *Port
|
const Port_85C30_info *Port
|
)
|
)
|
{
|
{
|
rtems_unsigned16 status;
|
rtems_unsigned16 status;
|
volatile Console_Protocol *Protocol;
|
volatile Console_Protocol *Protocol;
|
unsigned char data;
|
unsigned char data;
|
rtems_boolean did_something = FALSE;
|
rtems_boolean did_something = FALSE;
|
|
|
Protocol = Port->Protocol;
|
Protocol = Port->Protocol;
|
|
|
status = Read_85c30_register( Port->ctrl, 0x00 );
|
status = Read_85c30_register( Port->ctrl, 0x00 );
|
|
|
/*
|
/*
|
* Was this a RX interrupt? If so, then process it.
|
* Was this a RX interrupt? If so, then process it.
|
*/
|
*/
|
|
|
if ( Z8530_Status_Is_RX_character_available( status ) ) {
|
if ( Z8530_Status_Is_RX_character_available( status ) ) {
|
data = Read_85c30_register( Port->ctrl, DATA_REGISTER );
|
data = Read_85c30_register( Port->ctrl, DATA_REGISTER );
|
data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
|
data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
|
|
|
rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data,
|
rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data,
|
&data, 1 );
|
&data, 1 );
|
did_something = TRUE;
|
did_something = TRUE;
|
}
|
}
|
|
|
/*
|
/*
|
* Was this a TX empty interrupt? If so, then process it.
|
* Was this a TX empty interrupt? If so, then process it.
|
*/
|
*/
|
|
|
if (Z8530_Status_Is_TX_buffer_empty( status ) ) {
|
if (Z8530_Status_Is_TX_buffer_empty( status ) ) {
|
if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) {
|
if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) {
|
Ring_buffer_Remove_character( &Protocol->TX_Buffer, data );
|
Ring_buffer_Remove_character( &Protocol->TX_Buffer, data );
|
Write_85c30_register( Port->ctrl, DATA_REGISTER, data );
|
Write_85c30_register( Port->ctrl, DATA_REGISTER, data );
|
|
|
} else {
|
} else {
|
Protocol->Is_TX_active = FALSE;
|
Protocol->Is_TX_active = FALSE;
|
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 );
|
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 );
|
}
|
}
|
|
|
did_something = TRUE;
|
did_something = TRUE;
|
}
|
}
|
|
|
/*
|
/*
|
* Issue reset highest Interrupt Under Service (IUS) command.
|
* Issue reset highest Interrupt Under Service (IUS) command.
|
*/
|
*/
|
|
|
/*
|
/*
|
if ( did_something )
|
if ( did_something )
|
*/
|
*/
|
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
|
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
|
}
|
}
|
|
|
#endif
|
#endif
|
|
|
|
|