/* 82378zb.c
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/* 82378zb.c
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*
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*
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* COPYRIGHT (c) 1989-1997.
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* COPYRIGHT (c) 1989-1997.
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* On-Line Applications Research Corporation (OAR).
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* On-Line Applications Research Corporation (OAR).
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* Copyright assigned to U.S. Government, 1994.
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* Copyright assigned to U.S. Government, 1994.
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*
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*
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* The license and distribution terms for this file may in
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* The license and distribution terms for this file may in
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* the file LICENSE in this distribution or at
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* the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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* http://www.OARcorp.com/rtems/license.html.
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*
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*
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* $Id:
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* $Id:
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*/
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*/
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#include <bsp.h>
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#include <bsp.h>
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#if (SCORE603E_GENERATION == 1)
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#if (SCORE603E_GENERATION == 1)
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#include <rtems/libio.h>
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#include <rtems/libio.h>
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#include <libcsupport.h>
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#include <libcsupport.h>
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#include <string.h>
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#include <string.h>
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#include <fcntl.h>
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#include <fcntl.h>
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#include <assert.h>
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#include <assert.h>
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/*
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/*
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* initialize 82378zb
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* initialize 82378zb
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*/
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*/
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void initialize_PCI_bridge ()
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void initialize_PCI_bridge ()
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{
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{
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/*
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/*
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* INT CNTRL-1 ICW1
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* INT CNTRL-1 ICW1
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* LTIM and ICW4
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* LTIM and ICW4
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*/
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*/
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Write_82378ZB( 0x20, 0x19);
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Write_82378ZB( 0x20, 0x19);
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/*
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/*
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* INT CNTRL-1 ICW 2
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* INT CNTRL-1 ICW 2
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* Sets 5 msbs of the base address in the interrupt vector table
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* Sets 5 msbs of the base address in the interrupt vector table
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* for the vector routines to 0100 0 ??
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* for the vector routines to 0100 0 ??
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*/
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*/
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Write_82378ZB( 0x21, 0x40 );
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Write_82378ZB( 0x21, 0x40 );
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/*
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/*
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* INT CNTRL-1 ICW 3
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* INT CNTRL-1 ICW 3
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* Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1
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* Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1
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*/
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*/
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Write_82378ZB( 0x21, 0x04 );
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Write_82378ZB( 0x21, 0x04 );
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/*
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/*
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* INT CNTRL-1 ICW 4
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* INT CNTRL-1 ICW 4
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* Set Microprocessor mode for 80x86 system.
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* Set Microprocessor mode for 80x86 system.
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*/
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*/
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Write_82378ZB( 0x21, 0x01 );
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Write_82378ZB( 0x21, 0x01 );
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/*
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/*
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* INT CNTRL-1 OCW 2
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* INT CNTRL-1 OCW 2
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* Set Non-specific EOI command
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* Set Non-specific EOI command
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*/
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*/
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Write_82378ZB( 0x20, 0x20 );
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Write_82378ZB( 0x20, 0x20 );
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/*
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/*
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* INT CNTRL-1 OCW 3
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* INT CNTRL-1 OCW 3
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* Interrupt controller in normal mask mode.
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* Interrupt controller in normal mask mode.
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* Disable Poll mode command
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* Disable Poll mode command
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* Read IRQ register.
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* Read IRQ register.
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*/
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*/
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Write_82378ZB( 0x20, 0x2a );
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Write_82378ZB( 0x20, 0x2a );
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/*
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/*
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* INT CNTRL-1 OCW 1
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* INT CNTRL-1 OCW 1
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* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
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* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
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* a masked IRQ will not set the interrupt request register (IRR) bit for
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* a masked IRQ will not set the interrupt request register (IRR) bit for
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* that channel.
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* that channel.
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*
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*
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* XXXX - Was 0xfd Only allowing Timer interrupt through changed to
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* XXXX - Was 0xfd Only allowing Timer interrupt through changed to
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* 0xe1.
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* 0xe1.
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*/
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*/
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Write_82378ZB( 0x21, 0xe1 );
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Write_82378ZB( 0x21, 0xe1 );
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/*
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/*
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* INT CNTRL-2 ICW 1
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* INT CNTRL-2 ICW 1
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* LTIM and ICW4
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* LTIM and ICW4
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*/
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*/
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Write_82378ZB( 0xa0, 0x19 );
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Write_82378ZB( 0xa0, 0x19 );
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/*
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/*
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* INT CNTRL-2 ICW 2
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* INT CNTRL-2 ICW 2
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* Sets 5 msbs of the base address in the interrupt vector table
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* Sets 5 msbs of the base address in the interrupt vector table
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* for the vector routines to 0100 1 ??
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* for the vector routines to 0100 1 ??
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*/
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*/
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Write_82378ZB( 0xa1, 0x48 );
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Write_82378ZB( 0xa1, 0x48 );
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/*
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/*
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* INT CNTRL-1 ICW 3
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* INT CNTRL-1 ICW 3
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* Slave Identification Code (Must be intialized to 2).
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* Slave Identification Code (Must be intialized to 2).
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*/
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*/
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Write_82378ZB( 0xa1, 0x02 );
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Write_82378ZB( 0xa1, 0x02 );
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/*
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/*
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* INT CNTRL-1 ICW 4
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* INT CNTRL-1 ICW 4
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* Set Microprocessor mode for 80x86 system.
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* Set Microprocessor mode for 80x86 system.
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*/
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*/
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Write_82378ZB( 0xa1, 0x01 );
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Write_82378ZB( 0xa1, 0x01 );
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/*
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/*
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* INT CNTRL-1 OCW 2
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* INT CNTRL-1 OCW 2
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* Set Non-specific EOI command
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* Set Non-specific EOI command
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*/
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*/
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Write_82378ZB( 0xa0, 0x20 );
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Write_82378ZB( 0xa0, 0x20 );
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/*
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/*
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* INT CNTRL-1 OCW 3
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* INT CNTRL-1 OCW 3
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* Interrupt controller in normal mask mode.
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* Interrupt controller in normal mask mode.
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* Disable Poll mode command
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* Disable Poll mode command
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* Read IRQ register.
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* Read IRQ register.
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*/
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*/
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Write_82378ZB( 0xa0, 0x2a );
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Write_82378ZB( 0xa0, 0x2a );
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/*
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/*
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* INT CNTRL-1 OCW 1
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* INT CNTRL-1 OCW 1
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* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
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* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
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* a masked IRQ will not set the interrupt request register (IRR) bit for
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* a masked IRQ will not set the interrupt request register (IRR) bit for
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* that channel.
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* that channel.
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*
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*
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* XXXX - All interrupts masked.
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* XXXX - All interrupts masked.
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*/
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*/
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Write_82378ZB( 0xa1, 0xff );
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Write_82378ZB( 0xa1, 0xff );
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}
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}
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rtems_unsigned16 read_and_clear_irq ()
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rtems_unsigned16 read_and_clear_irq ()
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{
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{
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rtems_unsigned16 irq;
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rtems_unsigned16 irq;
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/*
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/*
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* XXX - Fix this for all interrupts later
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* XXX - Fix this for all interrupts later
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*/
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*/
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Write_82378ZB( 0x20, 0x0c);
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Write_82378ZB( 0x20, 0x0c);
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Read_82378ZB( 0x20, irq );
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Read_82378ZB( 0x20, irq );
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irq &= 0x7;
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irq &= 0x7;
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Write_82378ZB( 0x20, 0x20 );
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Write_82378ZB( 0x20, 0x20 );
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return irq;
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return irq;
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}
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}
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void init_irq_data_register()
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void init_irq_data_register()
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{
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{
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assert (0);
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assert (0);
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}
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}
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rtems_unsigned16 get_irq_mask()
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rtems_unsigned16 get_irq_mask()
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{
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{
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assert (0);
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assert (0);
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return 0;
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return 0;
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}
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}
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void set_irq_mask(
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void set_irq_mask(
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rtems_unsigned16 value
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rtems_unsigned16 value
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)
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)
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{
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{
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assert (0);
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assert (0);
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}
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}
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#endif /* end of generation 1 */
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#endif /* end of generation 1 */
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