/*
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/*
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* pci.c : this file contains basic PCI Io functions.
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* pci.c : this file contains basic PCI Io functions.
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*
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*
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* CopyRight (C) 1999 valette@crf.canon.fr
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* CopyRight (C) 1999 valette@crf.canon.fr
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*
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*
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* This code is heavilly inspired by the public specification of STREAM V2
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* This code is heavilly inspired by the public specification of STREAM V2
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* that can be found at :
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* that can be found at :
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*
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*
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* <http://www.chorus.com/Documentation/index.html> by following
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* <http://www.chorus.com/Documentation/index.html> by following
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* the STREAM API Specification Document link.
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* the STREAM API Specification Document link.
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*
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*
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* The license and distribution terms for this file may be
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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* http://www.OARcorp.com/rtems/license.html.
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*
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*
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* $Id: pci.c,v 1.2 2001-09-27 12:01:07 chris Exp $
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* $Id: pci.c,v 1.2 2001-09-27 12:01:07 chris Exp $
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*/
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*/
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|
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#include <bsp/consoleIo.h>
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#include <bsp/consoleIo.h>
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#include <libcpu/io.h>
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#include <libcpu/io.h>
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#include <bsp/pci.h>
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#include <bsp/pci.h>
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#include <bsp/residual.h>
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#include <bsp/residual.h>
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#include <bsp/openpic.h>
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#include <bsp/openpic.h>
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#include <bsp.h>
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#include <bsp.h>
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|
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#define PCI_CONFIG_ADDR 0xcf8
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#define PCI_CONFIG_ADDR 0xcf8
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#define PCI_CONFIG_DATA 0xcfc
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#define PCI_CONFIG_DATA 0xcfc
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#define PCI_INVALID_VENDORDEVICEID 0xffffffff
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#define PCI_INVALID_VENDORDEVICEID 0xffffffff
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#define PCI_MULTI_FUNCTION 0x80
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#define PCI_MULTI_FUNCTION 0x80
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#define RAVEN_MPIC_IOSPACE_ENABLE 0x1
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#define RAVEN_MPIC_IOSPACE_ENABLE 0x1
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#define RAVEN_MPIC_MEMSPACE_ENABLE 0x2
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#define RAVEN_MPIC_MEMSPACE_ENABLE 0x2
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#define RAVEN_MASTER_ENABLE 0x4
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#define RAVEN_MASTER_ENABLE 0x4
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#define RAVEN_PARITY_CHECK_ENABLE 0x40
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#define RAVEN_PARITY_CHECK_ENABLE 0x40
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#define RAVEN_SYSTEM_ERROR_ENABLE 0x100
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#define RAVEN_SYSTEM_ERROR_ENABLE 0x100
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#define RAVEN_CLEAR_EVENTS_MASK 0xf9000000
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#define RAVEN_CLEAR_EVENTS_MASK 0xf9000000
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|
|
|
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/*
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/*
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* Bit encode for PCI_CONFIG_HEADER_TYPE register
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* Bit encode for PCI_CONFIG_HEADER_TYPE register
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*/
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*/
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unsigned char ucMaxPCIBus;
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unsigned char ucMaxPCIBus;
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|
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static int
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static int
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indirect_pci_read_config_byte(unsigned char bus, unsigned char slot,
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indirect_pci_read_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned char *val) {
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unsigned char offset, unsigned char *val) {
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out_be32((unsigned int*) pci.pci_config_addr,
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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*val = in_8(pci.pci_config_data + (offset&3));
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*val = in_8(pci.pci_config_data + (offset&3));
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int
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static int
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indirect_pci_read_config_word(unsigned char bus, unsigned char slot,
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indirect_pci_read_config_word(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned short *val) {
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unsigned char offset, unsigned short *val) {
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*val = 0xffff;
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*val = 0xffff;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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*val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)));
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*val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)));
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int
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static int
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indirect_pci_read_config_dword(unsigned char bus, unsigned char slot,
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indirect_pci_read_config_dword(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned int *val) {
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unsigned char offset, unsigned int *val) {
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*val = 0xffffffff;
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*val = 0xffffffff;
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
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*val = in_le32((volatile unsigned int *)pci.pci_config_data);
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*val = in_le32((volatile unsigned int *)pci.pci_config_data);
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int
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static int
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indirect_pci_write_config_byte(unsigned char bus, unsigned char slot,
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indirect_pci_write_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned char val) {
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unsigned char offset, unsigned char val) {
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out_be32((unsigned int*) pci.pci_config_addr,
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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out_8(pci.pci_config_data + (offset&3), val);
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out_8(pci.pci_config_data + (offset&3), val);
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int
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static int
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indirect_pci_write_config_word(unsigned char bus, unsigned char slot,
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indirect_pci_write_config_word(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned short val) {
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unsigned char offset, unsigned short val) {
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24));
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out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val);
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out_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3)), val);
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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static int
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static int
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indirect_pci_write_config_dword(unsigned char bus, unsigned char slot,
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indirect_pci_write_config_dword(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned int val) {
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unsigned char offset, unsigned int val) {
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
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out_be32((unsigned int*) pci.pci_config_addr,
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out_be32((unsigned int*) pci.pci_config_addr,
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
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0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|(offset<<24));
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out_le32((volatile unsigned int *)pci.pci_config_data, val);
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out_le32((volatile unsigned int *)pci.pci_config_data, val);
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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|
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static const pci_config_access_functions indirect_functions = {
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static const pci_config_access_functions indirect_functions = {
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indirect_pci_read_config_byte,
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indirect_pci_read_config_byte,
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indirect_pci_read_config_word,
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indirect_pci_read_config_word,
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indirect_pci_read_config_dword,
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indirect_pci_read_config_dword,
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indirect_pci_write_config_byte,
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indirect_pci_write_config_byte,
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indirect_pci_write_config_word,
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indirect_pci_write_config_word,
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indirect_pci_write_config_dword
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indirect_pci_write_config_dword
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};
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};
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pci_config pci = {(volatile unsigned char*)PCI_CONFIG_ADDR,
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pci_config pci = {(volatile unsigned char*)PCI_CONFIG_ADDR,
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(volatile unsigned char*)PCI_CONFIG_DATA,
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(volatile unsigned char*)PCI_CONFIG_DATA,
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&indirect_functions};
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&indirect_functions};
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|
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static int
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static int
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direct_pci_read_config_byte(unsigned char bus, unsigned char slot,
|
direct_pci_read_config_byte(unsigned char bus, unsigned char slot,
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unsigned char function,
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unsigned char function,
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unsigned char offset, unsigned char *val) {
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unsigned char offset, unsigned char *val) {
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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*val=0xff;
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*val=0xff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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*val=in_8(pci.pci_config_data + ((1<<slot)&~1)
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*val=in_8(pci.pci_config_data + ((1<<slot)&~1)
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+ (function<<8) + offset);
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+ (function<<8) + offset);
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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|
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static int
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static int
|
direct_pci_read_config_word(unsigned char bus, unsigned char slot,
|
direct_pci_read_config_word(unsigned char bus, unsigned char slot,
|
unsigned char function,
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unsigned char function,
|
unsigned char offset, unsigned short *val) {
|
unsigned char offset, unsigned short *val) {
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*val = 0xffff;
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*val = 0xffff;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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if (bus != 0 || (1<<slot & 0xff8007fe)) {
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
|
*val=in_le16((volatile unsigned short *)
|
*val=in_le16((volatile unsigned short *)
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(pci.pci_config_data + ((1<<slot)&~1)
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(pci.pci_config_data + ((1<<slot)&~1)
|
+ (function<<8) + offset));
|
+ (function<<8) + offset));
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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|
|
static int
|
static int
|
direct_pci_read_config_dword(unsigned char bus, unsigned char slot,
|
direct_pci_read_config_dword(unsigned char bus, unsigned char slot,
|
unsigned char function,
|
unsigned char function,
|
unsigned char offset, unsigned int *val) {
|
unsigned char offset, unsigned int *val) {
|
*val = 0xffffffff;
|
*val = 0xffffffff;
|
if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
|
if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
}
|
}
|
*val=in_le32((volatile unsigned int *)
|
*val=in_le32((volatile unsigned int *)
|
(pci.pci_config_data + ((1<<slot)&~1)
|
(pci.pci_config_data + ((1<<slot)&~1)
|
+ (function<<8) + offset));
|
+ (function<<8) + offset));
|
return PCIBIOS_SUCCESSFUL;
|
return PCIBIOS_SUCCESSFUL;
|
}
|
}
|
|
|
static int
|
static int
|
direct_pci_write_config_byte(unsigned char bus, unsigned char slot,
|
direct_pci_write_config_byte(unsigned char bus, unsigned char slot,
|
unsigned char function,
|
unsigned char function,
|
unsigned char offset, unsigned char val) {
|
unsigned char offset, unsigned char val) {
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
}
|
}
|
out_8(pci.pci_config_data + ((1<<slot)&~1)
|
out_8(pci.pci_config_data + ((1<<slot)&~1)
|
+ (function<<8) + offset,
|
+ (function<<8) + offset,
|
val);
|
val);
|
return PCIBIOS_SUCCESSFUL;
|
return PCIBIOS_SUCCESSFUL;
|
}
|
}
|
|
|
static int
|
static int
|
direct_pci_write_config_word(unsigned char bus, unsigned char slot,
|
direct_pci_write_config_word(unsigned char bus, unsigned char slot,
|
unsigned char function,
|
unsigned char function,
|
unsigned char offset, unsigned short val) {
|
unsigned char offset, unsigned short val) {
|
if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
|
if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
}
|
}
|
out_le16((volatile unsigned short *)
|
out_le16((volatile unsigned short *)
|
(pci.pci_config_data + ((1<<slot)&~1)
|
(pci.pci_config_data + ((1<<slot)&~1)
|
+ (function<<8) + offset),
|
+ (function<<8) + offset),
|
val);
|
val);
|
return PCIBIOS_SUCCESSFUL;
|
return PCIBIOS_SUCCESSFUL;
|
}
|
}
|
|
|
static int
|
static int
|
direct_pci_write_config_dword(unsigned char bus, unsigned char slot,
|
direct_pci_write_config_dword(unsigned char bus, unsigned char slot,
|
unsigned char function,
|
unsigned char function,
|
unsigned char offset, unsigned int val) {
|
unsigned char offset, unsigned int val) {
|
if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
|
if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
if (bus != 0 || (1<<slot & 0xff8007fe)) {
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
}
|
}
|
out_le32((volatile unsigned int *)
|
out_le32((volatile unsigned int *)
|
(pci.pci_config_data + ((1<<slot)&~1)
|
(pci.pci_config_data + ((1<<slot)&~1)
|
+ (function<<8) + offset),
|
+ (function<<8) + offset),
|
val);
|
val);
|
return PCIBIOS_SUCCESSFUL;
|
return PCIBIOS_SUCCESSFUL;
|
}
|
}
|
|
|
static const pci_config_access_functions direct_functions = {
|
static const pci_config_access_functions direct_functions = {
|
direct_pci_read_config_byte,
|
direct_pci_read_config_byte,
|
direct_pci_read_config_word,
|
direct_pci_read_config_word,
|
direct_pci_read_config_dword,
|
direct_pci_read_config_dword,
|
direct_pci_write_config_byte,
|
direct_pci_write_config_byte,
|
direct_pci_write_config_word,
|
direct_pci_write_config_word,
|
direct_pci_write_config_dword
|
direct_pci_write_config_dword
|
};
|
};
|
|
|
|
|
void detect_host_bridge()
|
void detect_host_bridge()
|
{
|
{
|
PPC_DEVICE *hostbridge;
|
PPC_DEVICE *hostbridge;
|
unsigned int id0;
|
unsigned int id0;
|
unsigned int tmp;
|
unsigned int tmp;
|
|
|
/*
|
/*
|
* This code assumes that the host bridge is located at
|
* This code assumes that the host bridge is located at
|
* bus 0, dev 0, func 0 AND that the old pre PCI 2.1
|
* bus 0, dev 0, func 0 AND that the old pre PCI 2.1
|
* standart devices detection mecahnism that was used on PC
|
* standart devices detection mecahnism that was used on PC
|
* (still used in BSD source code) works.
|
* (still used in BSD source code) works.
|
*/
|
*/
|
hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
|
hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
|
BridgeController,
|
BridgeController,
|
PCIBridge, -1, 0);
|
PCIBridge, -1, 0);
|
if (hostbridge) {
|
if (hostbridge) {
|
if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
|
if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
|
pci.pci_functions=&indirect_functions;
|
pci.pci_functions=&indirect_functions;
|
/* Should be extracted from residual data,
|
/* Should be extracted from residual data,
|
* indeed MPC106 in CHRP mode is different,
|
* indeed MPC106 in CHRP mode is different,
|
* but we should not use residual data in
|
* but we should not use residual data in
|
* this case anyway.
|
* this case anyway.
|
*/
|
*/
|
pci.pci_config_addr = ((volatile unsigned char *)
|
pci.pci_config_addr = ((volatile unsigned char *)
|
(ptr_mem_map->io_base+0xcf8));
|
(ptr_mem_map->io_base+0xcf8));
|
pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
|
pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
|
} else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
|
} else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
|
pci.pci_functions=&direct_functions;
|
pci.pci_functions=&direct_functions;
|
pci.pci_config_data=(unsigned char *) 0x80800000;
|
pci.pci_config_data=(unsigned char *) 0x80800000;
|
} else {
|
} else {
|
}
|
}
|
} else {
|
} else {
|
/* Let us try by experimentation at our own risk! */
|
/* Let us try by experimentation at our own risk! */
|
pci.pci_functions = &direct_functions;
|
pci.pci_functions = &direct_functions;
|
/* On all direct bridges I know the host bridge itself
|
/* On all direct bridges I know the host bridge itself
|
* appears as device 0 function 0.
|
* appears as device 0 function 0.
|
*/
|
*/
|
pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
|
pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
|
if (id0==~0U) {
|
if (id0==~0U) {
|
pci.pci_functions = &indirect_functions;
|
pci.pci_functions = &indirect_functions;
|
pci.pci_config_addr = ((volatile unsigned char*)
|
pci.pci_config_addr = ((volatile unsigned char*)
|
(ptr_mem_map->io_base+0xcf8));
|
(ptr_mem_map->io_base+0xcf8));
|
pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
|
pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
|
}
|
}
|
/* Here we should check that the host bridge is actually
|
/* Here we should check that the host bridge is actually
|
* present, but if it not, we are in such a desperate
|
* present, but if it not, we are in such a desperate
|
* situation, that we probably can't even tell it.
|
* situation, that we probably can't even tell it.
|
*/
|
*/
|
}
|
}
|
pci_read_config_dword(0, 0, 0, 0, &id0);
|
pci_read_config_dword(0, 0, 0, 0, &id0);
|
if(id0 == PCI_VENDOR_ID_MOTOROLA +
|
if(id0 == PCI_VENDOR_ID_MOTOROLA +
|
(PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
|
(PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
|
/*
|
/*
|
* We have a Raven bridge. We will get information about its settings
|
* We have a Raven bridge. We will get information about its settings
|
*/
|
*/
|
pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
|
pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
|
#ifdef SHOW_RAVEN_SETTING
|
#ifdef SHOW_RAVEN_SETTING
|
printk("RAVEN PCI command register = %x\n",id0);
|
printk("RAVEN PCI command register = %x\n",id0);
|
#endif
|
#endif
|
id0 |= RAVEN_CLEAR_EVENTS_MASK;
|
id0 |= RAVEN_CLEAR_EVENTS_MASK;
|
pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
|
pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
|
pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
|
pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
|
#ifdef SHOW_RAVEN_SETTING
|
#ifdef SHOW_RAVEN_SETTING
|
printk("After error clearing RAVEN PCI command register = %x\n",id0);
|
printk("After error clearing RAVEN PCI command register = %x\n",id0);
|
#endif
|
#endif
|
|
|
if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
|
if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
|
pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
|
pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
|
#ifdef SHOW_RAVEN_SETTING
|
#ifdef SHOW_RAVEN_SETTING
|
printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
|
printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
|
#endif
|
#endif
|
}
|
}
|
if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
|
if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
|
pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
|
pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
|
#ifdef SHOW_RAVEN_SETTING
|
#ifdef SHOW_RAVEN_SETTING
|
printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
|
printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
|
#endif
|
#endif
|
OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
|
OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
|
printk("OpenPIC found at %p.\n",
|
printk("OpenPIC found at %p.\n",
|
OpenPIC);
|
OpenPIC);
|
}
|
}
|
}
|
}
|
if (OpenPIC == (volatile struct OpenPIC *)0) {
|
if (OpenPIC == (volatile struct OpenPIC *)0) {
|
BSP_panic("OpenPic Not found\n");
|
BSP_panic("OpenPic Not found\n");
|
}
|
}
|
|
|
}
|
}
|
|
|
/*
|
/*
|
* This routine determines the maximum bus number in the system
|
* This routine determines the maximum bus number in the system
|
*/
|
*/
|
void InitializePCI()
|
void InitializePCI()
|
{
|
{
|
unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs;
|
unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs;
|
unsigned char ucHeader;
|
unsigned char ucHeader;
|
unsigned char ucMaxSubordinate;
|
unsigned char ucMaxSubordinate;
|
unsigned int ulClass, ulDeviceID;
|
unsigned int ulClass, ulDeviceID;
|
|
|
detect_host_bridge();
|
detect_host_bridge();
|
/*
|
/*
|
* Scan PCI bus 0 looking for PCI-PCI bridges
|
* Scan PCI bus 0 looking for PCI-PCI bridges
|
*/
|
*/
|
for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
|
for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) {
|
(void)pci_read_config_dword(0,
|
(void)pci_read_config_dword(0,
|
ucSlotNumber,
|
ucSlotNumber,
|
0,
|
0,
|
PCI_VENDOR_ID,
|
PCI_VENDOR_ID,
|
&ulDeviceID);
|
&ulDeviceID);
|
if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
|
if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
|
/*
|
/*
|
* This slot is empty
|
* This slot is empty
|
*/
|
*/
|
continue;
|
continue;
|
}
|
}
|
(void)pci_read_config_byte(0,
|
(void)pci_read_config_byte(0,
|
ucSlotNumber,
|
ucSlotNumber,
|
0,
|
0,
|
PCI_HEADER_TYPE,
|
PCI_HEADER_TYPE,
|
&ucHeader);
|
&ucHeader);
|
if(ucHeader&PCI_MULTI_FUNCTION) {
|
if(ucHeader&PCI_MULTI_FUNCTION) {
|
ucNumFuncs=PCI_MAX_FUNCTIONS;
|
ucNumFuncs=PCI_MAX_FUNCTIONS;
|
}
|
}
|
else {
|
else {
|
ucNumFuncs=1;
|
ucNumFuncs=1;
|
}
|
}
|
for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) {
|
for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) {
|
(void)pci_read_config_dword(0,
|
(void)pci_read_config_dword(0,
|
ucSlotNumber,
|
ucSlotNumber,
|
ucFnNumber,
|
ucFnNumber,
|
PCI_VENDOR_ID,
|
PCI_VENDOR_ID,
|
&ulDeviceID);
|
&ulDeviceID);
|
if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
|
if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) {
|
/*
|
/*
|
* This slot/function is empty
|
* This slot/function is empty
|
*/
|
*/
|
continue;
|
continue;
|
}
|
}
|
|
|
/*
|
/*
|
* This slot/function has a device fitted.
|
* This slot/function has a device fitted.
|
*/
|
*/
|
(void)pci_read_config_dword(0,
|
(void)pci_read_config_dword(0,
|
ucSlotNumber,
|
ucSlotNumber,
|
ucFnNumber,
|
ucFnNumber,
|
PCI_CLASS_REVISION,
|
PCI_CLASS_REVISION,
|
&ulClass);
|
&ulClass);
|
ulClass >>= 16;
|
ulClass >>= 16;
|
if (ulClass == PCI_CLASS_BRIDGE_PCI) {
|
if (ulClass == PCI_CLASS_BRIDGE_PCI) {
|
/*
|
/*
|
* We have found a PCI-PCI bridge
|
* We have found a PCI-PCI bridge
|
*/
|
*/
|
(void)pci_read_config_byte(0,
|
(void)pci_read_config_byte(0,
|
ucSlotNumber,
|
ucSlotNumber,
|
ucFnNumber,
|
ucFnNumber,
|
PCI_SUBORDINATE_BUS,
|
PCI_SUBORDINATE_BUS,
|
&ucMaxSubordinate);
|
&ucMaxSubordinate);
|
if(ucMaxSubordinate>ucMaxPCIBus) {
|
if(ucMaxSubordinate>ucMaxPCIBus) {
|
ucMaxPCIBus=ucMaxSubordinate;
|
ucMaxPCIBus=ucMaxSubordinate;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/*
|
/*
|
* Return the number of PCI busses in the system
|
* Return the number of PCI busses in the system
|
*/
|
*/
|
unsigned char BusCountPCI()
|
unsigned char BusCountPCI()
|
{
|
{
|
return(ucMaxPCIBus+1);
|
return(ucMaxPCIBus+1);
|
}
|
}
|
|
|
