/*
|
/*
|
----------------------------------------------------------------------
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----------------------------------------------------------------------
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CHiPES Embedded RTR Systems Copyright (c) Tim Oliver 2002-2004
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CHiPES Embedded RTR Systems Copyright (c) Tim Oliver 2002-2004
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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File : os_cpu_a.S
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File : os_cpu_a.S
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Author(s) : Tim Oliver, timtimoliver@yahoo.co.uk
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Author(s) : Tim Oliver, timtimoliver@yahoo.co.uk
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Julius Baxter, julius@opencores.org
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Julius Baxter, julius@opencores.org
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---------------------------[Description]------------------------------
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---------------------------[Description]------------------------------
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Start up file for OpenRISC Reference Platform
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Start up file for OpenRISC Reference Platform
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Assembly code required for ORP port of MicroC/OS-II
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Assembly code required for ORP port of MicroC/OS-II
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|
|
Macros :
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Macros :
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exception_vector name org
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exception_vector name org
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load32i reg const
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load32i reg const
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store_context
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store_context
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restore_context
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restore_context
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|
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Internal Routines :
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Internal Routines :
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_reset Boot code installed at interrupt vector 0x100
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_reset Boot code installed at interrupt vector 0x100
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_start Start up sequence
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_start Start up sequence
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_OSTickISR Operating system timer tick interrupt service routine
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_OSTickISR Operating system timer tick interrupt service
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_OSStartHighRdy Starts the highest priority task that is available to run
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routine
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_OSStartHighRdy Starts the highest priority task that is
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available to run
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_OSCtxSwBP
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_OSCtxSwBP
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_OSCtxSw Task switch
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_OSCtxSw Task switch
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_OSIntCtxSw Task switch after interrupt
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_OSIntCtxSw Task switch after interrupt
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_UserISR Interrupt service routine template - requires code
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_UserISR Interrupt service routine template - requires
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_align Attempts to recover from memory alignment errors
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code
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_align Attempts to recover from memory alignment
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errors
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nest_not_one
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nest_not_one
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External Routines :
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External Routines :
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_OSIntExit
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_OSIntExit
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_OSTimeTick
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_OSTimeTick
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_OSTaskSwHook
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_OSTaskSwHook
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External variables :
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External variables :
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_OSIntNesting
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_OSIntNesting
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_OSRunning
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_OSRunning
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_OSPrioHighRdy
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_OSPrioHighRdy
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_OSPrioCur
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_OSPrioCur
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_OSTCBCur
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_OSTCBCur
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_OSTCBHighRdy
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_OSTCBHighRdy
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Interrupt Vectors Installed:
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Interrupt Vectors Installed:
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0x100 _reset
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0x100 _reset
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0x500 _OSTickISR
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0x500 _OSTickISR
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0x600 _align
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0x600 _align
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0x800 _UserISR
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0x800 _UserISR
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0xc00 _OSCtxSw
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0xc00 _OSCtxSw
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*/
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*/
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|
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/*
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/*
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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|
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "board.h"
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#include "board.h"
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|
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#define RED_ZONE_SIZE 128
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#define RED_ZONE_SIZE 128
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#define STK_FRAME_SIZE (128+RED_ZONE_SIZE)
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#define STK_FRAME_SIZE (128+RED_ZONE_SIZE)
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#define SPR_TTMR_LOAD (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
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#define SPR_TTMR_LOAD (SPR_TTMR_IE | SPR_TTMR_RT | \
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((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
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/* function prototypes */
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/* function prototypes */
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.global OSTickISR /* internal functions */
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.global OSTickISR /* internal functions */
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.global OSStartHighRdy
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.global OSStartHighRdy
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.global OSCtxSwBP
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.global OSCtxSwBP
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.global OSCtxSw
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.global OSCtxSw
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.global OSIntCtxSw
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.global OSIntCtxSw
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.global UserISR
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.global UserISR
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.global _align
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.global _align
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.global nest_not_one
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.global nest_not_one
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.extern OSIntExit /* external functions */
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.extern OSIntExit /* external functions */
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.extern OSTimeTick
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.extern OSTimeTick
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.extern OSTaskSwHook
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.extern OSTaskSwHook
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.extern OSIntNesting /* values */
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.extern OSIntNesting /* values */
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.extern OSRunning
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.extern OSRunning
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.extern OSPrioHighRdy
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.extern OSPrioHighRdy
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.extern OSPrioCur
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.extern OSPrioCur
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.extern OSTCBCur
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.extern OSTCBCur
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.extern OSTCBHighRdy
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.extern OSTCBHighRdy
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/* Macro Definitions */
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/* Macro Definitions */
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/* Utility macro: Load a 32-bit constant into a register */
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/* Utility macro: Load a 32-bit constant into a register */
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.macro load32i reg const
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.macro load32i reg const
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l.movhi \reg,hi(\const)
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l.movhi \reg,hi(\const)
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l.ori \reg,\reg,lo(\const)
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l.ori \reg,\reg,lo(\const)
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.endm
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.endm
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/* Utility macro: Start code for an exception handler */
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/* Utility macro: Start code for an exception handler */
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.macro exception_vector name
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.macro exception_vector name
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l.addi r1,r1,-STK_FRAME_SIZE
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l.addi r1,r1,-STK_FRAME_SIZE
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l.sw 0xc(r1),r3
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l.sw 0xc(r1),r3
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l.movhi r3,hi(\name)
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l.movhi r3,hi(\name)
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l.ori r3,r3,lo(\name)
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l.ori r3,r3,lo(\name)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.endm
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.endm
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.macro unhandled_exception
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.macro unhandled_exception
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l.ori r3, r0, 1
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l.ori r3, r0, 1
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l.j 0
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l.j 0
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l.nop NOP_EXIT
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l.nop NOP_EXIT
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.endm
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.endm
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|
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/* Utility macro: store the cpu context on the stack */
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/* Utility macro: store the cpu context on the stack */
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.macro store_context
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.macro store_context
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l.sw 0x8(r1),r2
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l.sw 0x8(r1),r2
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l.sw 0x10(r1),r4
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l.sw 0x10(r1),r4
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l.sw 0x14(r1),r5
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l.sw 0x14(r1),r5
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l.sw 0x18(r1),r6
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l.sw 0x18(r1),r6
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l.sw 0x1c(r1),r7
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l.sw 0x1c(r1),r7
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l.sw 0x20(r1),r8
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l.sw 0x20(r1),r8
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l.sw 0x24(r1),r9
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l.sw 0x24(r1),r9
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l.sw 0x28(r1),r10
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l.sw 0x28(r1),r10
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l.sw 0x2c(r1),r11
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l.sw 0x2c(r1),r11
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l.sw 0x30(r1),r12
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l.sw 0x30(r1),r12
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l.sw 0x34(r1),r13
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l.sw 0x34(r1),r13
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l.sw 0x38(r1),r14
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l.sw 0x38(r1),r14
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l.sw 0x3c(r1),r15
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l.sw 0x3c(r1),r15
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l.sw 0x40(r1),r16
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l.sw 0x40(r1),r16
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l.sw 0x44(r1),r17
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l.sw 0x44(r1),r17
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l.sw 0x48(r1),r18
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l.sw 0x48(r1),r18
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l.sw 0x4c(r1),r19
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l.sw 0x4c(r1),r19
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l.sw 0x50(r1),r20
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l.sw 0x50(r1),r20
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l.sw 0x54(r1),r21
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l.sw 0x54(r1),r21
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l.sw 0x58(r1),r22
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l.sw 0x58(r1),r22
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l.sw 0x5c(r1),r23
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l.sw 0x5c(r1),r23
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l.sw 0x60(r1),r24
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l.sw 0x60(r1),r24
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l.sw 0x64(r1),r25
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l.sw 0x64(r1),r25
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l.sw 0x68(r1),r26
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l.sw 0x68(r1),r26
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l.sw 0x6c(r1),r27
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l.sw 0x6c(r1),r27
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l.sw 0x70(r1),r28
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l.sw 0x70(r1),r28
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l.sw 0x74(r1),r29
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l.sw 0x74(r1),r29
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l.sw 0x78(r1),r30
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l.sw 0x78(r1),r30
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l.sw 0x7c(r1),r31
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l.sw 0x7c(r1),r31
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.endm
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.endm
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|
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/* Utility macro: restore the cpu context from the stack */
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/* Utility macro: restore the cpu context from the stack */
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.macro restore_context
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.macro restore_context
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l.lwz r2,0x8(r1)
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l.lwz r2,0x8(r1)
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l.lwz r3,0xc(r1)
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l.lwz r3,0xc(r1)
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l.lwz r4,0x10(r1)
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l.lwz r4,0x10(r1)
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l.lwz r5,0x14(r1)
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l.lwz r5,0x14(r1)
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l.lwz r6,0x18(r1)
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l.lwz r6,0x18(r1)
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l.lwz r7,0x1c(r1)
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l.lwz r7,0x1c(r1)
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l.lwz r8,0x20(r1)
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l.lwz r8,0x20(r1)
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l.lwz r9,0x24(r1)
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l.lwz r9,0x24(r1)
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l.lwz r10,0x28(r1)
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l.lwz r10,0x28(r1)
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l.lwz r11,0x2c(r1)
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l.lwz r11,0x2c(r1)
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l.lwz r12,0x30(r1)
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l.lwz r12,0x30(r1)
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l.lwz r13,0x34(r1)
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l.lwz r13,0x34(r1)
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l.lwz r14,0x38(r1)
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l.lwz r14,0x38(r1)
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l.lwz r15,0x3c(r1)
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l.lwz r15,0x3c(r1)
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l.lwz r16,0x40(r1)
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l.lwz r16,0x40(r1)
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l.lwz r17,0x44(r1)
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l.lwz r17,0x44(r1)
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l.lwz r18,0x48(r1)
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l.lwz r18,0x48(r1)
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l.lwz r19,0x4c(r1)
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l.lwz r19,0x4c(r1)
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l.lwz r20,0x50(r1)
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l.lwz r20,0x50(r1)
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l.lwz r21,0x54(r1)
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l.lwz r21,0x54(r1)
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l.lwz r22,0x58(r1)
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l.lwz r22,0x58(r1)
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l.lwz r23,0x5c(r1)
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l.lwz r23,0x5c(r1)
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l.lwz r24,0x60(r1)
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l.lwz r24,0x60(r1)
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l.lwz r25,0x64(r1)
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l.lwz r25,0x64(r1)
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l.lwz r26,0x68(r1)
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l.lwz r26,0x68(r1)
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l.lwz r27,0x6c(r1)
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l.lwz r27,0x6c(r1)
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l.lwz r28,0x70(r1)
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l.lwz r28,0x70(r1)
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l.lwz r29,0x74(r1)
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l.lwz r29,0x74(r1)
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l.lwz r30,0x78(r1)
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l.lwz r30,0x78(r1)
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l.lwz r31,0x7c(r1)
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l.lwz r31,0x7c(r1)
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.endm
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.endm
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|
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/* actual code */
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/* actual code */
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.section .stack, "aw", @nobits
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.section .stack, "aw", @nobits
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.space STACK_SIZE
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.space STACK_SIZE
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_stack:
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_stack:
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/* Exception vectors */
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/* Exception vectors */
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|
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.section .vectors, "ax"
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.section .vectors, "ax"
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.org 0x100
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.org 0x100
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_reset:
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_reset:
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l.movhi r0,0
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l.movhi r0,0
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l.addi r3,r0,SPR_SR_SM
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l.addi r3,r0,SPR_SR_SM
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l.mtspr r0,r3,SPR_SR
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l.mtspr r0,r3,SPR_SR
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load32i r3,_start
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load32i r3,_start
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.org 0x200
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.org 0x200
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unhandled_exception
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unhandled_exception
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.org 0x300
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.org 0x300
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unhandled_exception
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unhandled_exception
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.org 0x400
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.org 0x400
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unhandled_exception
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unhandled_exception
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.org 0x500
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.org 0x500
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exception_vector OSTickISR
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exception_vector OSTickISR
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|
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.org 0x600
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.org 0x600
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exception_vector _align
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exception_vector _align
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|
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.org 0x700
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.org 0x700
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unhandled_exception
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unhandled_exception
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.org 0x800
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.org 0x800
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exception_vector UserISR
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exception_vector UserISR
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.org 0x900
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.org 0x900
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unhandled_exception
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unhandled_exception
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.org 0xa00
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.org 0xa00
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unhandled_exception
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unhandled_exception
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.org 0xb00
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.org 0xb00
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unhandled_exception
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unhandled_exception
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.org 0xc00
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.org 0xc00
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exception_vector OSCtxSw
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exception_vector OSCtxSw
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/* Start of text section */
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/* Start of text section */
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.section .text
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.section .text
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|
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/* _start function - called immediately after reset */
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/* _start function - called immediately after reset */
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_start:
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_start:
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|
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/* Instruction cache enable */
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_ICP
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l.andi r26,r24,SPR_UPR_ICP
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l.sfeq r26,r0
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l.sfeq r26,r0
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l.bf .L8
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l.bf .L8
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l.nop
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l.nop
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/* Disable IC */
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/* Disable IC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_ICE
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l.xori r5,r5,SPR_SR_ICE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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|
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/* Establish cache block size
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/* Establish cache block size
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If BS=0, 16;
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If BS=0, 16;
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If BS=1, 32;
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If BS=1, 32;
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r14 contain block size
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r14 contain block size
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*/
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*/
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l.mfspr r24,r0,SPR_ICCFGR
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l.mfspr r24,r0,SPR_ICCFGR
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.andi r26,r24,SPR_ICCFGR_CBS
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l.srli r28,r26,7
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l.srli r28,r26,7
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l.ori r30,r0,16
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l.ori r30,r0,16
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l.sll r14,r30,r28
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l.sll r14,r30,r28
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|
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/* Establish number of cache sets
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/* Establish number of cache sets
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r16 contains number of cache sets
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r16 contains number of cache sets
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r28 contains log(# of cache sets)
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r28 contains log(# of cache sets)
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*/
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*/
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.andi r26,r24,SPR_ICCFGR_NCS
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l.srli r28,r26,3
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l.srli r28,r26,3
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l.ori r30,r0,1
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l.ori r30,r0,1
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l.sll r16,r30,r28
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l.sll r16,r30,r28
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/* Invalidate IC */
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/* Invalidate IC */
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l.addi r6,r0,0
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l.addi r6,r0,0
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l.sll r5,r14,r28
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l.sll r5,r14,r28
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.L7:
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.L7:
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l.mtspr r0,r6,SPR_ICBIR
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l.mtspr r0,r6,SPR_ICBIR
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l.sfne r6,r5
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l.sfne r6,r5
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l.bf .L7
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l.bf .L7
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l.add r6,r6,r14
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l.add r6,r6,r14
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|
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/* Enable IC */
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/* Enable IC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.ori r6,r6,SPR_SR_ICE
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l.ori r6,r6,SPR_SR_ICE
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l.mtspr r0,r6,SPR_SR
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l.mtspr r0,r6,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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|
|
.L8:
|
.L8:
|
/* Data cache enable */
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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/* Check if DC present and skip enabling otherwise */
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l.mfspr r24,r0,SPR_UPR
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l.mfspr r24,r0,SPR_UPR
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l.andi r26,r24,SPR_UPR_DCP
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l.andi r26,r24,SPR_UPR_DCP
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l.sfeq r26,r0
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l.sfeq r26,r0
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l.bf .L10
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l.bf .L10
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l.nop
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l.nop
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/* Disable DC */
|
/* Disable DC */
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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/* Establish cache block size
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/* Establish cache block size
|
If BS=0, 16;
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If BS=0, 16;
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If BS=1, 32;
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If BS=1, 32;
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r14 contain block size
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r14 contain block size
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*/
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*/
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l.mfspr r24,r0,SPR_DCCFGR
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l.mfspr r24,r0,SPR_DCCFGR
|
l.andi r26,r24,SPR_DCCFGR_CBS
|
l.andi r26,r24,SPR_DCCFGR_CBS
|
l.srli r28,r26,7
|
l.srli r28,r26,7
|
l.ori r30,r0,16
|
l.ori r30,r0,16
|
l.sll r14,r30,r28
|
l.sll r14,r30,r28
|
/* Establish number of cache sets
|
/* Establish number of cache sets
|
r16 contains number of cache sets
|
r16 contains number of cache sets
|
r28 contains log(# of cache sets)
|
r28 contains log(# of cache sets)
|
*/
|
*/
|
l.andi r26,r24,SPR_DCCFGR_NCS
|
l.andi r26,r24,SPR_DCCFGR_NCS
|
l.srli r28,r26,3
|
l.srli r28,r26,3
|
l.ori r30,r0,1
|
l.ori r30,r0,1
|
l.sll r16,r30,r28
|
l.sll r16,r30,r28
|
/* Invalidate DC */
|
/* Invalidate DC */
|
l.addi r6,r0,0
|
l.addi r6,r0,0
|
l.sll r5,r14,r28
|
l.sll r5,r14,r28
|
.L9:
|
.L9:
|
l.mtspr r0,r6,SPR_DCBIR
|
l.mtspr r0,r6,SPR_DCBIR
|
l.sfne r6,r5
|
l.sfne r6,r5
|
l.bf .L9
|
l.bf .L9
|
l.add r6,r6,r14
|
l.add r6,r6,r14
|
/* Enable DC */
|
/* Enable DC */
|
l.mfspr r6,r0,SPR_SR
|
l.mfspr r6,r0,SPR_SR
|
l.ori r6,r6,SPR_SR_DCE
|
l.ori r6,r6,SPR_SR_DCE
|
l.mtspr r0,r6,SPR_SR
|
l.mtspr r0,r6,SPR_SR
|
|
|
.L10:
|
.L10:
|
|
|
/* Clear BSS */
|
/* Clear BSS */
|
load32i r28, ___bss_start
|
load32i r28, ___bss_start
|
load32i r30, __end
|
load32i r30, __end
|
1:
|
1:
|
l.sw (0)(r28), r0
|
l.sw (0)(r28), r0
|
l.sfltu r28, r30
|
l.sfltu r28, r30
|
l.bf 1b
|
l.bf 1b
|
l.addi r28, r28, 4
|
l.addi r28, r28, 4
|
|
|
/* Initialise stack pointer */
|
/* Initialise stack pointer */
|
load32i r1,_stack-4
|
load32i r1,_stack-4
|
|
|
l.addi r2,r0,-3
|
l.addi r2,r0,-3
|
l.and r1,r1,r2
|
l.and r1,r1,r2
|
l.ori r2,r1,0
|
l.ori r2,r1,0
|
|
|
load32i r3,main
|
load32i r3,main
|
|
|
l.jr r3
|
l.jr r3
|
l.addi r3,r0,0
|
l.addi r3,r0,0
|
|
|
|
|
|
|
_align:
|
_align:
|
l.ori r3,r0,0x600
|
l.ori r3,r0,0x600
|
l.nop NOP_REPORT
|
l.nop NOP_REPORT
|
l.mfspr r3,r0,SPR_EPCR_BASE
|
l.mfspr r3,r0,SPR_EPCR_BASE
|
l.nop NOP_REPORT
|
l.nop NOP_REPORT
|
l.lwz r3,0(r3)
|
l.lwz r3,0(r3)
|
l.nop NOP_REPORT
|
l.nop NOP_REPORT
|
l.mfspr r3,r0,SPR_EEAR_BASE
|
l.mfspr r3,r0,SPR_EEAR_BASE
|
l.nop NOP_REPORT
|
l.nop NOP_REPORT
|
/* Loop in place, cause simulator to exit */
|
/* Loop in place, cause simulator to exit */
|
l.ori r3,r0,1
|
l.ori r3,r0,1
|
l.j 0
|
l.j 0
|
l.nop NOP_EXIT
|
l.nop NOP_EXIT
|
|
|
/*
|
/*
|
------------------------------
|
------------------------------
|
OSCtxSw
|
OSCtxSw
|
------------------------------
|
------------------------------
|
Description :
|
Description :
|
This routine switches between two different tasks.
|
This routine switches between two different tasks.
|
The task state of one is saved on its kernel stack.
|
The task state of one is saved on its kernel stack.
|
Then the state of the other is restored from its kernel stack.
|
Then the state of the other is restored from its kernel stack.
|
|
|
There maybe memory management hardware issues
|
There maybe memory management hardware issues
|
|
|
Finally, we can return to the second task, via the 'return'.
|
Finally, we can return to the second task, via the 'return'.
|
|
|
Includes OSIntCtxSw
|
Includes OSIntCtxSw
|
------------------------------
|
------------------------------
|
Uses:
|
Uses:
|
------------------------------
|
------------------------------
|
*/
|
*/
|
|
|
OSCtxSw:
|
OSCtxSw:
|
/* l.sys exception for now so we are in supervisor mode */
|
/* l.sys exception for now so we are in supervisor mode */
|
/* exception - recover pc from epcr */
|
/* exception - recover pc from epcr */
|
|
|
l.mfspr r3,r0,SPR_EPCR_BASE /* save program counter that was put in exception register */
|
l.mfspr r3,r0,SPR_EPCR_BASE /* save program counter that was put in
|
|
exception register */
|
l.sw 0(r1),r3
|
l.sw 0(r1),r3
|
l.mfspr r3,r0,SPR_ESR_BASE /* save status register that was put in exception register */
|
l.mfspr r3,r0,SPR_ESR_BASE /* save status register that was put in
|
|
exception register */
|
l.sw 4(r1),r3
|
l.sw 4(r1),r3
|
|
|
store_context
|
store_context
|
/* Store current stack pointer */
|
/* Store current stack pointer */
|
load32i r3,OSTCBCur /* r3= &OSTCBCur */
|
load32i r3,OSTCBCur /* r3= &OSTCBCur */
|
|
|
l.lwz r3,0(r3) /* r3 = &CurrentTask.OSTCBStkPtr */
|
l.lwz r3,0(r3) /* r3 = &CurrentTask.OSTCBStkPtr */
|
l.sw 0(r3),r1 /* CurrentTask.OSTCBStkPtr = SP */
|
l.sw 0(r3),r1 /* CurrentTask.OSTCBStkPtr = SP */
|
|
|
OSIntCtxSw:
|
OSIntCtxSw:
|
l.jal OSTaskSwHook /* call OSTaskSwHook */
|
l.jal OSTaskSwHook /* call OSTaskSwHook */
|
l.nop
|
l.nop
|
|
|
load32i r2,OSTCBHighRdy /* r2= &OSTCBHighRdy */
|
load32i r2,OSTCBHighRdy /* r2= &OSTCBHighRdy */
|
l.lwz r2,0(r2)
|
l.lwz r2,0(r2)
|
load32i r3,OSTCBCur /* r3= &OSTCBCur */
|
load32i r3,OSTCBCur /* r3= &OSTCBCur */
|
l.sw 0(r3),r2 /* OSTCBCur = OSTCBHighRdy */
|
l.sw 0(r3),r2 /* OSTCBCur = OSTCBHighRdy */
|
|
|
load32i r3,OSPrioHighRdy /* r3= &OSPrioHighRdy */
|
load32i r3,OSPrioHighRdy /* r3= &OSPrioHighRdy */
|
l.lbz r3, 0(r3)
|
l.lbz r3, 0(r3)
|
load32i r4,OSPrioCur /* r4= &OSPrioCur */
|
load32i r4,OSPrioCur /* r4= &OSPrioCur */
|
l.sb 0(r4), r3 /* OSPrioCur = OSPrioHighRdy */
|
l.sb 0(r4), r3 /* OSPrioCur = OSPrioHighRdy */
|
|
|
l.lwz r1, 0(r2) /* sp = OSTCBHighRdy */
|
l.lwz r1, 0(r2) /* sp = OSTCBHighRdy */
|
|
|
|
|
l.lwz r2,0(r1) /* load context for task to be resumed */
|
l.lwz r2,0(r1) /* load context for task to be resumed */
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.lwz r2,4(r1)
|
l.lwz r2,4(r1)
|
l.mtspr r0,r2,SPR_ESR_BASE
|
l.mtspr r0,r2,SPR_ESR_BASE
|
|
|
restore_context
|
restore_context
|
|
|
OSCtxSwBP:
|
OSCtxSwBP:
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
/*
|
/*
|
------------------------------
|
------------------------------
|
OSStartHighRdy
|
OSStartHighRdy
|
------------------------------
|
------------------------------
|
Description :
|
Description :
|
Starts the highest priority task that is available to run
|
Starts the highest priority task that is available to run
|
|
|
OSStartHighRdy() MUST:
|
OSStartHighRdy() MUST:
|
a) Call OSTaskSwHook() then,
|
a) Call OSTaskSwHook() then,
|
b) Set OSRunning to TRUE,
|
b) Set OSRunning to TRUE,
|
c) Switch to the HPT
|
c) Switch to the HPT
|
|
|
------------------------------
|
------------------------------
|
Uses :
|
Uses :
|
------------------------------
|
------------------------------
|
*/
|
*/
|
OSStartHighRdy:
|
OSStartHighRdy:
|
|
|
l.jal OSTaskSwHook /* call OSTaskSwHook */
|
l.jal OSTaskSwHook /* call OSTaskSwHook */
|
l.nop
|
l.nop
|
|
|
load32i r3,OSRunning /* r3= &OSRunning */
|
load32i r3,OSRunning /* r3= &OSRunning */
|
|
|
l.ori r4,r0, 0x01 /* set OSRunning == TRUE */
|
l.ori r4,r0, 0x01 /* set OSRunning == TRUE */
|
l.sb 0(r3), r4
|
l.sb 0(r3), r4
|
/* load stack pointer from next task's TCB area */
|
/* load stack pointer from next task's
|
|
TCB area */
|
load32i r3,OSTCBHighRdy /* r3 = &OSTCBHighRdy */
|
load32i r3,OSTCBHighRdy /* r3 = &OSTCBHighRdy */
|
l.lwz r3,0(r3) /* r3 = &OS_TCB */
|
l.lwz r3,0(r3) /* r3 = &OS_TCB */
|
l.lwz r1, 0(r3) /* stack is the first element */
|
l.lwz r1, 0(r3) /* stack is the first element */
|
|
|
l.lwz r2,0(r1)
|
l.lwz r2,0(r1)
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.lwz r2,4(r1)
|
l.lwz r2,4(r1)
|
l.mtspr r0,r2,SPR_ESR_BASE
|
l.mtspr r0,r2,SPR_ESR_BASE
|
|
|
restore_context
|
restore_context
|
|
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
/*
|
/*
|
------------------------------
|
------------------------------
|
OSTickISR
|
OSTickISR
|
------------------------------
|
------------------------------
|
Description :
|
Description :
|
|
|
------------------------------
|
------------------------------
|
Uses :
|
Uses :
|
------------------------------
|
------------------------------
|
*/
|
*/
|
OSTickISR:
|
OSTickISR:
|
l.mfspr r3,r0,SPR_EPCR_BASE /* save program counter that was put in exception register */
|
l.mfspr r3,r0,SPR_EPCR_BASE /* save program counter that was put
|
|
in exception register */
|
l.sw 0(r1),r3
|
l.sw 0(r1),r3
|
l.mfspr r3,r0,SPR_ESR_BASE /* save status register that was put in exception register */
|
l.mfspr r3,r0,SPR_ESR_BASE /* save status register that was put in
|
|
exception register */
|
l.sw 4(r1),r3
|
l.sw 4(r1),r3
|
|
|
store_context
|
store_context
|
/* either call OSIntEnter or Increment OSIntNesting */
|
/* either call OSIntEnter or Increment OSIntNesting */
|
|
|
/*
|
/*
|
l.jal OSIntEnter
|
l.jal OSIntEnter
|
l.nop
|
l.nop
|
load32i r2,OSIntNesting
|
load32i r2,OSIntNesting
|
l.lbz r3,0(r2)
|
l.lbz r3,0(r2)
|
*/
|
*/
|
load32i r2,OSIntNesting /* r2 &OSIntNesting */
|
load32i r2,OSIntNesting /* r2 &OSIntNesting */
|
l.lbz r3,0(r2) /* r3 OSIntNesting */
|
l.lbz r3,0(r2) /* r3 OSIntNesting */
|
l.addi r3,r3,1
|
l.addi r3,r3,1
|
l.sb 0(r2),r3
|
l.sb 0(r2),r3
|
|
|
/* if (OSIntNesting == 1) OSTCBCur->OSTCBStkPtr = sp */
|
/* if (OSIntNesting == 1) OSTCBCur->OSTCBStkPtr = sp */
|
l.sfeqi r3,1
|
l.sfeqi r3,1
|
l.bnf nest_not_one
|
l.bnf nest_not_one
|
l.nop
|
l.nop
|
|
|
load32i r4,OSTCBCur /* set pointer to Current TCB pointer */
|
load32i r4,OSTCBCur /* set pointer to Current TCB pointer */
|
/* r4= &OSTCBCur */
|
/* r4= &OSTCBCur */
|
|
|
/* Store current stack pointer */
|
/* Store current stack pointer */
|
l.lwz r5,0(r4) /* r5 = &CurrentTask.OSTCBStkPtr */
|
l.lwz r5,0(r4) /* r5 = &CurrentTask.OSTCBStkPtr */
|
l.sw 0(r5),r1 /* CurrentTask.OSTCBStkPtr = SP */
|
l.sw 0(r5),r1 /* CurrentTask.OSTCBStkPtr = SP */
|
|
|
nest_not_one:
|
nest_not_one:
|
/* clear interrupt */
|
/* clear interrupt */
|
load32i r3,SPR_TTMR_LOAD
|
load32i r3,SPR_TTMR_LOAD
|
l.mtspr r0,r3,SPR_TTMR
|
l.mtspr r0,r3,SPR_TTMR
|
|
|
/* optionally re enable interrupt */
|
/* optionally re enable interrupt */
|
|
|
/*Call OSTimeTick()*/
|
/*Call OSTimeTick()*/
|
l.jal OSTimeTick
|
l.jal OSTimeTick
|
l.nop
|
l.nop
|
/*Call OSIntExit()*/
|
/*Call OSIntExit()*/
|
l.jal OSIntExit
|
l.jal OSIntExit
|
l.nop
|
l.nop
|
/* load stack pointer from next task's TCB area */
|
/* load stack pointer from next task's
|
|
TCB area */
|
load32i r3,OSTCBHighRdy /* r3 = &OSTCBHighRdy */
|
load32i r3,OSTCBHighRdy /* r3 = &OSTCBHighRdy */
|
l.lwz r3,0(r3) /* r3 = &OS_TCB */
|
l.lwz r3,0(r3) /* r3 = &OS_TCB */
|
l.lwz r1, 0(r3) /* stack is the first element */
|
l.lwz r1, 0(r3) /* stack is the first element */
|
|
|
l.lwz r2,0(r1)
|
l.lwz r2,0(r1)
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.lwz r2,4(r1)
|
l.lwz r2,4(r1)
|
l.mtspr r0,r2,SPR_ESR_BASE
|
l.mtspr r0,r2,SPR_ESR_BASE
|
|
|
restore_context
|
restore_context
|
|
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
|
|
/*
|
/*
|
------------------------------
|
------------------------------
|
UserISR
|
UserISR
|
------------------------------
|
------------------------------
|
Description :
|
Description :
|
|
|
------------------------------
|
------------------------------
|
Uses :
|
Uses :
|
------------------------------
|
------------------------------
|
*/
|
*/
|
UserISR:
|
UserISR:
|
l.mfspr r2,r0,SPR_EPCR_BASE /* save program counter that was put in exception register */
|
l.mfspr r3,r0,SPR_EPCR_BASE /* save program counter that was put in
|
l.sw 0(r1),r2
|
exception register */
|
l.mfspr r2,r0,SPR_ESR_BASE /* save status register that was put in exception register */
|
l.sw 0(r1),r3
|
l.sw 4(r1),r2
|
l.mfspr r3,r0,SPR_ESR_BASE /* save status register that was put
|
|
in exception register */
|
|
l.sw 4(r1),r3
|
|
|
store_context
|
store_context
|
/* either call OSIntEnter or Increment OSIntNesting */
|
/* either call OSIntEnter or Increment OSIntNesting */
|
|
|
/*
|
/*
|
l.jal _OSIntEnter
|
l.jal _OSIntEnter
|
l.nop
|
l.nop
|
load32i r2,_OSIntNesting
|
load32i r2,_OSIntNesting
|
l.lbz r3,0(r2)
|
l.lbz r3,0(r2)
|
*/
|
*/
|
load32i r2,OSIntNesting /* r2 &OSIntNesting */
|
load32i r2,OSIntNesting /* r2 &OSIntNesting */
|
|
|
l.lbz r3,0(r2) /* r3 OSIntNesting */
|
l.lbz r3,0(r2) /* r3 OSIntNesting */
|
l.addi r3,r3,1
|
l.addi r3,r3,1
|
l.sb 0(r2),r3
|
l.sb 0(r2),r3
|
|
|
/* if (OSIntNesting == 1) OSTCBCur->OSTCBStkPtr = sp */
|
/* if (OSIntNesting == 1) OSTCBCur->OSTCBStkPtr = sp */
|
l.sfeqi r3,1
|
l.sfeqi r3,1
|
l.bnf Unest_not_one
|
l.bnf Unest_not_one
|
l.nop
|
l.nop
|
|
|
load32i r4,OSTCBCur /* set pointer to Current TCB pointer */
|
load32i r4,OSTCBCur /* set pointer to Current TCB pointer */
|
/* r4= &OSTCBCur */
|
/* r4= &OSTCBCur */
|
|
|
/* Store current stack pointer */
|
/* Store current stack pointer */
|
l.lwz r5,0(r4) /* r5 = &CurrentTask.OSTCBStkPtr */
|
l.lwz r5,0(r4) /* r5 = &CurrentTask.OSTCBStkPtr */
|
l.sw 0(r5),r1 /* CurrentTask.OSTCBStkPtr = SP */
|
l.sw 0(r5),r1 /* CurrentTask.OSTCBStkPtr = SP */
|
|
|
Unest_not_one:
|
Unest_not_one:
|
/* clear interrupt */
|
/* clear interrupt */
|
l.mtspr r0,r0,SPR_PICSR
|
l.mtspr r0,r0,SPR_PICSR
|
|
|
/* optionally re enable interrupt */
|
/* optionally re enable interrupt */
|
|
|
/*Call interrupt service routine */
|
/*Call interrupt service routine */
|
|
|
/*Call OSIntExit()*/
|
/*Call OSIntExit()*/
|
l.jal OSIntExit
|
l.jal OSIntExit
|
l.nop
|
l.nop
|
|
|
/* load stack pointer from next task's TCB area */
|
/* load stack pointer from next task's TCB area */
|
load32i r3,OSTCBHighRdy /* r3 = &OSTCBHighRdy */
|
load32i r3,OSTCBHighRdy /* r3 = &OSTCBHighRdy */
|
l.lwz r3,0(r3) /* r3 = &OS_TCB */
|
l.lwz r3,0(r3) /* r3 = &OS_TCB */
|
l.lwz r1, 0(r3) /* stack is the first element */
|
l.lwz r1, 0(r3) /* stack is the first element */
|
|
|
l.lwz r2,0(r1)
|
l.lwz r2,0(r1)
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.mtspr r0,r2,SPR_EPCR_BASE
|
l.lwz r2,4(r1)
|
l.lwz r2,4(r1)
|
l.mtspr r0,r2,SPR_ESR_BASE
|
l.mtspr r0,r2,SPR_ESR_BASE
|
|
|
restore_context
|
restore_context
|
|
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.addi r1,r1,STK_FRAME_SIZE
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
