[Library]
|
[Library]
|
|
|
; Altera specific primitive library mappings
|
; Altera specific primitive library mappings
|
|
|
vital2000 = $MODEL_TECH/../vital2000
|
vital2000 = $MODEL_TECH/../vital2000
|
ieee = $MODEL_TECH/../ieee
|
ieee = $MODEL_TECH/../ieee
|
verilog = $MODEL_TECH/../verilog
|
verilog = $MODEL_TECH/../verilog
|
std = $MODEL_TECH/../std
|
std = $MODEL_TECH/../std
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
synopsys = $MODEL_TECH/../synopsys
|
synopsys = $MODEL_TECH/../synopsys
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
apex20k = $MODEL_TECH/../altera/vhdl/apex20k
|
apex20k = $MODEL_TECH/../altera/vhdl/apex20k
|
apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
|
apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
|
apexii = $MODEL_TECH/../altera/vhdl/apexii
|
apexii = $MODEL_TECH/../altera/vhdl/apexii
|
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
altera = $MODEL_TECH/../altera/vhdl/altera
|
altera = $MODEL_TECH/../altera/vhdl/altera
|
lpm = $MODEL_TECH/../altera/vhdl/220model
|
lpm = $MODEL_TECH/../altera/vhdl/220model
|
220model = $MODEL_TECH/../altera/vhdl/220model
|
220model = $MODEL_TECH/../altera/vhdl/220model
|
alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
|
alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
|
flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
|
flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
|
flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
|
flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
|
max = $MODEL_TECH/../altera/vhdl/max
|
max = $MODEL_TECH/../altera/vhdl/max
|
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
stratix = $MODEL_TECH/../altera/vhdl/stratix
|
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
|
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
|
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
|
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
|
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
|
hcstratix = $MODEL_TECH/../altera/vhdl/hcstratix
|
hcstratix = $MODEL_TECH/../altera/vhdl/hcstratix
|
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
|
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
|
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
|
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
|
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
|
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
|
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
|
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
|
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
|
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
|
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
|
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
|
apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
|
apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
|
apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
|
apexii_ver = $MODEL_TECH/../altera/verilog/apexii
|
apexii_ver = $MODEL_TECH/../altera/verilog/apexii
|
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
|
alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
|
flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
|
flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
|
flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
|
flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
|
max_ver = $MODEL_TECH/../altera/verilog/max
|
max_ver = $MODEL_TECH/../altera/verilog/max
|
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
|
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
|
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
|
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
|
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
|
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
|
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
|
hcstratix_ver = $MODEL_TECH/../altera/verilog/hcstratix
|
hcstratix_ver = $MODEL_TECH/../altera/verilog/hcstratix
|
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
|
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
|
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
|
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
|
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
|
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
|
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
|
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
|
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
|
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
|
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
|
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
work = uart16550
|
work = uart16550
|
[vcom]
|
[vcom]
|
; Turn on VHDL-1993 as the default. Normally is off.
|
; Turn on VHDL-1993 as the default. Normally is off.
|
; VHDL93 = 1
|
; VHDL93 = 1
|
|
|
; Show source line containing error. Default is off.
|
; Show source line containing error. Default is off.
|
; Show_source = 1
|
; Show_source = 1
|
|
|
; Turn off unbound-component warnings. Default is on.
|
; Turn off unbound-component warnings. Default is on.
|
; Show_Warning1 = 0
|
; Show_Warning1 = 0
|
|
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
; Show_Warning2 = 0
|
; Show_Warning2 = 0
|
|
|
; Turn off null-range warnings. Default is on.
|
; Turn off null-range warnings. Default is on.
|
; Show_Warning3 = 0
|
; Show_Warning3 = 0
|
|
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
; Show_Warning4 = 0
|
; Show_Warning4 = 0
|
|
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
; Show_Warning5 = 0
|
; Show_Warning5 = 0
|
|
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
; Optimize_1164 = 0
|
; Optimize_1164 = 0
|
|
|
; Turn on resolving of ambiguous function overloading in favor of the
|
; Turn on resolving of ambiguous function overloading in favor of the
|
; "explicit" function declaration (not the one automatically created by
|
; "explicit" function declaration (not the one automatically created by
|
; the compiler for each type declaration). Default is off.
|
; the compiler for each type declaration). Default is off.
|
; .ini file has Explict enable so that std_logic_signed/unsigned
|
; .ini file has Explict enable so that std_logic_signed/unsigned
|
; will match synthesis tools behavior.
|
; will match synthesis tools behavior.
|
Explicit = 1
|
Explicit = 1
|
|
|
; Turn off VITAL compliance checking. Default is checking on.
|
; Turn off VITAL compliance checking. Default is checking on.
|
; NoVitalCheck = 1
|
; NoVitalCheck = 1
|
|
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
; IgnoreVitalErrors = 1
|
; IgnoreVitalErrors = 1
|
|
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
; Show_VitalChecksWarnings = false
|
; Show_VitalChecksWarnings = false
|
|
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
; NoVital = 1
|
; NoVital = 1
|
|
|
; Turn off inclusion of debugging info within design units. Default is to include.
|
; Turn off inclusion of debugging info within design units. Default is to include.
|
; NoDebug = 1
|
; NoDebug = 1
|
|
|
; Turn off "loading..." messages. Default is messages on.
|
; Turn off "loading..." messages. Default is messages on.
|
; Quiet = 1
|
; Quiet = 1
|
|
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
; -- signals used (read) by a process must be in the sensitivity list
|
; -- signals used (read) by a process must be in the sensitivity list
|
; CheckSynthesis = 1
|
; CheckSynthesis = 1
|
|
|
; Require the user to specify a configuration for all bindings,
|
; Require the user to specify a configuration for all bindings,
|
; and do not generate a compile time default binding for the
|
; and do not generate a compile time default binding for the
|
; component. This will result in an elaboration error of
|
; component. This will result in an elaboration error of
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
; issue of a false dependency upon the unused default binding.
|
; issue of a false dependency upon the unused default binding.
|
|
|
; RequireConfigForAllDefaultBinding = 1
|
; RequireConfigForAllDefaultBinding = 1
|
|
|
[vlog]
|
[vlog]
|
|
|
; Turn off inclusion of debugging info within design units. Default is to include.
|
; Turn off inclusion of debugging info within design units. Default is to include.
|
; NoDebug = 1
|
; NoDebug = 1
|
|
|
; Turn off "loading..." messages. Default is messages on.
|
; Turn off "loading..." messages. Default is messages on.
|
; Quiet = 1
|
; Quiet = 1
|
|
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
; Default is off.
|
; Default is off.
|
; Hazard = 1
|
; Hazard = 1
|
|
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
; insensitivity for module names. Default is no conversion.
|
; insensitivity for module names. Default is no conversion.
|
; UpCase = 1
|
; UpCase = 1
|
|
|
; Turns on incremental compilation of modules
|
; Turns on incremental compilation of modules
|
; Incremental = 1
|
; Incremental = 1
|
|
|
[vsim]
|
[vsim]
|
; Simulator resolution
|
; Simulator resolution
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
Resolution = ps
|
Resolution = ps
|
|
|
; User time unit for run commands
|
; User time unit for run commands
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
; then UserTimeUnit defaults to ps.
|
; then UserTimeUnit defaults to ps.
|
UserTimeUnit = default
|
UserTimeUnit = default
|
|
|
; Default run length
|
; Default run length
|
RunLength = 100
|
RunLength = 100
|
|
|
; Maximum iterations that can be run without advancing simulation time
|
; Maximum iterations that can be run without advancing simulation time
|
IterationLimit = 5000
|
IterationLimit = 5000
|
|
|
; Directive to license manager:
|
; Directive to license manager:
|
; vhdl Immediately reserve a VHDL license
|
; vhdl Immediately reserve a VHDL license
|
; vlog Immediately reserve a Verilog license
|
; vlog Immediately reserve a Verilog license
|
; plus Immediately reserve a VHDL and Verilog license
|
; plus Immediately reserve a VHDL and Verilog license
|
; nomgc Do not look for Mentor Graphics Licenses
|
; nomgc Do not look for Mentor Graphics Licenses
|
; nomti Do not look for Model Technology Licenses
|
; nomti Do not look for Model Technology Licenses
|
; noqueue Do not wait in the license queue when a license isn't available
|
; noqueue Do not wait in the license queue when a license isn't available
|
; License = plus
|
; License = plus
|
|
|
; Stop the simulator after an assertion message
|
; Stop the simulator after an assertion message
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
BreakOnAssertion = 3
|
BreakOnAssertion = 3
|
|
|
; Assertion Message Format
|
; Assertion Message Format
|
; %S - Severity Level
|
; %S - Severity Level
|
; %R - Report Message
|
; %R - Report Message
|
; %T - Time of assertion
|
; %T - Time of assertion
|
; %D - Delta
|
; %D - Delta
|
; %I - Instance or Region pathname (if available)
|
; %I - Instance or Region pathname (if available)
|
; %% - print '%' character
|
; %% - print '%' character
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
|
|
; Assertion File - alternate file for storing assertion messages
|
; Assertion File - alternate file for storing assertion messages
|
; AssertFile = assert.log
|
; AssertFile = assert.log
|
|
|
; Default radix for all windows and commands...
|
; Default radix for all windows and commands...
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
DefaultRadix = symbolic
|
DefaultRadix = symbolic
|
|
|
; VSIM Startup command
|
; VSIM Startup command
|
; Startup = do startup.do
|
; Startup = do startup.do
|
|
|
; File for saving command transcript
|
; File for saving command transcript
|
TranscriptFile = transcript
|
TranscriptFile = transcript
|
|
|
; File for saving command history
|
; File for saving command history
|
;CommandHistory = cmdhist.log
|
;CommandHistory = cmdhist.log
|
|
|
; Specify whether paths in simulator commands should be described
|
; Specify whether paths in simulator commands should be described
|
; in VHDL or Verilog format. For VHDL, PathSeparator = /
|
; in VHDL or Verilog format. For VHDL, PathSeparator = /
|
; for Verilog, PathSeparator = .
|
; for Verilog, PathSeparator = .
|
PathSeparator = /
|
PathSeparator = /
|
|
|
; Specify the dataset separator for fully rooted contexts.
|
; Specify the dataset separator for fully rooted contexts.
|
; The default is ':'. For example, sim:/top
|
; The default is ':'. For example, sim:/top
|
; Must not be the same character as PathSeparator.
|
; Must not be the same character as PathSeparator.
|
DatasetSeparator = :
|
DatasetSeparator = :
|
|
|
; Disable assertion messages
|
; Disable assertion messages
|
; IgnoreNote = 1
|
; IgnoreNote = 1
|
; IgnoreWarning = 1
|
; IgnoreWarning = 1
|
; IgnoreError = 1
|
; IgnoreError = 1
|
; IgnoreFailure = 1
|
; IgnoreFailure = 1
|
|
|
; Default force kind. May be freeze, drive, or deposit
|
; Default force kind. May be freeze, drive, or deposit
|
; or in other terms, fixed, wired or charged.
|
; or in other terms, fixed, wired or charged.
|
; DefaultForceKind = freeze
|
; DefaultForceKind = freeze
|
|
|
; If zero, open files when elaborated
|
; If zero, open files when elaborated
|
; else open files on first read or write
|
; else open files on first read or write
|
; DelayFileOpen = 0
|
; DelayFileOpen = 0
|
|
|
; Control VHDL files opened for write
|
; Control VHDL files opened for write
|
; 0 = Buffered, 1 = Unbuffered
|
; 0 = Buffered, 1 = Unbuffered
|
UnbufferedOutput = 0
|
UnbufferedOutput = 0
|
|
|
; Control number of VHDL files open concurrently
|
; Control number of VHDL files open concurrently
|
; This number should always be less then the
|
; This number should always be less then the
|
; current ulimit setting for max file descriptors
|
; current ulimit setting for max file descriptors
|
; 0 = unlimited
|
; 0 = unlimited
|
ConcurrentFileLimit = 40
|
ConcurrentFileLimit = 40
|
|
|
; This controls the number of hierarchical regions displayed as
|
; This controls the number of hierarchical regions displayed as
|
; part of a signal name shown in the waveform window. The default
|
; part of a signal name shown in the waveform window. The default
|
; value or a value of zero tells VSIM to display the full name.
|
; value or a value of zero tells VSIM to display the full name.
|
; WaveSignalNameWidth = 0
|
; WaveSignalNameWidth = 0
|
|
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
; and std_logic_signed packages.
|
; and std_logic_signed packages.
|
; StdArithNoWarnings = 1
|
; StdArithNoWarnings = 1
|
|
|
; Turn off warnings from the IEEE numeric_std and numeric_bit
|
; Turn off warnings from the IEEE numeric_std and numeric_bit
|
; packages.
|
; packages.
|
; NumericStdNoWarnings = 1
|
; NumericStdNoWarnings = 1
|
|
|
; Control the format of a generate statement label. Don't quote it.
|
; Control the format of a generate statement label. Don't quote it.
|
; GenerateFormat = %s__%d
|
; GenerateFormat = %s__%d
|
|
|
; Specify whether checkpoint files should be compressed.
|
; Specify whether checkpoint files should be compressed.
|
; The default is to be compressed.
|
; The default is to be compressed.
|
; CheckpointCompressMode = 0
|
; CheckpointCompressMode = 0
|
|
|
; List of dynamically loaded objects for Verilog PLI applications
|
; List of dynamically loaded objects for Verilog PLI applications
|
; Veriuser = veriuser.sl
|
; Veriuser = veriuser.sl
|
[Project]
|
[Project]
|
|
; Warning -- Do not edit the project properties directly.
|
|
; Property names are dynamic in nature and property
|
|
; values have special syntax. Changing property data directly
|
|
; can result in a corrupt MPF file. All project properties
|
|
; can be modified through project window dialogs.
|
Project_Version = 6
|
Project_Version = 6
|
Project_DefaultLib = uart16550
|
Project_DefaultLib = work
|
Project_SortMethod = unused
|
Project_SortMethod = unused
|
Project_Files_Count = 10
|
Project_Files_Count = 10
|
Project_File_0 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
|
Project_File_0 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
|
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1236708645 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_1 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
|
Project_File_1 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
|
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1085139805 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_2 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
|
Project_File_2 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
|
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1027977378 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_3 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
|
Project_File_3 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
|
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_4 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
|
Project_File_4 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
|
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1101115319 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_5 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
|
Project_File_5 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
|
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1087569975 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_6 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
|
Project_File_6 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
|
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_7 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
|
Project_File_7 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
|
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1085142915 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_8 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
|
Project_File_8 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
|
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1057947626 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_File_9 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
|
Project_File_9 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
|
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
|
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
|
Project_Sim_Count = 0
|
Project_Sim_Count = 0
|
Project_Folder_Count = 0
|
Project_Folder_Count = 0
|
Echo_Compile_Output = 0
|
Echo_Compile_Output = 0
|
Save_Compile_Report = 1
|
Save_Compile_Report = 1
|
Project_Opt_Count = 0
|
Project_Opt_Count = 0
|
ForceSoftPaths = 0
|
ForceSoftPaths = 0
|
ReOpenSourceFiles = 1
|
|
CloseSourceFiles = 1
|
|
ProjectStatusDelay = 5000
|
ProjectStatusDelay = 5000
|
VERILOG_DoubleClick = Edit
|
VERILOG_DoubleClick = Edit
|
VERILOG_CustomDoubleClick =
|
VERILOG_CustomDoubleClick =
|
SYSTEMVERILOG_DoubleClick = Edit
|
SYSTEMVERILOG_DoubleClick = Edit
|
SYSTEMVERILOG_CustomDoubleClick =
|
SYSTEMVERILOG_CustomDoubleClick =
|
VHDL_DoubleClick = Edit
|
VHDL_DoubleClick = Edit
|
VHDL_CustomDoubleClick =
|
VHDL_CustomDoubleClick =
|
PSL_DoubleClick = Edit
|
PSL_DoubleClick = Edit
|
PSL_CustomDoubleClick =
|
PSL_CustomDoubleClick =
|
TEXT_DoubleClick = Edit
|
TEXT_DoubleClick = Edit
|
TEXT_CustomDoubleClick =
|
TEXT_CustomDoubleClick =
|
SYSTEMC_DoubleClick = Edit
|
SYSTEMC_DoubleClick = Edit
|
SYSTEMC_CustomDoubleClick =
|
SYSTEMC_CustomDoubleClick =
|
TCL_DoubleClick = Edit
|
TCL_DoubleClick = Edit
|
TCL_CustomDoubleClick =
|
TCL_CustomDoubleClick =
|
MACRO_DoubleClick = Edit
|
MACRO_DoubleClick = Edit
|
MACRO_CustomDoubleClick =
|
MACRO_CustomDoubleClick =
|
VCD_DoubleClick = Edit
|
VCD_DoubleClick = Edit
|
VCD_CustomDoubleClick =
|
VCD_CustomDoubleClick =
|
SDF_DoubleClick = Edit
|
SDF_DoubleClick = Edit
|
SDF_CustomDoubleClick =
|
SDF_CustomDoubleClick =
|
XML_DoubleClick = Edit
|
XML_DoubleClick = Edit
|
XML_CustomDoubleClick =
|
XML_CustomDoubleClick =
|
LOGFILE_DoubleClick = Edit
|
LOGFILE_DoubleClick = Edit
|
LOGFILE_CustomDoubleClick =
|
LOGFILE_CustomDoubleClick =
|
UCDB_DoubleClick = Edit
|
UCDB_DoubleClick = Edit
|
UCDB_CustomDoubleClick =
|
UCDB_CustomDoubleClick =
|
EditorState =
|
|
Project_Major_Version = 6
|
Project_Major_Version = 6
|
Project_Minor_Version = 4
|
Project_Minor_Version = 5
|
|
|
