// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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//
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//
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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module boot_rom_1( data, addr, we, clk, q );
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module boot_rom_1( data, addr, we, clk, q );
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parameter DATA_WIDTH = 1;
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parameter DATA_WIDTH = 1;
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parameter ADDR_WIDTH = 1;
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parameter ADDR_WIDTH = 1;
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parameter MEM_INIT = 1;
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parameter MEM_INIT = 1;
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input [(DATA_WIDTH-1):0] data;
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input [(DATA_WIDTH-1):0] data;
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input [(ADDR_WIDTH-1):0] addr;
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input [(ADDR_WIDTH-1):0] addr;
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input we;
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input we;
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input clk;
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input clk;
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output [(DATA_WIDTH-1):0] q;
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output [(DATA_WIDTH-1):0] q;
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// Declare the RAM variable
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// Declare the RAM variable
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reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
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reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
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reg [ADDR_WIDTH-1:0] addr_reg;
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reg [ADDR_WIDTH-1:0] addr_reg;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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// Write
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// Write
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if (we) ram[addr] <= data;
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if (we) ram[addr] <= data;
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addr_reg <= addr;
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addr_reg <= addr;
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end
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end
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// Read returns NEW data at addr if we == 1'b1. This is the
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// Read returns NEW data at addr if we == 1'b1. This is the
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// natural behavior of TriMatrix memory blocks in Single Port
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// natural behavior of TriMatrix memory blocks in Single Port
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// mode
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// mode
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assign q = ram[addr_reg];
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assign q = ram[addr_reg];
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generate
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generate
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if( MEM_INIT != 0 )
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if( MEM_INIT != 0 )
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initial
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initial
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$readmemh( "../../../sw/load_this_to_ram/boot_rom_1.txt", ram );
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$readmemh( "../../../sw/load_this_to_ram/boot_rom_1.txt", ram );
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endgenerate
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endgenerate
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