//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// OR1200's Tick Timer ////
|
//// OR1200's Tick Timer ////
|
//// ////
|
//// ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// http://www.opencores.org/cores/or1k/ ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// TT according to OR1K architectural specification. ////
|
//// TT according to OR1K architectural specification. ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// None ////
|
//// None ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.7 2001/10/14 13:12:10 lampret
|
// Revision 1.7 2001/10/14 13:12:10 lampret
|
// MP3 version.
|
// MP3 version.
|
//
|
//
|
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
|
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
|
// no message
|
// no message
|
//
|
//
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
// Major clean-up.
|
// Major clean-up.
|
//
|
//
|
// Revision 1.1 2001/07/20 00:46:23 lampret
|
// Revision 1.1 2001/07/20 00:46:23 lampret
|
// Development version of RTL. Libraries are missing.
|
// Development version of RTL. Libraries are missing.
|
//
|
//
|
//
|
//
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "defines.v"
|
`include "defines.v"
|
|
|
module tt(
|
module tt(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
int
|
int
|
);
|
);
|
|
|
//
|
//
|
// RISC Internal Interface
|
// RISC Internal Interface
|
//
|
//
|
input clk; // Clock
|
input clk; // Clock
|
input rst; // Reset
|
input rst; // Reset
|
input spr_cs; // SPR CS
|
input spr_cs; // SPR CS
|
input spr_write; // SPR Write
|
input spr_write; // SPR Write
|
input [31:0] spr_addr; // SPR Address
|
input [31:0] spr_addr; // SPR Address
|
input [31:0] spr_dat_i; // SPR Write Data
|
input [31:0] spr_dat_i; // SPR Write Data
|
output [31:0] spr_dat_o; // SPR Read Data
|
output [31:0] spr_dat_o; // SPR Read Data
|
output int; // Interrupt output
|
output int; // Interrupt output
|
|
|
`ifdef TT_IMPLEMENTED
|
`ifdef TT_IMPLEMENTED
|
|
|
//
|
//
|
// TT Mode Register bits (or no register)
|
// TT Mode Register bits (or no register)
|
//
|
//
|
`ifdef TT_TTMR
|
`ifdef TT_TTMR
|
reg [31:0] ttmr; // TTMR bits
|
reg [31:0] ttmr; // TTMR bits
|
`else
|
`else
|
wire [31:0] ttmr; // No TTMR register
|
wire [31:0] ttmr; // No TTMR register
|
`endif
|
`endif
|
|
|
//
|
//
|
// TT Count Register bits (or no register)
|
// TT Count Register bits (or no register)
|
//
|
//
|
`ifdef TT_TTCR
|
`ifdef TT_TTCR
|
reg [31:0] ttcr; // TTCR bits
|
reg [31:0] ttcr; // TTCR bits
|
`else
|
`else
|
wire [31:0] ttcr; // No TTCR register
|
wire [31:0] ttcr; // No TTCR register
|
`endif
|
`endif
|
|
|
//
|
//
|
// Internal wires & regs
|
// Internal wires & regs
|
//
|
//
|
wire ttmr_sel; // TTMR select
|
wire ttmr_sel; // TTMR select
|
wire ttcr_sel; // TTCR select
|
wire ttcr_sel; // TTCR select
|
wire match; // Asserted when TTMR[TP]
|
wire match; // Asserted when TTMR[TP]
|
// is equal to TTCR[27:0]
|
// is equal to TTCR[27:0]
|
wire restart; // Restart counter when asserted
|
wire restart; // Restart counter when asserted
|
wire stop; // Stop counter when asserted
|
wire stop; // Stop counter when asserted
|
reg [31:0] spr_dat_o; // SPR data out
|
reg [31:0] spr_dat_o; // SPR data out
|
|
|
//
|
//
|
// TT registers address decoder
|
// TT registers address decoder
|
//
|
//
|
assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
|
assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
|
assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
|
assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
|
|
|
//
|
//
|
// Write to TTMR or update of TTMR[IP] bit
|
// Write to TTMR or update of TTMR[IP] bit
|
//
|
//
|
`ifdef TT_TTMR
|
`ifdef TT_TTMR
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
ttmr <= 32'b0;
|
ttmr <= 32'b0;
|
else if (ttmr_sel && spr_write)
|
else if (ttmr_sel && spr_write)
|
ttmr <= #1 spr_dat_i;
|
ttmr <= #1 spr_dat_i;
|
else if (ttmr[`TT_TTMR_IE])
|
else if (ttmr[`TT_TTMR_IE])
|
ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] | int;
|
ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] | int;
|
`else
|
`else
|
assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
|
assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3
|
`endif
|
`endif
|
|
|
//
|
//
|
// Write to or increment of TTCR
|
// Write to or increment of TTCR
|
//
|
//
|
`ifdef TT_TTCR
|
`ifdef TT_TTCR
|
always @(posedge clk or posedge restart)
|
always @(posedge clk or posedge restart)
|
if (restart)
|
if (restart)
|
ttcr <= 32'b0;
|
ttcr <= 32'b0;
|
else if (ttcr_sel && spr_write)
|
else if (ttcr_sel && spr_write)
|
ttcr <= #1 spr_dat_i;
|
ttcr <= #1 spr_dat_i;
|
else if (!stop)
|
else if (!stop)
|
ttcr <= #1 ttcr + 1'd1;
|
ttcr <= #1 ttcr + 1'd1;
|
`else
|
`else
|
assign ttcr = 32'b0;
|
assign ttcr = 32'b0;
|
`endif
|
`endif
|
|
|
//
|
//
|
// Read TT registers
|
// Read TT registers
|
//
|
//
|
always @(spr_addr or ttmr or ttcr)
|
always @(spr_addr or ttmr or ttcr)
|
case (spr_addr[`TTOFS_BITS]) // synopsys full_case parallel_case
|
case (spr_addr[`TTOFS_BITS]) // synopsys full_case parallel_case
|
`ifdef TT_READREGS
|
`ifdef TT_READREGS
|
`TT_OFS_TTMR: spr_dat_o = ttmr;
|
`TT_OFS_TTMR: spr_dat_o = ttmr;
|
`endif
|
`endif
|
default: spr_dat_o = ttcr;
|
default: spr_dat_o = ttcr;
|
endcase
|
endcase
|
|
|
//
|
//
|
// A match when TTMR[TP] is equal to TTCR[27:0]
|
// A match when TTMR[TP] is equal to TTCR[27:0]
|
//
|
//
|
assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
|
assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
|
|
|
//
|
//
|
// Restart when match and TTMR[M]==0x1 or when rst is asserted
|
// Restart when match and TTMR[M]==0x1 or when rst is asserted
|
//
|
//
|
assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
|
assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
|
|
|
//
|
//
|
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0
|
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0
|
//
|
//
|
assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) || (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
|
assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) || (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
|
|
|
//
|
//
|
// Generate an interrupt request
|
// Generate an interrupt request
|
//
|
//
|
assign int = match & ttmr[`TT_TTMR_IE];
|
assign int = match & ttmr[`TT_TTMR_IE];
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// When TT is not implemented, drive all outputs as would when TT is disabled
|
// When TT is not implemented, drive all outputs as would when TT is disabled
|
//
|
//
|
assign int = 1'b0;
|
assign int = 1'b0;
|
|
|
//
|
//
|
// Read TT registers
|
// Read TT registers
|
//
|
//
|
`ifdef TT_READREGS
|
`ifdef TT_READREGS
|
assign spr_dat_o = 32'b0;
|
assign spr_dat_o = 32'b0;
|
`endif
|
`endif
|
|
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
