/* CPU support.
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/* CPU support.
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Copyright (C) 1998 Free Software Foundation, Inc.
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Copyright (C) 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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Contributed by Cygnus Solutions.
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This file is part of GDB, the GNU debugger.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* This file is intended to be included by sim-base.h.
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/* This file is intended to be included by sim-base.h.
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This file provides an interface between the simulator framework and
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This file provides an interface between the simulator framework and
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the selected cpu. */
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the selected cpu. */
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#ifndef SIM_CPU_H
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#ifndef SIM_CPU_H
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#define SIM_CPU_H
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#define SIM_CPU_H
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/* Type of function to return an insn name. */
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/* Type of function to return an insn name. */
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typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int);
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typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int);
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/* Types for register access functions.
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/* Types for register access functions.
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These routines implement the sim_{fetch,store}_register interface. */
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These routines implement the sim_{fetch,store}_register interface. */
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typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int);
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typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int);
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typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int);
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typedef int (CPUREG_STORE_FN) (sim_cpu *, int, unsigned char *, int);
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/* Types for PC access functions.
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/* Types for PC access functions.
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Some simulators require a functional interface to access the program
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Some simulators require a functional interface to access the program
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counter [a macro is insufficient as the PC is kept in a cpu-specific part
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counter [a macro is insufficient as the PC is kept in a cpu-specific part
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of the sim_cpu struct]. */
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of the sim_cpu struct]. */
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typedef sim_cia (PC_FETCH_FN) (sim_cpu *);
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typedef sim_cia (PC_FETCH_FN) (sim_cpu *);
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typedef void (PC_STORE_FN) (sim_cpu *, sim_cia);
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typedef void (PC_STORE_FN) (sim_cpu *, sim_cia);
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/* Pseudo baseclass for each cpu. */
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/* Pseudo baseclass for each cpu. */
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typedef struct {
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typedef struct {
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/* Backlink to main state struct. */
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/* Backlink to main state struct. */
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SIM_DESC state;
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SIM_DESC state;
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#define CPU_STATE(cpu) ((cpu)->base.state)
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#define CPU_STATE(cpu) ((cpu)->base.state)
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/* Processor index within the SD_DESC */
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/* Processor index within the SD_DESC */
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int index;
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int index;
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#define CPU_INDEX(cpu) ((cpu)->base.index)
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#define CPU_INDEX(cpu) ((cpu)->base.index)
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/* The name of the cpu. */
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/* The name of the cpu. */
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const char *name;
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const char *name;
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#define CPU_NAME(cpu) ((cpu)->base.name)
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#define CPU_NAME(cpu) ((cpu)->base.name)
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/* Options specific to this cpu. */
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/* Options specific to this cpu. */
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struct option_list *options;
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struct option_list *options;
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#define CPU_OPTIONS(cpu) ((cpu)->base.options)
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#define CPU_OPTIONS(cpu) ((cpu)->base.options)
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/* Processor specific core data */
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/* Processor specific core data */
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sim_cpu_core core;
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sim_cpu_core core;
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#define CPU_CORE(cpu) (& (cpu)->base.core)
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#define CPU_CORE(cpu) (& (cpu)->base.core)
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/* Number of instructions (used to iterate over CPU_INSN_NAME). */
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/* Number of instructions (used to iterate over CPU_INSN_NAME). */
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unsigned int max_insns;
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unsigned int max_insns;
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#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns)
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#define CPU_MAX_INSNS(cpu) ((cpu)->base.max_insns)
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/* Function to return the name of an insn. */
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/* Function to return the name of an insn. */
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CPU_INSN_NAME_FN *insn_name;
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CPU_INSN_NAME_FN *insn_name;
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#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name)
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#define CPU_INSN_NAME(cpu) ((cpu)->base.insn_name)
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/* Trace data. See sim-trace.h. */
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/* Trace data. See sim-trace.h. */
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TRACE_DATA trace_data;
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TRACE_DATA trace_data;
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#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
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#define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
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/* Maximum number of debuggable entities.
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/* Maximum number of debuggable entities.
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This debugging is not intended for normal use.
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This debugging is not intended for normal use.
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It is only enabled when the simulator is configured with --with-debug
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It is only enabled when the simulator is configured with --with-debug
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which shouldn't normally be specified. */
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which shouldn't normally be specified. */
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#ifndef MAX_DEBUG_VALUES
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#ifndef MAX_DEBUG_VALUES
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#define MAX_DEBUG_VALUES 4
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#define MAX_DEBUG_VALUES 4
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#endif
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#endif
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/* Boolean array of specified debugging flags. */
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/* Boolean array of specified debugging flags. */
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char debug_flags[MAX_DEBUG_VALUES];
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char debug_flags[MAX_DEBUG_VALUES];
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#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
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#define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
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/* Standard values. */
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/* Standard values. */
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#define DEBUG_INSN_IDX 0
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#define DEBUG_INSN_IDX 0
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#define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
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#define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
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/* Debugging output goes to this or stderr if NULL.
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/* Debugging output goes to this or stderr if NULL.
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We can't store `stderr' here as stderr goes through a callback. */
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We can't store `stderr' here as stderr goes through a callback. */
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FILE *debug_file;
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FILE *debug_file;
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#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
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#define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
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/* Profile data. See sim-profile.h. */
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/* Profile data. See sim-profile.h. */
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PROFILE_DATA profile_data;
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PROFILE_DATA profile_data;
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#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
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#define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
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#ifdef SIM_HAVE_MODEL
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#ifdef SIM_HAVE_MODEL
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/* Machine tables for this cpu. See sim-model.h. */
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/* Machine tables for this cpu. See sim-model.h. */
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const MACH *mach;
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const MACH *mach;
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#define CPU_MACH(cpu) ((cpu)->base.mach)
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#define CPU_MACH(cpu) ((cpu)->base.mach)
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/* The selected model. */
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/* The selected model. */
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const MODEL *model;
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const MODEL *model;
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#define CPU_MODEL(cpu) ((cpu)->base.model)
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#define CPU_MODEL(cpu) ((cpu)->base.model)
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/* Model data (profiling state, etc.). */
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/* Model data (profiling state, etc.). */
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void *model_data;
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void *model_data;
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#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data)
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#define CPU_MODEL_DATA(cpu) ((cpu)->base.model_data)
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#endif
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#endif
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/* Routines to fetch/store registers. */
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/* Routines to fetch/store registers. */
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CPUREG_FETCH_FN *reg_fetch;
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CPUREG_FETCH_FN *reg_fetch;
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#define CPU_REG_FETCH(c) ((c)->base.reg_fetch)
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#define CPU_REG_FETCH(c) ((c)->base.reg_fetch)
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CPUREG_STORE_FN *reg_store;
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CPUREG_STORE_FN *reg_store;
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#define CPU_REG_STORE(c) ((c)->base.reg_store)
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#define CPU_REG_STORE(c) ((c)->base.reg_store)
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PC_FETCH_FN *pc_fetch;
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PC_FETCH_FN *pc_fetch;
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#define CPU_PC_FETCH(c) ((c)->base.pc_fetch)
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#define CPU_PC_FETCH(c) ((c)->base.pc_fetch)
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PC_STORE_FN *pc_store;
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PC_STORE_FN *pc_store;
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#define CPU_PC_STORE(c) ((c)->base.pc_store)
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#define CPU_PC_STORE(c) ((c)->base.pc_store)
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} sim_cpu_base;
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} sim_cpu_base;
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/* Create all cpus. */
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/* Create all cpus. */
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extern SIM_RC sim_cpu_alloc_all (SIM_DESC, int, int);
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extern SIM_RC sim_cpu_alloc_all (SIM_DESC, int, int);
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/* Create a cpu. */
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/* Create a cpu. */
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extern sim_cpu *sim_cpu_alloc (SIM_DESC, int);
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extern sim_cpu *sim_cpu_alloc (SIM_DESC, int);
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/* Release resources held by all cpus. */
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/* Release resources held by all cpus. */
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extern void sim_cpu_free_all (SIM_DESC);
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extern void sim_cpu_free_all (SIM_DESC);
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/* Release resources held by a cpu. */
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/* Release resources held by a cpu. */
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extern void sim_cpu_free (sim_cpu *);
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extern void sim_cpu_free (sim_cpu *);
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/* Return a pointer to the cpu data for CPU_NAME, or NULL if not found. */
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/* Return a pointer to the cpu data for CPU_NAME, or NULL if not found. */
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extern sim_cpu *sim_cpu_lookup (SIM_DESC, const char *);
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extern sim_cpu *sim_cpu_lookup (SIM_DESC, const char *);
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/* Return prefix to use in cpu specific messages. */
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/* Return prefix to use in cpu specific messages. */
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extern const char *sim_cpu_msg_prefix (sim_cpu *);
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extern const char *sim_cpu_msg_prefix (sim_cpu *);
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/* Cover fn to sim_io_eprintf. */
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/* Cover fn to sim_io_eprintf. */
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extern void sim_io_eprintf_cpu (sim_cpu *, const char *, ...);
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extern void sim_io_eprintf_cpu (sim_cpu *, const char *, ...);
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/* Get/set a pc value. */
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/* Get/set a pc value. */
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#define CPU_PC_GET(cpu) ((* CPU_PC_FETCH (cpu)) (cpu))
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#define CPU_PC_GET(cpu) ((* CPU_PC_FETCH (cpu)) (cpu))
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#define CPU_PC_SET(cpu,newval) ((* CPU_PC_STORE (cpu)) ((cpu), (newval)))
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#define CPU_PC_SET(cpu,newval) ((* CPU_PC_STORE (cpu)) ((cpu), (newval)))
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/* External interface to accessing the pc. */
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/* External interface to accessing the pc. */
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sim_cia sim_pc_get (sim_cpu *);
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sim_cia sim_pc_get (sim_cpu *);
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void sim_pc_set (sim_cpu *, sim_cia);
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void sim_pc_set (sim_cpu *, sim_cia);
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#endif /* SIM_CPU_H */
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#endif /* SIM_CPU_H */
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