# Test macro
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# Test macro
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.macro assert reg,value
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.macro assert reg,value
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cmpeq f0,\reg,\value
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cmpeq f0,\reg,\value
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bra/fx fail
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bra/fx fail
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.endm
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.endm
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# PR 15964 - a.s
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# PR 15964 - a.s
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add r8,r0,0x7fff7fff ;
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add r8,r0,0x7fff7fff ;
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add r9,r0,0x55555555 ;
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add r9,r0,0x55555555 ;
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add r12,r0,0x11111111 ;
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add r12,r0,0x11111111 ;
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add r1,r0,0x80000011 ; for psw
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add r1,r0,0x80000011 ; for psw
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mvtsys psw,r1 ||nop
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mvtsys psw,r1 ||nop
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addhhhh r12,r8,r9 ||addhlll r13,r12,r12
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addhhhh r12,r8,r9 ||addhlll r13,r12,r12
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mvfsys r20,psw ||nop
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mvfsys r20,psw ||nop
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mvtsys psw,r1 || add r2,r8, r9
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mvtsys psw,r1 || add r2,r8, r9
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mvfsys r21,psw ||nop
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mvfsys r21,psw ||nop
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assert r20, 0x80000000
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assert r20, 0x80000000
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assert r21, 0x80000014
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assert r21, 0x80000014
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# PR 15964 - b.s
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# PR 15964 - b.s
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add r40,r0,0x7fffffff
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add r40,r0,0x7fffffff
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add r41,r0,0x7fffffff
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add r41,r0,0x7fffffff
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add r1,r0,0x80000000 ; for psw
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add r1,r0,0x80000000 ; for psw
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mvtsys psw,r1,||nop
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mvtsys psw,r1,||nop
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cmpeq f1,r40,r41,||cmpeq f0,r40,r41,;
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cmpeq f1,r40,r41,||cmpeq f0,r40,r41,;
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mvfsys r42,psw
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mvfsys r42,psw
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assert r42, 0x80005000
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assert r42, 0x80005000
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# PR 16993 - a.s
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# PR 16993 - a.s
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add r8,r0,0x80005555 ; for psw
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add r8,r0,0x80005555 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r40,r0,0x11111111 ;
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add r40,r0,0x11111111 ;
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add r41,r0,0x22222222 ;
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add r41,r0,0x22222222 ;
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add r42,r0,0x00000000 ;
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add r42,r0,0x00000000 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||add r42,r40,r41,;
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mvtsys psw,r9 ||add r42,r40,r41,;
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mvfsys r10,psw
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mvfsys r10,psw
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assert r10, 0x80000000
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assert r10, 0x80000000
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# PR 16995 - b.s
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# PR 16995 - b.s
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add r8,r0,0x80000000 ; for psw
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add r8,r0,0x80000000 ; for psw
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add r9,r0,0x80005555 ; for psw
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add r9,r0,0x80005555 ; for psw
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add r10,r0,0x00000000 ;
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add r10,r0,0x00000000 ;
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add r40,r0,0x11111111 ;
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add r40,r0,0x11111111 ;
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add r41,r0,0x22222222 ;
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add r41,r0,0x22222222 ;
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add r42,r0,0x00000000 ;
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add r42,r0,0x00000000 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||add r42,r40,r41,;
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mvtsys psw,r9 ||add r42,r40,r41,;
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mvfsys r10,psw
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mvfsys r10,psw
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assert r10, 0x80005544
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assert r10, 0x80005544
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# PR 17006 - c.s
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# PR 17006 - c.s
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add r8,r0,0x80005555 ; for psw
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add r8,r0,0x80005555 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r10,r0,0x00000000 ;
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add r10,r0,0x00000000 ;
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add r40,r0,0x00000011 ;
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add r40,r0,0x00000011 ;
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add r41,r0,0x00000011 ;
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add r41,r0,0x00000011 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||cmpeq f5,r40,r41,;
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mvtsys psw,r9 ||cmpeq f5,r40,r41,;
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mvfsys r10,psw
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mvfsys r10,psw
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assert r10, 0x80000010
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assert r10, 0x80000010
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# PR 17006 - d.s
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# PR 17006 - d.s
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add r9,r0,0x80000000 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r40,r0,0x00000011 ;
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add r40,r0,0x00000011 ;
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add r41,r0,0x00000011 ;
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add r41,r0,0x00000011 ;
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nop ||nop
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nop ||nop
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mvtsys psw, r9 || nop
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mvtsys psw, r9 || nop
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nop ||nop
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nop ||nop
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nop ||cmpeq f5,r40,r41,;
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nop ||cmpeq f5,r40,r41,;
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mvfsys r10,psw
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mvfsys r10,psw
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assert r10, 0x80000010
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assert r10, 0x80000010
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# PR 17106 - a.s
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# PR 17106 - a.s
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; test 000 ; mvtsys(s=0) || sathl(s=0) prallel execution test
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; test 000 ; mvtsys(s=0) || sathl(s=0) prallel execution test
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add r8,r0,0x80005555 ; for psw
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add r8,r0,0x80005555 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r9,r0,0x80000000 ; for psw
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add r40,r0,0x00000044 ;
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add r40,r0,0x00000044 ;
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add r41,r0,0x00000008 ;
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add r41,r0,0x00000008 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||sathl r30,r40,r41,;
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mvtsys psw,r9 ||sathl r30,r40,r41,;
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mvfsys r20, psw ||nop
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mvfsys r20, psw ||nop
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;-------------------------------
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;-------------------------------
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; test 001 ; mvtsys(s=0) || sathl(s=1) prallel execution test
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; test 001 ; mvtsys(s=0) || sathl(s=1) prallel execution test
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_test_001:
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_test_001:
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add r40,r0,0x00004444 ;
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add r40,r0,0x00004444 ;
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add r41,r0,0x00000008 ;
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add r41,r0,0x00000008 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||sathl r31,r40,r41,;
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mvtsys psw,r9 ||sathl r31,r40,r41,;
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mvfsys r21,psw ||nop
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mvfsys r21,psw ||nop
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;-------------------------------
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;-------------------------------
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; test 002 ; mvtsys(s=1) || sathl(s=0) prallel execution test
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; test 002 ; mvtsys(s=1) || sathl(s=0) prallel execution test
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add r8,r0,0x80000000 ; for psw
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add r8,r0,0x80000000 ; for psw
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add r9,r0,0x80005555 ; for psw
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add r9,r0,0x80005555 ; for psw
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add r40,r0,0x00000044 ;
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add r40,r0,0x00000044 ;
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add r41,r0,0x00000008 ;
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add r41,r0,0x00000008 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||sathl r32,r40,r41,;
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mvtsys psw,r9 ||sathl r32,r40,r41,;
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mvfsys r22,psw ||nop
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mvfsys r22,psw ||nop
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;-------------------------------
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;-------------------------------
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; test 003 ; mvtsys(s=1) || sathl(s=1) prallel execution test
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; test 003 ; mvtsys(s=1) || sathl(s=1) prallel execution test
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; init-reg
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; init-reg
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add r40,r0,0x00004444 ;
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add r40,r0,0x00004444 ;
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add r41,r0,0x00000008 ;
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add r41,r0,0x00000008 ;
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mvtsys psw,r8 ||nop
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mvtsys psw,r8 ||nop
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mvtsys psw,r9 ||sathl r33,r40,r41,;
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mvtsys psw,r9 ||sathl r33,r40,r41,;
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mvfsys r23,psw ||nop
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mvfsys r23,psw ||nop
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assert r20, 0x80000000
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assert r20, 0x80000000
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assert r21, 0x80000040
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assert r21, 0x80000040
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assert r22, 0x80005555
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assert r22, 0x80005555
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assert r23, 0x80005515
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assert r23, 0x80005515
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# PR 18288 - a.s
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# PR 18288 - a.s
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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; mvtsys (C =1, V= VA = 0) || addc (C= V= VA =0)
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; mvtsys (C =1, V= VA = 0) || addc (C= V= VA =0)
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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test_000b:
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test_000b:
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add r1,r0,1 ||nop ; set C bit
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add r1,r0,1 ||nop ; set C bit
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||nop
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mvtsys psw r1 ||addc r20,r0,1
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mvtsys psw r1 ||addc r20,r0,1
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mvfsys r10,psw ||nop
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mvfsys r10,psw ||nop
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; C changed in MU is not used in IU.
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; C changed in MU is not used in IU.
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; IU prevail for resulting C.
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; IU prevail for resulting C.
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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; mvtsys (V =1, C = VA = 0) || add (C= V= VA =0)
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; mvtsys (V =1, C = VA = 0) || add (C= V= VA =0)
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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test_001b:
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test_001b:
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add r1,r0,0x10 ||nop ; set V bit
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add r1,r0,0x10 ||nop ; set V bit
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||nop
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mvtsys psw r1 ||add r0,r0,r0
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mvtsys psw r1 ||add r0,r0,r0
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mvfsys r11,psw ||nop
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mvfsys r11,psw ||nop
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; IU prevail for resulting V.
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; IU prevail for resulting V.
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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; mvtsys (V = C= VA = 0) || add (C=0,V= VA =1)
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; mvtsys (V = C= VA = 0) || add (C=0,V= VA =1)
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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test_002b:
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test_002b:
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add r1,r0,0x70000000
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add r1,r0,0x70000000
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add r2,r0,0x30000000
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add r2,r0,0x30000000
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||add r0,r1,r2
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mvtsys psw r0 ||add r0,r1,r2
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mvfsys r12,psw ||nop
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mvfsys r12,psw ||nop
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; IU prevail for resulting V.
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; IU prevail for resulting V.
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; VA is set(OR'ed)
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; VA is set(OR'ed)
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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; mvtsys (C= 0 V = VA = 1) || add (C= V= VA =0)
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; mvtsys (C= 0 V = VA = 1) || add (C= V= VA =0)
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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test_003b:
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test_003b:
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add r1,r0,0x14 ||nop ; set V and VA bit
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add r1,r0,0x14 ||nop ; set V and VA bit
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||nop
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mvtsys psw r1 ||add r0,r0,r0
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mvtsys psw r1 ||add r0,r0,r0
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mvfsys r13,psw ||nop
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mvfsys r13,psw ||nop
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; IU prevail for resulging V
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; IU prevail for resulging V
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; VA is set(OR'ed)
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; VA is set(OR'ed)
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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; mvtsys (f3 =1) || orfg (f3) : GROUP_B
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; mvtsys (f3 =1) || orfg (f3) : GROUP_B
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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test_004b:
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test_004b:
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add r1,r0,0x100 ; set f3
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add r1,r0,0x100 ; set f3
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||nop
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mvtsys psw,r1 ||orfg f3,f3,0
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mvtsys psw,r1 ||orfg f3,f3,0
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mvfsys r14,psw ||nop
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mvfsys r14,psw ||nop
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; results of IU prevail.
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; results of IU prevail.
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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; mvtsys (f4 =1) || sathp
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; mvtsys (f4 =1) || sathp
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;------------------------------------------------------------------------
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;------------------------------------------------------------------------
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test_005b:
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test_005b:
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add r1,r0,0x40 ; set f4
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add r1,r0,0x40 ; set f4
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mvtsys psw r0 ||nop
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mvtsys psw r0 ||nop
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mvtsys psw r1 ||sathl r2,r1,3
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mvtsys psw r1 ||sathl r2,r1,3
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mvfsys r15,psw ||nop
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mvfsys r15,psw ||nop
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; results of MU is used in IU
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; results of MU is used in IU
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assert r20, 0x1
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assert r20, 0x1
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assert r10, 0x0
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assert r10, 0x0
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assert r11, 0x0
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assert r11, 0x0
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assert r12, 0x14
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assert r12, 0x14
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assert r13, 0x4
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assert r13, 0x4
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assert r14, 0x0
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assert r14, 0x0
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assert r15, 0x0
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assert r15, 0x0
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# PR 18288 - b.s
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# PR 18288 - b.s
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add r7,r0,0x80000000
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add r7,r0,0x80000000
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mvtsys psw,r7 || nop
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mvtsys psw,r7 || nop
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add r8,r0,0x7fff7fff ;
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add r8,r0,0x7fff7fff ;
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add r9,r0,0x55555555 ;
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add r9,r0,0x55555555 ;
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add r12,r0,0x11111111 ;
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add r12,r0,0x11111111 ;
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add r13,r0,0x00000000 ;
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add r13,r0,0x00000000 ;
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addhhhh r12,r8,r9 ||addhlll r13,r12,r12
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addhhhh r12,r8,r9 ||addhlll r13,r12,r12
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mvfsys r60,psw ||nop
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mvfsys r60,psw ||nop
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;------------------------------------------
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;------------------------------------------
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add r20,r0,0x66666666 ;
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add r20,r0,0x66666666 ;
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add r21,r0,0x77777777 ;
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add r21,r0,0x77777777 ;
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add r40,r0,0x22222222 ;
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add r40,r0,0x22222222 ;
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add r41,r0,0x55555555 ;
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add r41,r0,0x55555555 ;
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add r22,r20,r21 ||add r42,r40,r41,;
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add r22,r20,r21 ||add r42,r40,r41,;
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mvfsys r61,psw ||nop
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mvfsys r61,psw ||nop
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assert r60, 0x80000000
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assert r60, 0x80000000
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assert r61, 0x80000000
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assert r61, 0x80000000
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# PR 19224
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# PR 19224
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add r7,r0,0x80000000
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add r7,r0,0x80000000
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add r2,r0,r0 || nop
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add r2,r0,r0 || nop
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add r1,r0,0x1 || nop
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add r1,r0,0x1 || nop
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# confirm that these insns do not kill the add in the right container
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# confirm that these insns do not kill the add in the right container
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mvtsys psw,r7 -> add r2,r2,r1
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mvtsys psw,r7 -> add r2,r2,r1
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mvtsys pswh,r7 -> add r2,r2,r1
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mvtsys pswh,r7 -> add r2,r2,r1
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mvtsys pswl,r7 -> add r2,r2,r1
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mvtsys pswl,r7 -> add r2,r2,r1
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mvtsys f0,r7 -> add r2,r2,r1
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mvtsys f0,r7 -> add r2,r2,r1
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mvtsys mod_s,r7 -> add r2,r2,r1
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mvtsys mod_s,r7 -> add r2,r2,r1
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assert r2, 0x5
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assert r2, 0x5
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# all okay
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# all okay
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bra ok
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bra ok
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ok:
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ok:
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add r2, r0, 0
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add r2, r0, 0
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.long 0x0e000004
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.long 0x0e000004
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nop
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nop
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fail:
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fail:
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add r2, r0, 47
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add r2, r0, 47
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.long 0x0e000004
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.long 0x0e000004
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nop
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nop
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