OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [arelease/] [rc203soc/] [syn/] [RAMB4_S16_S16.v] - Diff between revs 1328 and 1765

Only display areas with differences | Details | Blame | View Log

Rev 1328 Rev 1765
//
//
// Black boxes for 4kB caches
// Black boxes for 4kB caches
//
//
// This are black boxes to synthesize caches memories using
// This are black boxes to synthesize caches memories using
// distributed memories. 
// distributed memories. 
// To reduce area and improve timing it is strongly recommend to 
// To reduce area and improve timing it is strongly recommend to 
// use block RAM generated using Coregen
// use block RAM generated using Coregen
//
//
 
 
module RAMB4_S16_S16(
module RAMB4_S16_S16(
         CLKA,
         CLKA,
         RSTA,
         RSTA,
         ADDRA,
         ADDRA,
         DIA,
         DIA,
         ENA,
         ENA,
         WEA,
         WEA,
         DOA,
         DOA,
         CLKB,
         CLKB,
         RSTB,
         RSTB,
         ADDRB,
         ADDRB,
         DIB,
         DIB,
         ENB,
         ENB,
         WEB,
         WEB,
         DOB
         DOB
         );  //synthesis syn_black_box
         );  //synthesis syn_black_box
 
 
input CLKA;
input CLKA;
input RSTA;
input RSTA;
input [7:0] ADDRA;
input [7:0] ADDRA;
input [15:0] DIA;
input [15:0] DIA;
input ENA;
input ENA;
input WEA;
input WEA;
output [15:0] DOA;
output [15:0] DOA;
 
 
input CLKB;
input CLKB;
input RSTB;
input RSTB;
input [7:0] ADDRB;
input [7:0] ADDRB;
input [15:0] DIB;
input [15:0] DIB;
input ENB;
input ENB;
input WEB;
input WEB;
output [15:0] DOB;
output [15:0] DOB;
endmodule
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.