OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [final_interface/] [gdb-5.0/] [sim/] [w65/] [interp.c] - Diff between revs 114 and 1765

Only display areas with differences | Details | Blame | View Log

Rev 114 Rev 1765
/* Simulator for the WDC 65816 architecture.
/* Simulator for the WDC 65816 architecture.
 
 
   Written by Steve Chamberlain of Cygnus Support.
   Written by Steve Chamberlain of Cygnus Support.
   sac@cygnus.com
   sac@cygnus.com
 
 
   This file is part of W65 sim
   This file is part of W65 sim
 
 
 
 
                THIS SOFTWARE IS NOT COPYRIGHTED
                THIS SOFTWARE IS NOT COPYRIGHTED
 
 
   Cygnus offers the following for use in the public domain.  Cygnus
   Cygnus offers the following for use in the public domain.  Cygnus
   makes no warranty with regard to the software or it's performance
   makes no warranty with regard to the software or it's performance
   and the user accepts the software "AS IS" with all faults.
   and the user accepts the software "AS IS" with all faults.
 
 
   CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
   CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
   THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
 
*/
*/
 
 
#include "config.h"
#include "config.h"
 
 
#include <stdio.h>
#include <stdio.h>
#include <signal.h>
#include <signal.h>
#ifdef HAVE_STDLIB_H
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#include <stdlib.h>
#endif
#endif
#ifdef HAVE_TIME_H
#ifdef HAVE_TIME_H
#include <time.h>
#include <time.h>
#endif
#endif
#ifdef HAVE_UNISTD_H
#ifdef HAVE_UNISTD_H
#include <unistd.h>
#include <unistd.h>
#endif
#endif
#include <sys/param.h>
#include <sys/param.h>
#include "bfd.h"
#include "bfd.h"
#include "callback.h"
#include "callback.h"
#include "remote-sim.h"
#include "remote-sim.h"
#include "../../newlib/libc/sys/w65/sys/syscall.h"
#include "../../newlib/libc/sys/w65/sys/syscall.h"
 
 
#include "interp.h"
#include "interp.h"
 
 
saved_state_type saved_state;
saved_state_type saved_state;
 
 
int
int
get_now ()
get_now ()
{
{
  return time ((long *) 0);
  return time ((long *) 0);
}
}
void
void
control_c (sig, code, scp, addr)
control_c (sig, code, scp, addr)
     int sig;
     int sig;
     int code;
     int code;
     char *scp;
     char *scp;
     char *addr;
     char *addr;
{
{
  saved_state.exception = SIGINT;
  saved_state.exception = SIGINT;
}
}
 
 
wai ()
wai ()
{
{
  saved_state.exception = SIGTRAP;
  saved_state.exception = SIGTRAP;
}
}
 
 
 
 
 
 
wdm (acc, x)
wdm (acc, x)
     int acc;
     int acc;
     int x;
     int x;
 
 
{
{
int cycles;
int cycles;
  /* The x points to where the registers live, acc has code */
  /* The x points to where the registers live, acc has code */
 
 
#define R(arg)  (x +  arg * 2)
#define R(arg)  (x +  arg * 2)
unsigned  R0 = R(0);
unsigned  R0 = R(0);
unsigned  R4 = R(4);
unsigned  R4 = R(4);
unsigned  R5 = R(5);
unsigned  R5 = R(5);
unsigned  R6 = R(6);
unsigned  R6 = R(6);
unsigned  R7 = R(7);
unsigned  R7 = R(7);
unsigned  R8 = R(8);
unsigned  R8 = R(8);
unsigned char *memory = saved_state.memory;
unsigned char *memory = saved_state.memory;
  int a1 = fetch16 (R (4));
  int a1 = fetch16 (R (4));
  switch (a1)
  switch (a1)
    {
    {
    case SYS_write:
    case SYS_write:
      {
      {
        int file = fetch16 (R5);
        int file = fetch16 (R5);
        unsigned char *buf = fetch24 (R6) + memory;
        unsigned char *buf = fetch24 (R6) + memory;
        int len = fetch16 (R8);
        int len = fetch16 (R8);
        int res = write (file, buf, len);
        int res = write (file, buf, len);
        store16 (R0, res);
        store16 (R0, res);
        break;
        break;
      }
      }
    case 0:
    case 0:
      printf ("%c", acc);
      printf ("%c", acc);
      fflush (stdout);
      fflush (stdout);
      break;
      break;
    case 1:
    case 1:
      saved_state.exception = SIGTRAP;
      saved_state.exception = SIGTRAP;
      break;
      break;
    default:
    default:
      saved_state.exception = SIGILL;
      saved_state.exception = SIGILL;
      break;
      break;
    }
    }
}
}
 
 
 
 
void
void
sim_resume (step, insignal)
sim_resume (step, insignal)
     int step;
     int step;
     int insignal;
     int insignal;
{
{
  void (*prev) ();
  void (*prev) ();
  register unsigned char *memory;
  register unsigned char *memory;
  if (step)
  if (step)
    {
    {
      saved_state.exception = SIGTRAP;
      saved_state.exception = SIGTRAP;
    }
    }
  else
  else
    {
    {
      saved_state.exception = 0;
      saved_state.exception = 0;
    }
    }
 
 
 
 
  prev = signal (SIGINT, control_c);
  prev = signal (SIGINT, control_c);
  do
  do
    {
    {
      int x = (saved_state.p >> 4) & 1;
      int x = (saved_state.p >> 4) & 1;
      int m = (saved_state.p >> 5) & 1;
      int m = (saved_state.p >> 5) & 1;
      if (x == 0 && m == 0)
      if (x == 0 && m == 0)
        {
        {
          ifunc_X0_M0 ();
          ifunc_X0_M0 ();
        }
        }
      else if (x == 0 && m == 1)
      else if (x == 0 && m == 1)
        {
        {
          ifunc_X0_M1 ();
          ifunc_X0_M1 ();
        }
        }
      else if (x == 1 && m == 0)
      else if (x == 1 && m == 0)
        {
        {
          ifunc_X1_M0 ();
          ifunc_X1_M0 ();
        }
        }
      else if (x == 1 && m == 1)
      else if (x == 1 && m == 1)
        {
        {
          ifunc_X1_M1 ();
          ifunc_X1_M1 ();
        }
        }
    }
    }
  while (saved_state.exception == 0);
  while (saved_state.exception == 0);
 
 
  signal (SIGINT, prev);
  signal (SIGINT, prev);
}
}
 
 
 
 
 
 
 
 
init_pointers ()
init_pointers ()
{
{
  if (!saved_state.memory)
  if (!saved_state.memory)
    {
    {
      saved_state.memory = calloc (64 * 1024, NUMSEGS);
      saved_state.memory = calloc (64 * 1024, NUMSEGS);
    }
    }
}
}
 
 
int
int
sim_write (addr, buffer, size)
sim_write (addr, buffer, size)
     SIM_ADDR addr;
     SIM_ADDR addr;
     unsigned char *buffer;
     unsigned char *buffer;
     int size;
     int size;
{
{
  int i;
  int i;
  init_pointers ();
  init_pointers ();
 
 
  for (i = 0; i < size; i++)
  for (i = 0; i < size; i++)
    {
    {
      saved_state.memory[(addr + i) & MMASK] = buffer[i];
      saved_state.memory[(addr + i) & MMASK] = buffer[i];
    }
    }
  return size;
  return size;
}
}
 
 
int
int
sim_read (addr, buffer, size)
sim_read (addr, buffer, size)
     SIM_ADDR addr;
     SIM_ADDR addr;
     unsigned char *buffer;
     unsigned char *buffer;
     int size;
     int size;
{
{
  int i;
  int i;
 
 
  init_pointers ();
  init_pointers ();
 
 
  for (i = 0; i < size; i++)
  for (i = 0; i < size; i++)
    {
    {
      buffer[i] = saved_state.memory[(addr + i) & MMASK];
      buffer[i] = saved_state.memory[(addr + i) & MMASK];
    }
    }
  return size;
  return size;
}
}
 
 
 
 
 
 
struct
struct
{
{
  unsigned int *ptr;
  unsigned int *ptr;
  int size;
  int size;
}
}
rinfo[] =
rinfo[] =
 
 
{
{
  &saved_state.r[0], 2,
  &saved_state.r[0], 2,
  &saved_state.r[1], 2,
  &saved_state.r[1], 2,
  &saved_state.r[2], 2,
  &saved_state.r[2], 2,
  &saved_state.r[3], 2,
  &saved_state.r[3], 2,
  &saved_state.r[4], 2,
  &saved_state.r[4], 2,
  &saved_state.r[5], 2,
  &saved_state.r[5], 2,
  &saved_state.r[6], 2,
  &saved_state.r[6], 2,
  &saved_state.r[7], 2,
  &saved_state.r[7], 2,
  &saved_state.r[8], 2,
  &saved_state.r[8], 2,
  &saved_state.r[9], 2,
  &saved_state.r[9], 2,
  &saved_state.r[10], 2,
  &saved_state.r[10], 2,
  &saved_state.r[11], 2,
  &saved_state.r[11], 2,
  &saved_state.r[12], 2,
  &saved_state.r[12], 2,
  &saved_state.r[13], 2,
  &saved_state.r[13], 2,
  &saved_state.r[14], 2,
  &saved_state.r[14], 2,
  &saved_state.r[15], 4,
  &saved_state.r[15], 4,
  &saved_state.pc, 4,
  &saved_state.pc, 4,
  &saved_state.a, 4,
  &saved_state.a, 4,
  &saved_state.x, 4,
  &saved_state.x, 4,
  &saved_state.y, 4,
  &saved_state.y, 4,
  &saved_state.dbr, 4,
  &saved_state.dbr, 4,
  &saved_state.d, 4,
  &saved_state.d, 4,
  &saved_state.s, 4,
  &saved_state.s, 4,
  &saved_state.p, 4,
  &saved_state.p, 4,
  &saved_state.ticks, 4,
  &saved_state.ticks, 4,
  &saved_state.cycles, 4,
  &saved_state.cycles, 4,
  &saved_state.insts, 4,
  &saved_state.insts, 4,
  0
  0
};
};
 
 
int
int
sim_store_register (rn, value, length)
sim_store_register (rn, value, length)
     int rn;
     int rn;
     unsigned char *value;
     unsigned char *value;
     int length;
     int length;
{
{
  unsigned int val;
  unsigned int val;
  int i;
  int i;
  val = 0;
  val = 0;
  for (i = 0; i < rinfo[rn].size; i++)
  for (i = 0; i < rinfo[rn].size; i++)
    {
    {
      val |= (*value++) << (i * 8);
      val |= (*value++) << (i * 8);
    }
    }
 
 
  *(rinfo[rn].ptr) = val;
  *(rinfo[rn].ptr) = val;
  return -1;
  return -1;
}
}
 
 
int
int
sim_fetch_register (rn, buf, length)
sim_fetch_register (rn, buf, length)
     int rn;
     int rn;
     unsigned char *buf;
     unsigned char *buf;
     int length;
     int length;
{
{
  unsigned int val = *(rinfo[rn].ptr);
  unsigned int val = *(rinfo[rn].ptr);
  int i;
  int i;
 
 
  for (i = 0; i < rinfo[rn].size; i++)
  for (i = 0; i < rinfo[rn].size; i++)
    {
    {
      *buf++ = val;
      *buf++ = val;
      val = val >> 8;
      val = val >> 8;
    }
    }
  return -1;
  return -1;
}
}
 
 
 
 
sim_reg_size (n)
sim_reg_size (n)
{
{
  return rinfo[n].size;
  return rinfo[n].size;
}
}
int
int
sim_trace ()
sim_trace ()
{
{
  return 0;
  return 0;
}
}
 
 
void
void
sim_stop_reason (reason, sigrc)
sim_stop_reason (reason, sigrc)
     enum sim_stop *reason;
     enum sim_stop *reason;
     int *sigrc;
     int *sigrc;
{
{
  *reason = sim_stopped;
  *reason = sim_stopped;
  *sigrc = saved_state.exception;
  *sigrc = saved_state.exception;
}
}
 
 
int
int
sim_set_pc (x)
sim_set_pc (x)
     SIM_ADDR x;
     SIM_ADDR x;
{
{
  saved_state.pc = x;
  saved_state.pc = x;
  return 0;
  return 0;
}
}
 
 
 
 
void
void
sim_info (verbose)
sim_info (verbose)
     int verbose;
     int verbose;
{
{
  double timetaken = (double) saved_state.ticks;
  double timetaken = (double) saved_state.ticks;
  double virttime = saved_state.cycles / 2.0e6;
  double virttime = saved_state.cycles / 2.0e6;
 
 
  printf ("\n\n# instructions executed  %10d\n", saved_state.insts);
  printf ("\n\n# instructions executed  %10d\n", saved_state.insts);
  printf ("# cycles                 %10d\n", saved_state.cycles);
  printf ("# cycles                 %10d\n", saved_state.cycles);
  printf ("# real time taken        %10.4f\n", timetaken);
  printf ("# real time taken        %10.4f\n", timetaken);
  printf ("# virtual time taken     %10.4f\n", virttime);
  printf ("# virtual time taken     %10.4f\n", virttime);
 
 
  if (timetaken != 0)
  if (timetaken != 0)
    {
    {
      printf ("# cycles/second          %10d\n", (int) (saved_state.cycles / timetaken));
      printf ("# cycles/second          %10d\n", (int) (saved_state.cycles / timetaken));
      printf ("# simulation ratio       %10.4f\n", virttime / timetaken);
      printf ("# simulation ratio       %10.4f\n", virttime / timetaken);
    }
    }
 
 
}
}
 
 
 
 
 
 
void
void
sim_open (kind, cb, abfd, argv)
sim_open (kind, cb, abfd, argv)
     SIM_OPEN_KIND kind;
     SIM_OPEN_KIND kind;
     host_callback *cb;
     host_callback *cb;
     struct _bfd *abfd;
     struct _bfd *abfd;
     char **argv;
     char **argv;
{
{
}
}
 
 
 
 
 
 
#undef fetch8
#undef fetch8
fetch8func (x)
fetch8func (x)
{
{
  if (x & ~MMASK)
  if (x & ~MMASK)
    {
    {
      saved_state.exception = SIGBUS;
      saved_state.exception = SIGBUS;
      return 0;
      return 0;
    }
    }
  return saved_state.memory[x];
  return saved_state.memory[x];
}
}
 
 
fetch8 (x)
fetch8 (x)
{
{
return fetch8func(x);
return fetch8func(x);
}
}
 
 
void
void
sim_close (quitting)
sim_close (quitting)
     int quitting;
     int quitting;
{
{
  /* nothing to do */
  /* nothing to do */
}
}
 
 
int
int
sim_load (prog, from_tty)
sim_load (prog, from_tty)
     char *prog;
     char *prog;
     int from_tty;
     int from_tty;
{
{
  /* Return nonzero so gdb will handle it.  */
  /* Return nonzero so gdb will handle it.  */
  return 1;
  return 1;
}
}
 
 
 
 
void
void
sim_create_inferior (abfd, argv, env)
sim_create_inferior (abfd, argv, env)
     struct _bfd *abfd;
     struct _bfd *abfd;
     char **argv;
     char **argv;
     char **env;
     char **env;
{
{
  SIM_ADDR start_address;
  SIM_ADDR start_address;
  int pc;
  int pc;
  if (abfd != NULL)
  if (abfd != NULL)
    start_address = bfd_get_start_address (abfd);
    start_address = bfd_get_start_address (abfd);
  else
  else
    start_address = 0; /*??*/
    start_address = 0; /*??*/
  /* ??? We assume this is a 4 byte quantity.  */
  /* ??? We assume this is a 4 byte quantity.  */
  pc = start_address;
  pc = start_address;
  sim_store_register (16, (unsigned char *) &pc);
  sim_store_register (16, (unsigned char *) &pc);
}
}
 
 
void
void
sim_set_callbacks (ptr)
sim_set_callbacks (ptr)
struct host_callback_struct *ptr;
struct host_callback_struct *ptr;
{
{
 
 
}
}
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.