//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's simulation monitor ////
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//// OR1200's simulation monitor ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Simulation monitor ////
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//// Simulation monitor ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - move it to bench ////
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//// - move it to bench ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Revision 1.1 2001/08/20 18:17:52 damjan
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// Initial revision
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// Initial revision
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//
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//
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Revision 1.1 2001/08/13 03:37:07 lampret
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// Added monitor.v and timescale.v
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// Added monitor.v and timescale.v
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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`include "defines.v"
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`include "defines.v"
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// Enable debug_mem task. Only affects simulation.
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// Enable debug_mem task. Only affects simulation.
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`define enable_debug_mem
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`define enable_debug_mem
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// Enable display_arch_state task. Only affects simulation.
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// Enable display_arch_state task. Only affects simulation.
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`define enable_display_arch_state
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`define enable_display_arch_state
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module or1200_monitor;
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module or1200_monitor;
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task monitortask;
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task monitortask;
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begin
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begin
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end
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end
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endtask
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endtask
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integer fexe;
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integer fexe;
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reg [23:0] ref;
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reg [23:0] ref;
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initial begin
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initial begin
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ref = 0;
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ref = 0;
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fexe = $fopen("executed.log");
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fexe = $fopen("executed.log");
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$timeformat (-9, 2, " ns", 12);
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$timeformat (-9, 2, " ns", 12);
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end
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end
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task finish_simulation;
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task finish_simulation;
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begin
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begin
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$fclose(fexe);
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$fclose(fexe);
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display_arch_state;
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display_arch_state;
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display_memory(0, 8191);
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display_memory(0, 8191);
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$shm_save;
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$shm_save;
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$shm_close;
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$shm_close;
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$dumpflush;
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$dumpflush;
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$finish;
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$finish;
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end
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end
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endtask
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endtask
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task caught_sys203;
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task caught_sys203;
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begin
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begin
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$display("simulation terminated due to l.sys 203");
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$display("simulation terminated due to l.sys 203");
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finish_simulation;
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finish_simulation;
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end
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end
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endtask
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endtask
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task display_arch_state;
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task display_arch_state;
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reg [5:0] i;
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reg [5:0] i;
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reg [31:0] r;
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reg [31:0] r;
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integer j;
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integer j;
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begin
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begin
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`ifdef enable_display_arch_state
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`ifdef enable_display_arch_state
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ref = ref + 1;
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ref = ref + 1;
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// if (ref == 17890) begin
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// if (ref == 17890) begin
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// $dumpfile("dump.vcd");
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// $dumpfile("dump.vcd");
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// $dumpvars(20,tb_or1200);
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// $dumpvars(20,tb_or1200);
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// end
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// end
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$fwrite(fexe, "\nEXECUTED(): %h: %h", xess_top.i_xess_fpga.risc.cpu.except.wb_pc, xess_top.i_xess_fpga.risc.cpu.id.wb_insn);
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$fwrite(fexe, "\nEXECUTED(): %h: %h", xess_top.i_xess_fpga.risc.cpu.except.wb_pc, xess_top.i_xess_fpga.risc.cpu.id.wb_insn);
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for(i = 0; i < 32; i = i + 1) begin
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for(i = 0; i < 32; i = i + 1) begin
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if (i % 4 == 0)
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if (i % 4 == 0)
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$fdisplay(fexe);
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$fdisplay(fexe);
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`ifdef XILINX_RAMB4
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`ifdef XILINX_RAMB4
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r = 32'h0000_0000;
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r = 32'h0000_0000;
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for(j = 0; j < 16; j = j + 1) begin
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for(j = 0; j < 16; j = j + 1) begin
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r[j] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_0.mem[i*16+j];
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r[j] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_0.mem[i*16+j];
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end
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end
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for(j = 0; j < 16; j = j + 1) begin
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for(j = 0; j < 16; j = j + 1) begin
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r[j+16] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_1.mem[i*16+j];
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r[j+16] = xess_top.i_xess_fpga.risc.cpu.rf.rf_a.ramb4_s16_1.mem[i*16+j];
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end
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end
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$fwrite(fexe, "GPR%d: %h ", i, r);
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$fwrite(fexe, "GPR%d: %h ", i, r);
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`else
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`else
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`ifdef XILINX_RAM32X1D
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`ifdef XILINX_RAM32X1D
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`else
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`else
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`ifdef ARTISAN_SDP
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`ifdef ARTISAN_SDP
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`else
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`else
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$fwrite(fexe, "GPR%d: %h ", i, xess_top.i_xess_fpga.risc.cpu.rf.rf_a.mem[i]);
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$fwrite(fexe, "GPR%d: %h ", i, xess_top.i_xess_fpga.risc.cpu.rf.rf_a.mem[i]);
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`endif
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`endif
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`endif
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`endif
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`endif
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`endif
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end
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end
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$fdisplay(fexe);
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$fdisplay(fexe);
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r = xess_top.i_xess_fpga.risc.cpu.sprs.sr;
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r = xess_top.i_xess_fpga.risc.cpu.sprs.sr;
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$fwrite(fexe, "SR : %h ", r);
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$fwrite(fexe, "SR : %h ", r);
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r = xess_top.i_xess_fpga.risc.cpu.sprs.epcr;
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r = xess_top.i_xess_fpga.risc.cpu.sprs.epcr;
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$fwrite(fexe, "EPCR0: %h ", r);
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$fwrite(fexe, "EPCR0: %h ", r);
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r = xess_top.i_xess_fpga.risc.cpu.sprs.eear;
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r = xess_top.i_xess_fpga.risc.cpu.sprs.eear;
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$fwrite(fexe, "EEAR0: %h ", r);
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$fwrite(fexe, "EEAR0: %h ", r);
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r = xess_top.i_xess_fpga.risc.cpu.sprs.esr;
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r = xess_top.i_xess_fpga.risc.cpu.sprs.esr;
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$fdisplay(fexe, "ESR0 : %h", r);
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$fdisplay(fexe, "ESR0 : %h", r);
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// $fdisplay(fexe);
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// $fdisplay(fexe);
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`endif
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`endif
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end
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end
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endtask
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endtask
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task display_memory;
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task display_memory;
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input [31:0] from;
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input [31:0] from;
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input [31:0] to;
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input [31:0] to;
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integer i;
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integer i;
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begin
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begin
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// for(i = from; i < to; i = i + 4)
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// for(i = from; i < to; i = i + 4)
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// $display("mem[%h] = %h mem[%h] = %h mem[%h] = %h mem[%h] = %h ",
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// $display("mem[%h] = %h mem[%h] = %h mem[%h] = %h mem[%h] = %h ",
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// i, sram2.ramCore[i], i+4, sram2.ramCore[i+1], i+8, sram2.ramCore[i+2], i+12, sram2.ramCore[i+3]); //zSramX32
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// i, sram2.ramCore[i], i+4, sram2.ramCore[i+1], i+8, sram2.ramCore[i+2], i+12, sram2.ramCore[i+3]); //zSramX32
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// i<<2, sram2.mem[i], (i<<2)+4, sram2.mem[i+1], (i<<2)+8, sram2.mem[i+2], (i<<2)+12, sram2.mem[i+3]); //sram32kx32
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// i<<2, sram2.mem[i], (i<<2)+4, sram2.mem[i+1], (i<<2)+8, sram2.mem[i+2], (i<<2)+12, sram2.mem[i+3]); //sram32kx32
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end
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end
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endtask
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endtask
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task debug_mem;
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task debug_mem;
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input [79:0] device;
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input [79:0] device;
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input write;
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input write;
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input [31:0] addr;
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input [31:0] addr;
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input [31:0] data;
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input [31:0] data;
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input [3:0] bs;
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input [3:0] bs;
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begin
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begin
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`ifdef enable_debug_mem
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`ifdef enable_debug_mem
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if (write)
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if (write)
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$display( "%t: WRITE to %s addr 0x%h with a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
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$display( "%t: WRITE to %s addr 0x%h with a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
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else
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else
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$display( "%t: READ from %s addr 0x%h which contains a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
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$display( "%t: READ from %s addr 0x%h which contains a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs);
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`endif
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`endif
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end
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end
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endtask
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endtask
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always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
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always @(posedge xess_top.i_xess_fpga.risc.cpu.id.clk)
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if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
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if (!xess_top.i_xess_fpga.risc.cpu.id.wb_freeze) begin
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#2;
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#2;
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if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
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if ((xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h1500ffff) && (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14000000)
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&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444))
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&& (xess_top.i_xess_fpga.risc.cpu.id.wb_insn != 32'h14004444))
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display_arch_state;
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display_arch_state;
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if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
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if (xess_top.i_xess_fpga.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203)
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caught_sys203;
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caught_sys203;
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end
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end
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endmodule
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endmodule
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