URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
Rev 769 |
Rev 1765 |
/* Enable Verilog HDL preprocessor */
|
/* Enable Verilog HDL preprocessor */
|
hdlin_enable_vpp = true
|
hdlin_enable_vpp = true
|
|
|
/* Set log path */
|
/* Set log path */
|
LOG_PATH = "../log/"
|
LOG_PATH = "../log/"
|
|
|
/* Set gate-level netlist path */
|
/* Set gate-level netlist path */
|
GATE_PATH = "../out/"
|
GATE_PATH = "../out/"
|
|
|
/* Set RAMS_PATH */
|
/* Set RAMS_PATH */
|
RAMS_PATH = "../../../lib/"
|
RAMS_PATH = "../../../lib/"
|
|
|
/* Set RTL source path */
|
/* Set RTL source path */
|
RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \
|
RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \
|
"../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \
|
"../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \
|
"../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" }
|
"../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" }
|
|
|
/* Optimize adders */
|
/* Optimize adders */
|
synlib_model_map_effort = high
|
synlib_model_map_effort = high
|
hlo_share_effort = medium
|
hlo_share_effort = medium
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.