#include "spr_defs.h"
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#include "spr_defs.h"
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#include "board.h"
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#include "board.h"
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#include "mc.h"
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#include "mc.h"
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.extern _reset_support
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.extern _reset_support
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.extern _eth_int
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.extern _eth_int
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.extern _src_beg
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.extern _src_beg
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.extern _dst_beg
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.extern _dst_beg
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.extern _dst_end
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.extern _dst_end
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.extern _c_reset
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.extern _c_reset
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.extern _int_main
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.extern _int_main
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.global _lolev_ie
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.global _lolev_ie
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.global _lolev_idis
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.global _lolev_idis
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.section .stack, "aw", @nobits
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.section .stack, "aw", @nobits
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.space STACK_SIZE
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.space STACK_SIZE
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_stack:
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_stack:
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.if IN_FLASH
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.if IN_FLASH
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.section .reset, "ax"
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.section .reset, "ax"
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.else
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.else
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.section .vectors, "ax"
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.section .vectors, "ax"
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.endif
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.endif
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.org 0x100
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.org 0x100
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_reset:
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_reset:
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.if IN_FLASH
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.if IN_FLASH
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l.movhi r3,hi(MC_BASE_ADD)
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l.movhi r3,hi(MC_BASE_ADD)
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l.ori r3,r3,MC_BA_MASK
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l.ori r3,r3,MC_BA_MASK
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l.addi r5,r0,0x00
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l.addi r5,r0,0x00
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l.sw 0(r3),r5
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l.sw 0(r3),r5
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.endif
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.endif
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l.movhi r3,hi(_start)
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l.movhi r3,hi(_start)
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l.ori r3,r3,lo(_start)
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l.ori r3,r3,lo(_start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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.if IN_FLASH
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.if IN_FLASH
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.section .vectors, "ax"
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.section .vectors, "ax"
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.endif
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.endif
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.org 0x800
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.org 0x800
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l.j _int_wrapper
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l.j _int_wrapper
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l.nop
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l.nop
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.section .text
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.section .text
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_start:
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_start:
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.if IN_FLASH
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.if IN_FLASH
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l.jal _init_mc
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l.jal _init_mc
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l.nop
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l.nop
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/* Wait for SDRAM */
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/* Wait for SDRAM */
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l.addi r3,r0,0x0000 /* igor zmanjsal iz 0x7fff na 0x0000 */
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l.addi r3,r0,0x0000 /* igor zmanjsal iz 0x7fff na 0x0000 */
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1: l.sfeqi r3,0
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1: l.sfeqi r3,0
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l.bnf 1b
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l.bnf 1b
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l.addi r3,r3,-1
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l.addi r3,r3,-1
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.endif
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.endif
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/* Copy form flash to sram */
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/* Copy form flash to sram */
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.if IN_FLASH
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.if IN_FLASH
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l.movhi r3,hi(_src_beg)
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l.movhi r3,hi(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.movhi r4,hi(_vec_start)
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l.movhi r4,hi(_vec_start)
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l.ori r4,r4,lo(_vec_start)
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l.ori r4,r4,lo(_vec_start)
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l.movhi r5,hi(_vec_end)
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l.movhi r5,hi(_vec_end)
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l.ori r5,r5,lo(_vec_end)
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l.ori r5,r5,lo(_vec_end)
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l.sub r5,r5,r4
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l.sub r5,r5,r4
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l.sfeqi r5,0
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l.sfeqi r5,0
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l.bf 2f
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l.bf 2f
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l.nop
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l.nop
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1: l.lwz r6,0(r3)
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1: l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.sfgtsi r5,0
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l.bf 1b
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l.bf 1b
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l.nop
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l.nop
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2:
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2:
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l.movhi r4,hi(_dst_beg)
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l.movhi r4,hi(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.movhi r5,hi(_dst_end)
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l.movhi r5,hi(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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1: l.sfgeu r4,r5
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1: l.sfgeu r4,r5
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l.bf 1f
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l.bf 1f
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l.nop
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l.nop
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l.lwz r8,0(r3)
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l.lwz r8,0(r3)
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l.sw 0(r4),r8
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l.sw 0(r4),r8
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l.addi r3,r3,4
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l.addi r3,r3,4
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l.bnf 1b
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l.bnf 1b
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l.addi r4,r4,4
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l.addi r4,r4,4
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1:
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1:
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l.addi r3,r0,0
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l.addi r3,r0,0
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l.addi r4,r0,0
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l.addi r4,r0,0
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3:
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3:
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.endif
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.endif
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.if IC_ENABLE
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.if IC_ENABLE
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l.jal _ic_enable
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l.jal _ic_enable
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l.nop
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l.nop
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.endif
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.endif
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.if DC_ENABLE
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.if DC_ENABLE
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l.jal _dc_enable
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l.jal _dc_enable
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l.nop
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l.nop
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.endif
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.endif
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l.movhi r1,hi(_stack-4)
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l.movhi r1,hi(_stack-4)
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l.addi r1,r1,lo(_stack-4)
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l.addi r1,r1,lo(_stack-4)
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l.addi r2,r0,-3
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l.addi r2,r0,-3
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l.and r1,r1,r2
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l.and r1,r1,r2
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l.movhi r2,hi(_main)
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l.movhi r2,hi(_main)
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l.ori r2,r2,lo(_main)
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l.ori r2,r2,lo(_main)
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l.jr r2
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l.jr r2
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l.addi r2,r0,0
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l.addi r2,r0,0
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_ic_enable:
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_ic_enable:
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/* Flush IC */
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/* Flush IC */
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l.addi r10,r0,0
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l.addi r10,r0,0
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l.addi r11,r0,IC_SIZE
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l.addi r11,r0,IC_SIZE
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1:
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1:
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l.mtspr r0,r10,SPR_ICBIR
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l.mtspr r0,r10,SPR_ICBIR
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l.sfne r10,r11
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l.sfne r10,r11
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l.bf 1b
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l.bf 1b
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l.addi r10,r10,16
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l.addi r10,r10,16
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/* Enable IC */
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/* Enable IC */
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l.addi r10,r0,(SPR_SR_ICE|SPR_SR_SM)
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l.addi r10,r0,(SPR_SR_ICE|SPR_SR_SM)
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l.mtspr r0,r10,SPR_SR
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l.mtspr r0,r10,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_enable:
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_dc_enable:
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/* Flush DC */
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/* Flush DC */
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l.addi r10,r0,0
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l.addi r10,r0,0
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l.addi r11,r0,DC_SIZE
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l.addi r11,r0,DC_SIZE
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1:
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1:
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l.mtspr r0,r10,SPR_DCBIR
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l.mtspr r0,r10,SPR_DCBIR
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l.sfne r10,r11
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l.sfne r10,r11
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l.bf 1b
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l.bf 1b
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l.addi r10,r10,16
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l.addi r10,r10,16
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/* Enable DC */
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/* Enable DC */
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l.addi r10,r0,(SPR_SR_DCE|SPR_SR_SM)
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l.addi r10,r0,(SPR_SR_DCE|SPR_SR_SM)
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l.mtspr r0,r10,SPR_SR
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l.mtspr r0,r10,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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.if IN_FLASH
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.if IN_FLASH
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_init_mc:
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_init_mc:
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l.movhi r3,hi(MC_BASE_ADD)
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l.movhi r3,hi(MC_BASE_ADD)
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l.ori r3,r3,lo(MC_BASE_ADD)
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l.ori r3,r3,lo(MC_BASE_ADD)
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l.addi r4,r3,MC_CSC(0)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADD)
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l.movhi r5,hi(FLASH_BASE_ADD)
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l.srai r5,r5,5
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l.srai r5,r5,5
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l.ori r5,r5,0x0025
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(0)
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_BA_MASK
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSR
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(1)
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSC(1)
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADD)
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l.movhi r5,hi(SDRAM_BASE_ADD)
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l.srai r5,r5,5
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l.srai r5,r5,5
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l.ori r5,r5,0x0411
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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.endif
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.endif
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_int_wrapper:
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_int_wrapper:
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l.addi r1,r1,-128
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l.addi r1,r1,-128
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l.sw 0x4(r1),r2
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l.sw 0x4(r1),r2
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l.sw 0x8(r1),r4
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l.sw 0x8(r1),r4
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l.sw 0xc(r1),r5
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l.sw 0xc(r1),r5
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l.sw 0x10(r1),r6
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l.sw 0x10(r1),r6
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l.sw 0x14(r1),r7
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l.sw 0x14(r1),r7
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l.sw 0x18(r1),r8
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l.sw 0x18(r1),r8
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l.sw 0x1c(r1),r9
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l.sw 0x1c(r1),r9
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l.sw 0x20(r1),r10
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l.sw 0x20(r1),r10
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l.sw 0x24(r1),r11
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l.sw 0x24(r1),r11
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l.sw 0x28(r1),r12
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l.sw 0x28(r1),r12
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l.sw 0x2c(r1),r13
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l.sw 0x2c(r1),r13
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l.sw 0x30(r1),r14
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l.sw 0x30(r1),r14
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l.sw 0x34(r1),r15
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l.sw 0x34(r1),r15
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l.sw 0x38(r1),r16
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l.sw 0x38(r1),r16
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l.sw 0x3c(r1),r17
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l.sw 0x3c(r1),r17
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l.sw 0x40(r1),r18
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l.sw 0x40(r1),r18
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l.sw 0x44(r1),r19
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l.sw 0x44(r1),r19
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l.sw 0x48(r1),r20
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l.sw 0x48(r1),r20
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l.sw 0x4c(r1),r21
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l.sw 0x4c(r1),r21
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l.sw 0x50(r1),r22
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l.sw 0x50(r1),r22
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l.sw 0x54(r1),r23
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l.sw 0x54(r1),r23
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l.sw 0x58(r1),r24
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l.sw 0x58(r1),r24
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l.sw 0x5c(r1),r25
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l.sw 0x5c(r1),r25
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l.sw 0x60(r1),r26
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l.sw 0x60(r1),r26
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l.sw 0x64(r1),r27
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l.sw 0x64(r1),r27
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l.sw 0x68(r1),r28
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l.sw 0x68(r1),r28
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l.sw 0x6c(r1),r29
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l.sw 0x6c(r1),r29
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l.sw 0x70(r1),r30
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l.sw 0x70(r1),r30
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l.sw 0x74(r1),r31
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l.sw 0x74(r1),r31
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l.sw 0x78(r1),r3
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l.sw 0x78(r1),r3
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l.movhi r3,hi(_eth_int)
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l.movhi r3,hi(_eth_int)
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l.ori r3,r3,lo(_eth_int)
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l.ori r3,r3,lo(_eth_int)
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l.jalr r3
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l.jalr r3
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l.nop
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l.nop
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l.lwz r2,0x4(r1)
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l.lwz r2,0x4(r1)
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l.lwz r4,0x8(r1)
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l.lwz r4,0x8(r1)
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l.lwz r5,0xc(r1)
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l.lwz r5,0xc(r1)
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l.lwz r6,0x10(r1)
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l.lwz r6,0x10(r1)
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l.lwz r7,0x14(r1)
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l.lwz r7,0x14(r1)
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l.lwz r8,0x18(r1)
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l.lwz r8,0x18(r1)
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l.lwz r9,0x1c(r1)
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l.lwz r9,0x1c(r1)
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l.lwz r10,0x20(r1)
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l.lwz r10,0x20(r1)
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l.lwz r11,0x24(r1)
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l.lwz r11,0x24(r1)
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l.lwz r12,0x28(r1)
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l.lwz r12,0x28(r1)
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l.lwz r13,0x2c(r1)
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l.lwz r13,0x2c(r1)
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l.lwz r14,0x30(r1)
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l.lwz r14,0x30(r1)
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l.lwz r15,0x34(r1)
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l.lwz r15,0x34(r1)
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l.lwz r16,0x38(r1)
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l.lwz r16,0x38(r1)
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l.lwz r17,0x3c(r1)
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l.lwz r17,0x3c(r1)
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l.lwz r18,0x40(r1)
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l.lwz r18,0x40(r1)
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l.lwz r19,0x44(r1)
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l.lwz r19,0x44(r1)
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l.lwz r20,0x48(r1)
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l.lwz r20,0x48(r1)
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l.lwz r21,0x4c(r1)
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l.lwz r21,0x4c(r1)
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l.lwz r22,0x50(r1)
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l.lwz r22,0x50(r1)
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l.lwz r23,0x54(r1)
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l.lwz r23,0x54(r1)
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l.lwz r24,0x58(r1)
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l.lwz r24,0x58(r1)
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l.lwz r25,0x5c(r1)
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l.lwz r25,0x5c(r1)
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l.lwz r26,0x60(r1)
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l.lwz r26,0x60(r1)
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l.lwz r27,0x64(r1)
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l.lwz r27,0x64(r1)
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l.lwz r28,0x68(r1)
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l.lwz r28,0x68(r1)
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l.lwz r29,0x6c(r1)
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l.lwz r29,0x6c(r1)
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l.lwz r30,0x70(r1)
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l.lwz r30,0x70(r1)
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l.lwz r31,0x74(r1)
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l.lwz r31,0x74(r1)
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# l.lwz r3,0x78(r1)
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# l.lwz r3,0x78(r1)
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l.mtspr r0,r0,SPR_PICSR
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l.mtspr r0,r0,SPR_PICSR
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l.mfspr r3,r0,SPR_ESR_BASE
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l.mfspr r3,r0,SPR_ESR_BASE
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l.ori r3,r3,SPR_SR_IEE
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l.ori r3,r3,SPR_SR_IEE
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l.mtspr r0,r3,SPR_ESR_BASE
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l.mtspr r0,r3,SPR_ESR_BASE
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l.lwz r3,0x78(r1)
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l.lwz r3,0x78(r1)
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l.addi r1,r1,128
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l.addi r1,r1,128
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l.rfe
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l.rfe
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l.nop
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l.nop
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.section .text
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.section .text
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_lolev_ie:
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_lolev_ie:
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l.mfspr r3,r0,SPR_SR
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l.mfspr r3,r0,SPR_SR
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l.ori r3,r3,SPR_SR_IEE
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l.ori r3,r3,SPR_SR_IEE
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l.mtspr r0,r3,SPR_SR
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l.mtspr r0,r3,SPR_SR
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l.movhi r3,hi(ETH0_INT)
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l.movhi r3,hi(ETH0_INT)
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l.ori r3,r3,lo(ETH0_INT)
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l.ori r3,r3,lo(ETH0_INT)
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l.mtspr r0,r3,SPR_PICMR
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l.mtspr r0,r3,SPR_PICMR
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|
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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|
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_lolev_idis:
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_lolev_idis:
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l.mtspr r0,r0,SPR_PICMR
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l.mtspr r0,r0,SPR_PICMR
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|
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l.jr r9
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l.jr r9
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l.nop
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l.nop
|
|
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