/* icache_model.c -- instruction cache simulation
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/* icache_model.c -- instruction cache simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Cache functions.
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/* Cache functions.
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At the moment this functions only simulate functionality of instruction
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At the moment this functions only simulate functionality of instruction
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caches and do not influence on fetche/decode/execute stages and timings.
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caches and do not influence on fetche/decode/execute stages and timings.
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They are here only to verify performance of various cache configurations.
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They are here only to verify performance of various cache configurations.
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <errno.h>
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#include <errno.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include "icache_model.h"
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#include "icache_model.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "stats.h"
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#include "stats.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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/* Instruction cache */
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/* Instruction cache */
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/* Number of IC sets (power of 2) */
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/* Number of IC sets (power of 2) */
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#define IC_SETS 512
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#define IC_SETS 512
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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#define IC_BLOCK_SIZE 16
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#define IC_BLOCK_SIZE 16
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/* Number of IC ways (1, 2, 3 etc.). */
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/* Number of IC ways (1, 2, 3 etc.). */
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#define IC_WAYS 1
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#define IC_WAYS 1
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/* Number of usage states (2, 3, 4 etc.). */
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/* Number of usage states (2, 3, 4 etc.). */
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#define IC_USTATES 2
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#define IC_USTATES 2
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struct ic_set {
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struct ic_set {
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struct {
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struct {
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unsigned long tagaddr; /* tag address */
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unsigned long tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[IC_WAYS];
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} way[IC_WAYS];
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} ic[IC_SETS];
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} ic[IC_SETS];
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void ic_info()
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void ic_info()
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{
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{
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if (!getsprbits(SPR_UPR, SPR_UPR_ICP)) {
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if (!getsprbits(SPR_UPR, SPR_UPR_ICP)) {
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printf("ICache not implemented. Set UPR[ICP].\n");
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printf("ICache not implemented. Set UPR[ICP].\n");
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return;
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return;
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}
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}
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printf("Instruction cache %dKB: ", IC_SETS * IC_BLOCK_SIZE * IC_WAYS / 1024);
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printf("Instruction cache %dKB: ", IC_SETS * IC_BLOCK_SIZE * IC_WAYS / 1024);
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printf("%d ways, %d sets, block size %d bytes\n", IC_WAYS, IC_SETS, IC_BLOCK_SIZE);
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printf("%d ways, %d sets, block size %d bytes\n", IC_WAYS, IC_SETS, IC_BLOCK_SIZE);
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}
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}
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/* First check if instruction is already in the cache and if it is:
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/* First check if instruction is already in the cache and if it is:
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- increment IC read hit stats,
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- increment IC read hit stats,
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- set 'lru' at this way to IC_USTATES - 1 and
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- set 'lru' at this way to IC_USTATES - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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and if not:
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and if not:
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- increment IC read miss stats
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- increment IC read miss stats
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- set 'lru' with IC_USTATES - 1 and decrement 'lru' of other
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- set 'lru' with IC_USTATES - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void ic_simulate_fetch(unsigned long fetchaddr)
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void ic_simulate_fetch(unsigned long fetchaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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/* ICache simulation enabled/disabled. */
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/* ICache simulation enabled/disabled. */
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if ((!getsprbits(SPR_UPR, SPR_UPR_ICP)) || (!getsprbits(SPR_SR, SPR_SR_ICE)))
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if ((!getsprbits(SPR_UPR, SPR_UPR_ICP)) || (!getsprbits(SPR_SR, SPR_SR_ICE)))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (fetchaddr / IC_BLOCK_SIZE) % IC_SETS;
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set = (fetchaddr / IC_BLOCK_SIZE) % IC_SETS;
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tagaddr = (fetchaddr / IC_BLOCK_SIZE) / IC_SETS;
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tagaddr = (fetchaddr / IC_BLOCK_SIZE) / IC_SETS;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < IC_WAYS; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached instruction? */
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/* Did we find our cached instruction? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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ic_stats.readhit++;
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ic_stats.readhit++;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < IC_WAYS; i++)
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if (ic[set].way[i].lru)
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if (ic[set].way[i].lru)
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[way].lru = IC_USTATES - 1;
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ic[set].way[way].lru = IC_USTATES - 1;
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = IC_USTATES - 1;
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int minlru = IC_USTATES - 1;
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int minway = 0;
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int minway = 0;
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ic_stats.readmiss++;
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ic_stats.readmiss++;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < IC_WAYS; i++)
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if (ic[set].way[i].lru < minlru)
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if (ic[set].way[i].lru < minlru)
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minway = i;
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minway = i;
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ic[set].way[minway].tagaddr = tagaddr;
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ic[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < IC_WAYS; i++)
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if ((ic[set].way[i].lru) &&
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if ((ic[set].way[i].lru) &&
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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(getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << i)))
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[minway].lru = IC_USTATES - 1;
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ic[set].way[minway].lru = IC_USTATES - 1;
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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otherwise don't do anything.
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otherwise don't do anything.
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*/
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*/
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void ic_inv(unsigned long dataaddr)
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void ic_inv(unsigned long dataaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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if (!getsprbits(SPR_UPR, SPR_UPR_ICP))
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if (!getsprbits(SPR_UPR, SPR_UPR_ICP))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / IC_BLOCK_SIZE) % IC_SETS;
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set = (dataaddr / IC_BLOCK_SIZE) % IC_SETS;
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tagaddr = (dataaddr / IC_BLOCK_SIZE) / IC_SETS;
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tagaddr = (dataaddr / IC_BLOCK_SIZE) / IC_SETS;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < IC_WAYS; i++)
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for (i = 0; i < IC_WAYS; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if ((way >= 0) && (getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << way))) { /* Yes, we did. */
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if ((way >= 0) && (getsprbits(SPR_ICCR, SPR_ICCR_EW) & (1 << way))) { /* Yes, we did. */
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ic[set].way[way].tagaddr = -1;
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ic[set].way[way].tagaddr = -1;
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}
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}
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}
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}
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void ic_clock()
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void ic_clock()
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{
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{
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unsigned long addr;
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unsigned long addr;
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if (addr = mfspr(SPR_ICBPR)) {
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if (addr = mfspr(SPR_ICBPR)) {
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ic_simulate_read(addr);
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ic_simulate_fetch(addr);
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mtspr(SPR_ICBPR, 0);
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mtspr(SPR_ICBPR, 0);
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}
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}
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if (addr = mfspr(SPR_ICBIR)) {
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if (addr = mfspr(SPR_ICBIR)) {
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ic_inv(addr);
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ic_inv(addr);
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mtspr(SPR_ICBIR, 0);
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mtspr(SPR_ICBIR, 0);
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}
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}
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if (addr = mfspr(SPR_ICBLR)) {
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if (addr = mfspr(SPR_ICBLR)) {
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mtspr(SPR_ICBLR, 0);
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mtspr(SPR_ICBLR, 0);
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}
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}
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}
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}
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