/* except.c -- Simulation of OR1K exceptions
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/* except.c -- Simulation of OR1K exceptions
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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extern int cont_run;
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extern int cont_run;
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extern struct iqueue_entry iqueue[20];
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extern struct iqueue_entry iqueue[20];
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extern unsigned long pc;
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extern unsigned long pc;
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extern unsigned long pcnext;
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extern unsigned long pcnext;
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extern unsigned long pc_phy;
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extern struct iqueue_entry iqueue[];
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extern struct iqueue_entry iqueue[];
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extern int delay_insn;
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extern int delay_insn;
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int cycle_delay = 0; /* Added by CZ 27/05/01 */
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/* Handle OR1K exceptions. */
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/* Handle OR1K exceptions. */
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void except_handle(int except, unsigned long ea)
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void except_handle(int except, unsigned long ea)
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{
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{
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unsigned long pc_saved;
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unsigned long pc_saved;
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printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
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printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
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printf("Iqueue[0].insn_addr: 0x%x Eff ADDR: 0x%x\n", iqueue[0].insn_addr, ea);
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printf("Iqueue[0].insn_addr: 0x%x Eff ADDR: 0x%x\n", iqueue[0].insn_addr, ea);
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printf(" pc: 0x%x pcnext: 0x%x\n", pc, pcnext);
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printf(" pc: 0x%x pcnext: 0x%x\n", pc, pcnext);
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#if ONLY_VIRTUAL_MACHINE
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#if ONLY_VIRTUAL_MACHINE
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printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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printf("WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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cont_run = 0;
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cont_run = 0;
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#else
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#else
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if (delay_insn) {
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if (delay_insn) {
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printf(" INFO: Exception during execution of delay slot insn.\n");
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printf(" INFO: Exception during execution of delay slot insn.\n");
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pc -= 4;
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pc -= 4;
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}
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}
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#if 0
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#if 0
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if ((pcnext != (pc + 4)) && (except != EXCEPT_ITLBMISS)) { /* Always execute delay slot insn */
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if ((pcnext != (pc + 4)) && (except != EXCEPT_ITLBMISS)) { /* Always execute delay slot insn */
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printf("XXXXXXXXXXXXXX\n");
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printf("XXXXXXXXXXXXXX\n");
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fetch(); /* before starting with exception */
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fetch(); /* before starting with exception */
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decode(&iqueue[0]); /* (itlbmiss is special case) */
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decode(&iqueue[0]); /* (itlbmiss is special case) */
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execute();
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execute();
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}
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}
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#endif
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#endif
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if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
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if (!(mfspr(SPR_SR) & SPR_SR_EXR)) {
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printf("ABORT: Exception occured while exception detection was disabled.\n");
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printf("ABORT: Exception occured while exception detection was disabled.\n");
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cont_run = 0;
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cont_run = 0;
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return;
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return;
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}
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}
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pc_saved = pc & ~0x3;
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pc_saved = pc & ~0x3;
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mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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/* Address translation is always disabled when starting exception. */
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/* Address translation is always disabled when starting exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EXR); /* Disable except. */
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pc = (unsigned long)except;
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pc = (unsigned long)except;
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pcnext = (unsigned long)except;
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/* MM: We do pc update after the execute (in the simulator), so we
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decrease it by 4 so that next instruction points to first exception
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instruction. */
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if (except == EXCEPT_SYSCALL)
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pc -= 4;
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pcnext = pc+4;
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/* Added by CZ 27/05/01 */
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pc_phy = pc;
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cycle_delay = 7; /* An exception stalls the CPU 7 clock cycles */
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#endif
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#endif
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}
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}
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