/* execute.c -- OR1K architecture dependent simulation
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/* execute.c -- OR1K architecture dependent simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Most of the OR1K simulation is done in here.
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/* Most of the OR1K simulation is done in here.
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When SIMPLE_EXECUTION is defined below a file insnset.c is included!
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When SIMPLE_EXECUTION is defined below a file insnset.c is included!
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <ctype.h>
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#include <ctype.h>
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#include "config.h"
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#include "config.h"
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#include "arch.h"
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#include "arch.h"
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#include "branch_predict.h"
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#include "branch_predict.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "labels.h"
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#include "labels.h"
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#include "parse.h"
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#include "parse.h"
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#include "execute.h"
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#include "execute.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "immu.h"
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#include "immu.h"
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#include "dmmu.h"
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#include "dmmu.h"
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#include "debug.h"
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#include "debug.h"
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#include "stats.h"
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#include "stats.h"
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/* General purpose registers. */
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/* General purpose registers. */
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machword reg[MAX_GPRS];
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machword reg[MAX_GPRS];
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/* Instruction queue */
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/* Instruction queue */
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struct iqueue_entry iqueue[20];
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struct iqueue_entry iqueue[20];
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/* Is current insn in execution a delay insn? */
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/* Is current insn in execution a delay insn? */
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int delay_insn;
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int delay_insn;
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/* Benchmark multi issue execution */
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/* Benchmark multi issue execution */
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int multissue[20];
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int multissue[20];
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int issued_per_cycle = 4;
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int issued_per_cycle = 4;
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/* Whether break was hit - so we can step over a break */
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/* Whether break was hit - so we can step over a break */
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static int break_just_hit = 0;
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static int break_just_hit = 0;
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/* freemem 'pointer' */
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/* freemem 'pointer' */
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extern unsigned long freemem;
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extern unsigned long freemem;
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/* Completition queue */
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/* Completition queue */
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struct iqueue_entry icomplet[20];
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struct iqueue_entry icomplet[20];
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/* Program counter (and translated PC) */
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/* Program counter (and translated PC) */
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unsigned long pc;
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unsigned long pc;
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unsigned long pc_phy;
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unsigned long pc_phy;
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/* Previous program counter */
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/* Previous program counter */
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unsigned long pcprev = 0;
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unsigned long pcprev = 0;
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/* Temporary program counter */
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/* Temporary program counter */
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unsigned long pcnext;
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unsigned long pcnext;
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/* Delay instruction effective address register */
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/* Delay instruction effective address register */
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unsigned long pcdelay;
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unsigned long pcdelay;
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/* CCR */
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/* CCR */
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int flag;
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int flag;
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/* CCR (for dependency calculation) */
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/* CCR (for dependency calculation) */
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char ccr_flag[10] = "flag";
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char ccr_flag[10] = "flag";
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/* Store buffer analysis - stores are accumulated and commited when IO is idle */
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/* Store buffer analysis - stores are accumulated and commited when IO is idle */
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static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;
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static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;
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static int sbuf_buf[MAX_SBUF_LEN] = {0};
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static int sbuf_buf[MAX_SBUF_LEN] = {0};
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static int sbuf_prev_cycles = 0;
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static int sbuf_prev_cycles = 0;
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/* Num cycles waiting for stores to complete */
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/* Num cycles waiting for stores to complete */
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int sbuf_wait_cyc = 0;
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int sbuf_wait_cyc = 0;
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/* Number of total store cycles */
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/* Number of total store cycles */
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int sbuf_total_cyc = 0;
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int sbuf_total_cyc = 0;
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/* Whether we are doing statistical analysis */
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/* Whether we are doing statistical analysis */
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int do_stats = 0;
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int do_stats = 0;
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/* Local data needed for execution. */
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/* Local data needed for execution. */
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static int next_delay_insn;
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static int next_delay_insn;
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static int breakpoint;
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static int breakpoint;
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static unsigned long *op;
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static int num_op;
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/* Effective address of instructions that have an effective address. This is
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* only used to get dump_exe_log correct */
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static unsigned long insn_ea;
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/* Implementation specific.
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/* Implementation specific.
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Get an actual value of a specific register. */
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Get an actual value of a specific register. */
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unsigned long evalsim_reg32(int regno)
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unsigned long evalsim_reg32(int regno)
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{
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{
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if (regno < MAX_GPRS) {
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if (regno < MAX_GPRS) {
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return reg[regno];
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return reg[regno];
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} else {
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} else {
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PRINTF("\nABORT: read out of registers\n");
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PRINTF("\nABORT: read out of registers\n");
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return 0;
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return 0;
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}
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}
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}
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}
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/* Implementation specific.
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/* Implementation specific.
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Set a specific register with value. */
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Set a specific register with value. */
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void setsim_reg32(int regno, unsigned long value)
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void setsim_reg32(int regno, unsigned long value)
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{
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{
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if (regno == 0) /* gpr0 is always zero */
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if (regno == 0) /* gpr0 is always zero */
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value = 0;
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value = 0;
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if (regno < MAX_GPRS) {
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if (regno < MAX_GPRS) {
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reg[regno] = value;
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reg[regno] = value;
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} else {
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} else {
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PRINTF("\nABORT: write out of registers\n");
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PRINTF("\nABORT: write out of registers\n");
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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}
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}
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}
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}
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/* Implementation specific.
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/* Implementation specific.
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Get an actual value of a specific register. */
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Get an actual value of a specific register. */
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inline static unsigned long eval_reg32(int regno)
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inline static unsigned long eval_reg32(int regno)
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{
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{
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if (regno < MAX_GPRS) {
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if (regno < MAX_GPRS) {
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#if RAW_RANGE_STATS
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#if RAW_RANGE_STATS
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int delta = (runtime.sim.cycles - raw_stats.reg[regno]);
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int delta = (runtime.sim.cycles - raw_stats.reg[regno]);
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if ((unsigned long)delta < (unsigned long)MAX_RAW_RANGE)
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if ((unsigned long)delta < (unsigned long)MAX_RAW_RANGE)
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raw_stats.range[delta]++;
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raw_stats.range[delta]++;
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#endif /* RAW_RANGE */
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#endif /* RAW_RANGE */
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return reg[regno];
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return reg[regno];
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} else {
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} else {
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PRINTF("\nABORT: read out of registers\n");
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PRINTF("\nABORT: read out of registers\n");
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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return 0;
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return 0;
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}
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}
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}
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}
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/* Implementation specific.
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/* Implementation specific.
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Set a specific register with value. */
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Set a specific register with value. */
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inline static void set_reg32(int regno, unsigned long value)
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inline static void set_reg32(int regno, unsigned long value)
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{
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{
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#if 0
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#if 0
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if (strcmp(regstr, FRAME_REG) == 0) {
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if (strcmp(regstr, FRAME_REG) == 0) {
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PRINTF("FP (%s) modified by insn at %x. ", FRAME_REG, pc);
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PRINTF("FP (%s) modified by insn at %x. ", FRAME_REG, pc);
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PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);
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PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);
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}
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}
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if (strcmp(regstr, STACK_REG) == 0) {
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if (strcmp(regstr, STACK_REG) == 0) {
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PRINTF("SP (%s) modified by insn at %x. ", STACK_REG, pc);
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PRINTF("SP (%s) modified by insn at %x. ", STACK_REG, pc);
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PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regmo), value);
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PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regmo), value);
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}
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}
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#endif
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#endif
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if (regno < MAX_GPRS) {
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if (regno < MAX_GPRS) {
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reg[regno] = value;
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reg[regno] = value;
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#if RAW_RANGE_STATS
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#if RAW_RANGE_STATS
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raw_stats.reg[regno] = runtime.sim.cycles;
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raw_stats.reg[regno] = runtime.sim.cycles;
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#endif /* RAW_RANGE */
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#endif /* RAW_RANGE */
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} else {
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} else {
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PRINTF("\nABORT: write out of registers\n");
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PRINTF("\nABORT: write out of registers\n");
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runtime.sim.cont_run = 0;
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runtime.sim.cont_run = 0;
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}
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}
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}
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}
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/* Does srcoperand depend on computation of dstoperand? Return
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/* Implementation specific.
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Evaluates source operand opd. */
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static unsigned long eval_operand_val(unsigned long insn,
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struct insn_op_struct *opd)
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{
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unsigned long operand = 0;
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unsigned long sbit;
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unsigned int nbits = 0;
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while(1) {
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operand |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;
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nbits += opd->data;
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if(opd->type & OPTYPE_OP)
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break;
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opd++;
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}
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if(opd->type & OPTYPE_SIG) {
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sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
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if(operand & (1 << sbit)) operand |= 0xffffffff << sbit;
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}
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return operand;
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}
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/* Does source operand depend on computation of dstoperand? Return
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non-zero if yes.
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non-zero if yes.
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Cycle t Cycle t+1
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Cycle t Cycle t+1
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dst: irrelevant src: immediate always 0
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dst: irrelevant src: immediate always 0
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dst: reg1 direct src: reg2 direct 0 if reg1 != reg2
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dst: reg1 direct src: reg2 direct 0 if reg1 != reg2
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dst: reg1 disp src: reg2 direct always 0
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dst: reg1 disp src: reg2 direct always 0
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dst: reg1 direct src: reg2 disp 0 if reg1 != reg2
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dst: reg1 direct src: reg2 disp 0 if reg1 != reg2
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dst: reg1 disp src: reg2 disp always 1 (store must
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dst: reg1 disp src: reg2 disp always 1 (store must
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finish before load)
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finish before load)
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dst: flag src: flag always 1
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dst: flag src: flag always 1
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*/
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*/
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int depend_operands(prev, next)
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int depend_operands(prev, next)
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struct iqueue_entry *prev;
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struct iqueue_entry *prev;
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struct iqueue_entry *next;
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struct iqueue_entry *next;
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{
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{
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/* Find destination type. */
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/* Find destination type. */
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unsigned long type = 0;
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unsigned long type = 0;
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int i = 0;
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int prev_dis, next_dis;
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unsigned int prev_reg_val = 0;
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struct insn_op_struct *opd;
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if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG
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if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG
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&& or32_opcodes[next->insn_index].flags & OR32_R_FLAG)
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&& or32_opcodes[next->insn_index].flags & OR32_R_FLAG)
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return 1;
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return 1;
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while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST))
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opd = op_start[prev->insn_index];
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if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST)
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prev_dis = 0;
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{
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type = prev->op[i + MAX_OPERANDS];
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while (1) {
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if (opd->type & OPTYPE_DIS)
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prev_dis = 1;
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if (opd->type & OPTYPE_DST) {
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type = opd->type;
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if (prev_dis)
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type |= OPTYPE_DIS;
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/* Destination is always a register */
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prev_reg_val = eval_operand_val (prev->insn, opd);
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break;
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break;
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}
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}
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else
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if (opd->type & OPTYPE_LAST)
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i++;
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return 0; /* Doesn't have a destination operand */
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if (opd->type & OPTYPE_OP)
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prev_dis = 0;
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opd++;
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}
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/* We search all source operands - if we find confict => return 1 */
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/* We search all source operands - if we find confict => return 1 */
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i = 0;
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opd = op_start[next->insn_index];
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while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))
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next_dis = 0;
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if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))
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{
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while (1) {
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if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS) {
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if (opd->type & OPTYPE_DIS)
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if (type & OPTYPE_DIS)
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next_dis = 1;
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return 1;
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/* This instruction sequence also depends on order of execution:
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else if (next->op[i] == prev->op[i]
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* l.lw r1, k(r1)
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG))
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* l.sw k(r1), r4
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* Here r1 is a destination in l.sw */
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/* FIXME: This situation is not handeld here when r1 == r2:
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* l.sw k(r1), r4
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* l.lw r3, k(r2)
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*/
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if (!(opd->type & OPTYPE_DST) || (next_dis && (opd->type & OPTYPE_DST))) {
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if (opd->type & OPTYPE_REG)
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if (eval_operand_val (next->insn, opd) == prev_reg_val)
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return 1;
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return 1;
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}
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}
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if (next->op[i] == prev->op[i]
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if (opd->type & OPTYPE_LAST)
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&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG)
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break;
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&& (type & OPTYPE_REG))
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opd++;
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return 1;
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i++;
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}
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}
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else
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i++;
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return 0;
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return 0;
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}
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}
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/* Sets a new SPR_SR_OV value, based on next register value */
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/* Sets a new SPR_SR_OV value, based on next register value */
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#if SET_OV_FLAG
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#if SET_OV_FLAG
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#define set_ov_flag(value) if((value) & 0x80000000) setsprbits (SPR_SR, SPR_SR_OV, 1); else setsprbits (SPR_SR, SPR_SR_OV, 0)
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#define set_ov_flag(value) if((value) & 0x80000000) setsprbits (SPR_SR, SPR_SR_OV, 1); else setsprbits (SPR_SR, SPR_SR_OV, 0)
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#else
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#else
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#define set_ov_flag(value)
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#define set_ov_flag(value)
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#endif
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#endif
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/* Modified by CZ 26/05/01 for new mode execution */
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/* Modified by CZ 26/05/01 for new mode execution */
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/* Fetch returns nonzero if instruction should NOT be executed. */
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/* Fetch returns nonzero if instruction should NOT be executed. */
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static inline int fetch()
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static inline int fetch()
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{
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{
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/* Update the pc for pending exceptions, or get physical pc */
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/* Update the pc for pending exceptions, or get physical pc */
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if (!pending.valid)
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if (!pending.valid)
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pc_phy = immu_translate(pc);
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pc_phy = immu_translate(pc);
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if(pending.valid)
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if(pending.valid)
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except_handle_backend(pending.type, pending.address, pending.saved);
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except_handle_backend(pending.type, pending.address, pending.saved);
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if (CHECK_BREAKPOINTS) {
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if (CHECK_BREAKPOINTS) {
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/* MM: Check for breakpoint. This has to be done in fetch cycle,
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/* MM: Check for breakpoint. This has to be done in fetch cycle,
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because of peripheria.
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because of peripheria.
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MM1709: if we cannot access the memory entry, we could not set the
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MM1709: if we cannot access the memory entry, we could not set the
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breakpoint earlier, so just chech the breakpoint list. */
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breakpoint earlier, so just chech the breakpoint list. */
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if (has_breakpoint (pc_phy) && !break_just_hit) {
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if (has_breakpoint (pc_phy) && !break_just_hit) {
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break_just_hit = 1;
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break_just_hit = 1;
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return 1; /* Breakpoint set. */
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return 1; /* Breakpoint set. */
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}
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}
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break_just_hit = 0;
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break_just_hit = 0;
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}
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}
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pc_phy &= ~0x03;
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pc_phy &= ~0x03;
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runtime.cpu.instructions++;
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runtime.cpu.instructions++;
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/* Fetch instruction. */
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/* Fetch instruction. */
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iqueue[0].insn_addr = pc;
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iqueue[0].insn_addr = pc;
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iqueue[0].insn = eval_insn (pc_phy, &breakpoint);
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iqueue[0].insn = eval_insn (pc_phy, &breakpoint);
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|
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/* update_pc will be called after execution */
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/* update_pc will be called after execution */
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return 0;
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return 0;
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}
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}
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|
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/* This code actually updates the PC value. */
|
/* This code actually updates the PC value. */
|
static inline void update_pc ()
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static inline void update_pc ()
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{
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{
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delay_insn = next_delay_insn;
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delay_insn = next_delay_insn;
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pcprev = pc; /* Store value for later */
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pcprev = pc; /* Store value for later */
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pc = pcnext;
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pc = pcnext;
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pcnext = delay_insn ? pcdelay : pcnext + 4;
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pcnext = delay_insn ? pcdelay : pcnext + 4;
|
}
|
}
|
|
|
#if SIMPLE_EXECUTION
|
#if SIMPLE_EXECUTION
|
static inline
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static inline
|
#endif
|
#endif
|
void analysis (struct iqueue_entry *current)
|
void analysis (struct iqueue_entry *current)
|
{
|
{
|
if (config.cpu.dependstats) {
|
if (config.cpu.dependstats) {
|
/* Dynamic, dependency stats. */
|
/* Dynamic, dependency stats. */
|
adddstats(icomplet[0].insn_index, current->insn_index, 1, check_depend());
|
adddstats(icomplet[0].insn_index, current->insn_index, 1, check_depend());
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|
|
/* Dynamic, functional units stats. */
|
/* Dynamic, functional units stats. */
|
addfstats(or32_opcodes[icomplet[0].insn_index].func_unit,
|
addfstats(or32_opcodes[icomplet[0].insn_index].func_unit,
|
or32_opcodes[current->insn_index].func_unit, 1, check_depend());
|
or32_opcodes[current->insn_index].func_unit, 1, check_depend());
|
|
|
/* Dynamic, single stats. */
|
/* Dynamic, single stats. */
|
addsstats(current->insn_index, 1);
|
addsstats(current->insn_index, 1);
|
}
|
}
|
|
|
if (config.cpu.superscalar) {
|
if (config.cpu.superscalar) {
|
if ((or32_opcodes[current->insn_index].func_unit == it_branch) ||
|
if ((or32_opcodes[current->insn_index].func_unit == it_branch) ||
|
(or32_opcodes[current->insn_index].func_unit == it_jump))
|
(or32_opcodes[current->insn_index].func_unit == it_jump))
|
runtime.sim.storecycles += 0;
|
runtime.sim.storecycles += 0;
|
|
|
if (or32_opcodes[current->insn_index].func_unit == it_store)
|
if (or32_opcodes[current->insn_index].func_unit == it_store)
|
runtime.sim.storecycles += 1;
|
runtime.sim.storecycles += 1;
|
|
|
if (or32_opcodes[current->insn_index].func_unit == it_load)
|
if (or32_opcodes[current->insn_index].func_unit == it_load)
|
runtime.sim.loadcycles += 1;
|
runtime.sim.loadcycles += 1;
|
#if 0
|
#if 0
|
if ((icomplet[0].func_unit == it_load) && check_depend())
|
if ((icomplet[0].func_unit == it_load) && check_depend())
|
runtime.sim.loadcycles++;
|
runtime.sim.loadcycles++;
|
#endif
|
#endif
|
|
|
/* Pseudo multiple issue benchmark */
|
/* Pseudo multiple issue benchmark */
|
if ((multissue[or32_opcodes[current->insn_index].func_unit] < 1) ||
|
if ((multissue[or32_opcodes[current->insn_index].func_unit] < 1) ||
|
(check_depend()) || (issued_per_cycle < 1)) {
|
(check_depend()) || (issued_per_cycle < 1)) {
|
int i;
|
int i;
|
for (i = 0; i < 20; i++)
|
for (i = 0; i < 20; i++)
|
multissue[i] = 2;
|
multissue[i] = 2;
|
issued_per_cycle = 2;
|
issued_per_cycle = 2;
|
runtime.cpu.supercycles++;
|
runtime.cpu.supercycles++;
|
if (check_depend())
|
if (check_depend())
|
runtime.cpu.hazardwait++;
|
runtime.cpu.hazardwait++;
|
multissue[it_unknown] = 2;
|
multissue[it_unknown] = 2;
|
multissue[it_shift] = 2;
|
multissue[it_shift] = 2;
|
multissue[it_compare] = 1;
|
multissue[it_compare] = 1;
|
multissue[it_branch] = 1;
|
multissue[it_branch] = 1;
|
multissue[it_jump] = 1;
|
multissue[it_jump] = 1;
|
multissue[it_extend] = 2;
|
multissue[it_extend] = 2;
|
multissue[it_nop] = 2;
|
multissue[it_nop] = 2;
|
multissue[it_move] = 2;
|
multissue[it_move] = 2;
|
multissue[it_movimm] = 2;
|
multissue[it_movimm] = 2;
|
multissue[it_arith] = 2;
|
multissue[it_arith] = 2;
|
multissue[it_store] = 2;
|
multissue[it_store] = 2;
|
multissue[it_load] = 2;
|
multissue[it_load] = 2;
|
}
|
}
|
multissue[or32_opcodes[current->insn_index].func_unit]--;
|
multissue[or32_opcodes[current->insn_index].func_unit]--;
|
issued_per_cycle--;
|
issued_per_cycle--;
|
}
|
}
|
|
|
if (config.cpu.dependstats)
|
if (config.cpu.dependstats)
|
/* Instruction waits in completition buffer until retired. */
|
/* Instruction waits in completition buffer until retired. */
|
memcpy (&icomplet[0], current, sizeof (struct iqueue_entry));
|
memcpy (&icomplet[0], current, sizeof (struct iqueue_entry));
|
|
|
if (config.sim.history) {
|
if (config.sim.history) {
|
int i;
|
int i;
|
|
|
/* History of execution */
|
/* History of execution */
|
for (i = HISTEXEC_LEN - 1; i; i--)
|
for (i = HISTEXEC_LEN - 1; i; i--)
|
histexec[i] = histexec[i - 1];
|
histexec[i] = histexec[i - 1];
|
histexec[0] = icomplet[0].insn_addr; /* add last insn */
|
histexec[0] = icomplet[0].insn_addr; /* add last insn */
|
}
|
}
|
|
|
if (config.sim.exe_log) dump_exe_log();
|
if (config.sim.exe_log) dump_exe_log();
|
}
|
}
|
|
|
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
|
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
|
static inline void sbuf_store (int cyc) {
|
static inline void sbuf_store (int cyc) {
|
int delta = runtime.sim.cycles - sbuf_prev_cycles;
|
int delta = runtime.sim.cycles - sbuf_prev_cycles;
|
sbuf_total_cyc += cyc;
|
sbuf_total_cyc += cyc;
|
sbuf_prev_cycles = runtime.sim.cycles;
|
sbuf_prev_cycles = runtime.sim.cycles;
|
|
|
//PRINTF (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
//PRINTF (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
//PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
|
//PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
|
/* Take stores from buffer, that occured meanwhile */
|
/* Take stores from buffer, that occured meanwhile */
|
while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {
|
while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {
|
delta -= sbuf_buf[sbuf_tail];
|
delta -= sbuf_buf[sbuf_tail];
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_count--;
|
sbuf_count--;
|
}
|
}
|
if (sbuf_count)
|
if (sbuf_count)
|
sbuf_buf[sbuf_tail] -= delta;
|
sbuf_buf[sbuf_tail] -= delta;
|
|
|
/* Store buffer is full, take one out */
|
/* Store buffer is full, take one out */
|
if (sbuf_count >= config.cpu.sbuf_len) {
|
if (sbuf_count >= config.cpu.sbuf_len) {
|
sbuf_wait_cyc += sbuf_buf[sbuf_tail];
|
sbuf_wait_cyc += sbuf_buf[sbuf_tail];
|
runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];
|
runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];
|
sbuf_prev_cycles += sbuf_buf[sbuf_tail];
|
sbuf_prev_cycles += sbuf_buf[sbuf_tail];
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_count--;
|
sbuf_count--;
|
}
|
}
|
/* Put newest store in the buffer */
|
/* Put newest store in the buffer */
|
sbuf_buf[sbuf_head] = cyc;
|
sbuf_buf[sbuf_head] = cyc;
|
sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;
|
sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;
|
sbuf_count++;
|
sbuf_count++;
|
//PRINTF ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
//PRINTF ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
}
|
}
|
|
|
/* Store buffer analysis - previous stores should commit, before any load */
|
/* Store buffer analysis - previous stores should commit, before any load */
|
static inline void sbuf_load () {
|
static inline void sbuf_load () {
|
int delta = runtime.sim.cycles - sbuf_prev_cycles;
|
int delta = runtime.sim.cycles - sbuf_prev_cycles;
|
sbuf_prev_cycles = runtime.sim.cycles;
|
sbuf_prev_cycles = runtime.sim.cycles;
|
|
|
//PRINTF (">LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
//PRINTF (">LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
//PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
|
//PRINTF ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);
|
/* Take stores from buffer, that occured meanwhile */
|
/* Take stores from buffer, that occured meanwhile */
|
while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {
|
while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {
|
delta -= sbuf_buf[sbuf_tail];
|
delta -= sbuf_buf[sbuf_tail];
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_count--;
|
sbuf_count--;
|
}
|
}
|
if (sbuf_count)
|
if (sbuf_count)
|
sbuf_buf[sbuf_tail] -= delta;
|
sbuf_buf[sbuf_tail] -= delta;
|
|
|
/* Wait for all stores to complete */
|
/* Wait for all stores to complete */
|
while (sbuf_count > 0) {
|
while (sbuf_count > 0) {
|
sbuf_wait_cyc += sbuf_buf[sbuf_tail];
|
sbuf_wait_cyc += sbuf_buf[sbuf_tail];
|
runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];
|
runtime.sim.mem_cycles += sbuf_buf[sbuf_tail];
|
sbuf_prev_cycles += sbuf_buf[sbuf_tail];
|
sbuf_prev_cycles += sbuf_buf[sbuf_tail];
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
|
sbuf_count--;
|
sbuf_count--;
|
}
|
}
|
//PRINTF ("|LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
//PRINTF ("|LOAD %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);
|
}
|
}
|
|
|
/* Outputs dissasembled instruction */
|
/* Outputs dissasembled instruction */
|
void dump_exe_log ()
|
void dump_exe_log ()
|
{
|
{
|
unsigned long i = iqueue[0].insn_addr;
|
unsigned long insn_addr = iqueue[0].insn_addr;
|
|
unsigned long i, j;
|
|
|
if (i == 0xffffffff) return;
|
if (insn_addr == 0xffffffff) return;
|
if (config.sim.exe_log_start <= runtime.cpu.instructions && (config.sim.exe_log_end <= 0 || runtime.cpu.instructions <= config.sim.exe_log_end)) {
|
if ((config.sim.exe_log_start <= runtime.cpu.instructions) &&
|
if (config.sim.exe_log_marker && runtime.cpu.instructions % config.sim.exe_log_marker == 0) {
|
((config.sim.exe_log_end <= 0) ||
|
|
(runtime.cpu.instructions <= config.sim.exe_log_end))) {
|
|
if (config.sim.exe_log_marker &&
|
|
!(runtime.cpu.instructions % config.sim.exe_log_marker)) {
|
fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions);
|
fprintf (runtime.sim.fexe_log, "--------------------- %8lli instruction ---------------------\n", runtime.cpu.instructions);
|
}
|
}
|
switch (config.sim.exe_log_type) {
|
switch (config.sim.exe_log_type) {
|
case EXE_LOG_HARDWARE:
|
case EXE_LOG_HARDWARE:
|
fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ", runtime.cpu.instructions, i);
|
fprintf (runtime.sim.fexe_log, "\nEXECUTED(%11llu): %.8lx: ",
|
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i), evalsim_mem8_void(i + 1));
|
runtime.cpu.instructions, insn_addr);
|
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(i + 2), evalsim_mem8_void(i + 3));
|
fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8_void(insn_addr),
|
|
evalsim_mem8_void(insn_addr + 1));
|
|
fprintf (runtime.sim.fexe_log, "%.2x%.2x",
|
|
evalsim_mem8_void(insn_addr + 2),
|
|
evalsim_mem8_void(insn_addr + 3));
|
for(i = 0; i < MAX_GPRS; i++) {
|
for(i = 0; i < MAX_GPRS; i++) {
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
fprintf(runtime.sim.fexe_log, "\n");
|
fprintf(runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx ", i, reg[i]);
|
fprintf (runtime.sim.fexe_log, "GPR%2lu: %.8lx ", i, reg[i]);
|
}
|
}
|
fprintf (runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
|
fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
|
fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
|
fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
|
fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
|
fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
|
fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));
|
fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));
|
break;
|
break;
|
case EXE_LOG_SIMPLE:
|
case EXE_LOG_SIMPLE:
|
case EXE_LOG_SOFTWARE:
|
case EXE_LOG_SOFTWARE:
|
{
|
{
|
extern char *disassembled;
|
extern char *disassembled;
|
disassemble_index (iqueue[0].insn, iqueue[0].insn_index);
|
disassemble_index (iqueue[0].insn, iqueue[0].insn_index);
|
{
|
{
|
struct label_entry *entry;
|
struct label_entry *entry;
|
entry = get_label(i);
|
entry = get_label(insn_addr);
|
if (entry)
|
if (entry)
|
fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
|
fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
|
}
|
}
|
|
|
if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
|
if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
|
int i,j=0;
|
struct insn_op_struct *opd = op_start[iqueue[0].insn_index];
|
|
|
for (i = 0; i < num_op; i++)
|
j = 0;
|
if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {
|
while (1) {
|
j=1;
|
i = eval_operand_val (iqueue[0].insn, opd);
|
fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", op[i],
|
while (!(opd->type & OPTYPE_OP))
|
peek_into_dtlb(op[i],0,0));
|
opd++;
|
} else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {
|
if (opd->type & OPTYPE_DIS) {
|
fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", op[i],
|
fprintf (runtime.sim.fexe_log, "EA =%08lx PA =%08lx ", insn_ea,
|
evalsim_reg32 (op[i]));
|
peek_into_dtlb(insn_ea,0,0));
|
|
opd++; /* Skip of register operand */
|
|
j++;
|
|
} else if ((opd->type & OPTYPE_REG) && i) {
|
|
fprintf (runtime.sim.fexe_log, "r%-2li=%08lx ", i,
|
|
evalsim_reg32 (i));
|
} else
|
} else
|
fprintf (runtime.sim.fexe_log, " ");
|
fprintf (runtime.sim.fexe_log, " ");
|
|
j++;
|
i+=j;
|
if(opd->type & OPTYPE_LAST)
|
for (; i < 3; i++)
|
break;
|
|
opd++;
|
|
}
|
|
while(j < 3) {
|
fprintf (runtime.sim.fexe_log, " ");
|
fprintf (runtime.sim.fexe_log, " ");
|
|
j++;
|
}
|
}
|
fprintf (runtime.sim.fexe_log, "%.8lx ", i);
|
}
|
|
fprintf (runtime.sim.fexe_log, "%.8lx ", insn_addr);
|
fprintf (runtime.sim.fexe_log, "%s\n", disassembled);
|
fprintf (runtime.sim.fexe_log, "%s\n", disassembled);
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Dump registers - 'r' or 't' command */
|
/* Dump registers - 'r' or 't' command */
|
void dumpreg()
|
void dumpreg()
|
{
|
{
|
int i;
|
int i;
|
unsigned long physical_pc;
|
unsigned long physical_pc;
|
|
|
if ((physical_pc = peek_into_itlb(iqueue[0].insn_addr))) {
|
if ((physical_pc = peek_into_itlb(iqueue[0].insn_addr))) {
|
/*
|
/*
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", iqueue[0].insn_addr, physical_pc);
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", iqueue[0].insn_addr, physical_pc);
|
*/
|
*/
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
}
|
}
|
else {
|
else {
|
PRINTF("INTERNAL SIMULATOR ERROR:\n");
|
PRINTF("INTERNAL SIMULATOR ERROR:\n");
|
PRINTF("no translation for currently executed instruction\n");
|
PRINTF("no translation for currently executed instruction\n");
|
}
|
}
|
|
|
// generate_time_pretty (temp, runtime.sim.cycles * config.sim.clkcycle_ps);
|
// generate_time_pretty (temp, runtime.sim.cycles * config.sim.clkcycle_ps);
|
PRINTF(" (executed) [cycle %lld, #%lld]\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF(" (executed) [cycle %lld, #%lld]\n", runtime.sim.cycles, runtime.cpu.instructions);
|
if (config.cpu.superscalar)
|
if (config.cpu.superscalar)
|
PRINTF ("Superscalar CYCLES: %u", runtime.cpu.supercycles);
|
PRINTF ("Superscalar CYCLES: %u", runtime.cpu.supercycles);
|
if (config.cpu.hazards)
|
if (config.cpu.hazards)
|
PRINTF (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
|
PRINTF (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
|
else
|
else
|
if (config.cpu.superscalar)
|
if (config.cpu.superscalar)
|
PRINTF ("\n");
|
PRINTF ("\n");
|
|
|
if ((physical_pc = peek_into_itlb(pc))) {
|
if ((physical_pc = peek_into_itlb(pc))) {
|
/*
|
/*
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", pc, physical_pc);
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", pc, physical_pc);
|
*/
|
*/
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
}
|
}
|
else
|
else
|
PRINTF("%08lx: : xxxxxxxx ITLB miss follows", pc);
|
PRINTF("%08lx: : xxxxxxxx ITLB miss follows", pc);
|
|
|
PRINTF(" (next insn) %s", (delay_insn?"(delay insn)":""));
|
PRINTF(" (next insn) %s", (delay_insn?"(delay insn)":""));
|
for(i = 0; i < MAX_GPRS; i++) {
|
for(i = 0; i < MAX_GPRS; i++) {
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
PRINTF("\n");
|
PRINTF("\n");
|
PRINTF("GPR%.2u: %.8lx ", i, evalsim_reg32(i));
|
PRINTF("GPR%.2u: %.8lx ", i, evalsim_reg32(i));
|
}
|
}
|
PRINTF("flag: %u\n", flag);
|
PRINTF("flag: %u\n", flag);
|
}
|
}
|
|
|
/* Generated/built in decoding/executing function */
|
/* Generated/built in decoding/executing function */
|
static inline void decode_execute (struct iqueue_entry *current);
|
static inline void decode_execute (struct iqueue_entry *current);
|
|
|
/* Wrapper around real decode_execute function -- some statistics here only */
|
/* Wrapper around real decode_execute function -- some statistics here only */
|
static inline void decode_execute_wrapper (struct iqueue_entry *current)
|
static inline void decode_execute_wrapper (struct iqueue_entry *current)
|
{
|
{
|
breakpoint = 0;
|
breakpoint = 0;
|
next_delay_insn = 0;
|
next_delay_insn = 0;
|
|
|
#ifndef HAS_EXECUTION
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#ifndef HAS_EXECUTION
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#error HAS_EXECUTION has to be defined in order to execute programs.
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#error HAS_EXECUTION has to be defined in order to execute programs.
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#endif
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#endif
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if(config.debug.enabled && CheckDebugUnit(DebugInstructionFetch, pc_phy))
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if(config.debug.enabled && CheckDebugUnit(DebugInstructionFetch, pc_phy))
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breakpoint = 1;
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breakpoint = 1;
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decode_execute (current);
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decode_execute (current);
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#if SET_OV_FLAG
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#if SET_OV_FLAG
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/* Check for range exception */
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/* Check for range exception */
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if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))
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if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))
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except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
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except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
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#endif
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#endif
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if(breakpoint)
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if(breakpoint)
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except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
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except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
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}
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}
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/* Reset the CPU */
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/* Reset the CPU */
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void cpu_reset()
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void cpu_reset()
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{
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{
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int i;
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int i;
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runtime.sim.cycles = 0;
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runtime.sim.cycles = 0;
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runtime.sim.loadcycles = 0;
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runtime.sim.loadcycles = 0;
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runtime.sim.storecycles = 0;
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runtime.sim.storecycles = 0;
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runtime.cpu.instructions = 0;
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runtime.cpu.instructions = 0;
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runtime.cpu.supercycles = 0;
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runtime.cpu.supercycles = 0;
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runtime.cpu.hazardwait = 0;
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runtime.cpu.hazardwait = 0;
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for (i = 0; i < MAX_GPRS; i++)
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for (i = 0; i < MAX_GPRS; i++)
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set_reg32 (i, 0);
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set_reg32 (i, 0);
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memset(iqueue, 0, sizeof(iqueue));
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memset(iqueue, 0, sizeof(iqueue));
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memset(icomplet, 0, sizeof(icomplet));
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memset(icomplet, 0, sizeof(icomplet));
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sbuf_head = 0;
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sbuf_head = 0;
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sbuf_tail = 0;
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sbuf_tail = 0;
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sbuf_count = 0;
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sbuf_count = 0;
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sbuf_prev_cycles = 0;
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sbuf_prev_cycles = 0;
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/* Cpu configuration */
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/* Cpu configuration */
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mtspr(SPR_UPR, config.cpu.upr);
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mtspr(SPR_UPR, config.cpu.upr);
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setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);
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setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);
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setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
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setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
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mtspr(SPR_SR, config.cpu.sr);
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mtspr(SPR_SR, config.cpu.sr);
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pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
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pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
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if (config.sim.verbose) PRINTF ("Starting at 0x%08lx\n", pcnext);
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if (config.sim.verbose) PRINTF ("Starting at 0x%08lx\n", pcnext);
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pc = pcnext;
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pc = pcnext;
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pc_phy = pc;
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pc_phy = pc;
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pcnext += 4;
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pcnext += 4;
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debug(1, "reset ...\n");
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debug(1, "reset ...\n");
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/* MM1409: All programs should set their stack pointer! */
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/* MM1409: All programs should set their stack pointer! */
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except_handle(EXCEPT_RESET, 0);
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except_handle(EXCEPT_RESET, 0);
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}
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}
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/* Simulates one CPU clock cycle */
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/* Simulates one CPU clock cycle */
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inline int cpu_clock ()
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inline int cpu_clock ()
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{
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{
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if(fetch()) {
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if(fetch()) {
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PRINTF ("Breakpoint hit.\n");
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PRINTF ("Breakpoint hit.\n");
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runtime.sim.cont_run = 0; /* memory breakpoint encountered */
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runtime.sim.cont_run = 0; /* memory breakpoint encountered */
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return 1;
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return 1;
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}
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}
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decode_execute_wrapper (&iqueue[0]);
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decode_execute_wrapper (&iqueue[0]);
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update_pc();
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update_pc();
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return 0;
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return 0;
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}
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}
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/* If decoding cannot be found, call this function */
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/* If decoding cannot be found, call this function */
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#if SIMPLE_EXECUTION
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#if SIMPLE_EXECUTION
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void l_invalid (struct iqueue_entry *current) {
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void l_invalid (struct iqueue_entry *current) {
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#else
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#else
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void l_invalid () {
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void l_invalid () {
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#endif
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#endif
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except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
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except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
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}
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}
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#if !SIMPLE_EXECUTION
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#if !SIMPLE_EXECUTION
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/* Include decode_execute function */
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/* Include decode_execute function */
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#include "execgen.c"
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#include "execgen.c"
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#else /* SIMPLE_EXECUTION */
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#else /* SIMPLE_EXECUTION */
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#define INSTRUCTION(name) void name (struct iqueue_entry *current)
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#define INSTRUCTION(name) void name (struct iqueue_entry *current)
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/* Implementation specific.
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/* Implementation specific.
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Parses and returns operands. */
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Evaluates source operand op_no. */
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static void
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static unsigned long eval_operand (int op_no, unsigned long insn_index,
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eval_operands (unsigned long insn, int insn_index, int* breakpoint)
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unsigned long insn)
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{
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{
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struct insn_op_struct *opd = op_start[insn_index];
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struct insn_op_struct *opd = op_start[insn_index];
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unsigned long data = 0;
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unsigned long ret;
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int dis = 0;
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int no = 0;
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while (1)
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while (op_no) {
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{
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if(opd->type & OPTYPE_LAST) {
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unsigned long tmp = 0, nbits = 0;
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fprintf (stderr, "Instruction requested more operands than it has\n");
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while (1)
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exit (1);
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{
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}
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tmp |= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;
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if((opd->type & OPTYPE_OP) && !(opd->type & OPTYPE_DIS))
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nbits += opd->data;
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op_no--;
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if (opd->type & OPTYPE_OP)
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break;
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opd++;
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opd++;
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}
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}
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/* Do we have to sign extend? */
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if (opd->type & OPTYPE_SIG)
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{
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int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
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if (tmp & (1 << sbit))
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tmp |= 0xFFFFFFFF << sbit;
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}
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if (opd->type & OPTYPE_DIS) {
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if (opd->type & OPTYPE_DIS) {
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/* We have to read register later. */
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ret = eval_operand_val (insn, opd);
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data += tmp;
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while (!(opd->type & OPTYPE_OP))
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dis = 1;
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} else
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{
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if (dis && (opd->type & OPTYPE_REG))
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op[no] = data + eval_reg32 (tmp);
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else
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op[no] = tmp;
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op[no + MAX_OPERANDS] = opd->type | (dis ? OPTYPE_DIS : 0);
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no++;
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data = 0;
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dis = 0;
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}
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if(opd->type & OPTYPE_LAST) {
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num_op = no;
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return;
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}
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opd++;
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opd++;
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opd++;
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ret += eval_reg32 (eval_operand_val (insn, opd));
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insn_ea = ret;
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return ret;
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}
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}
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num_op = no;
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if (opd->type & OPTYPE_REG)
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return eval_reg32 (eval_operand_val (insn, opd));
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return eval_operand_val (insn, opd);
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}
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}
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/* Implementation specific.
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/* Implementation specific.
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Evaluates source operand op_no. */
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Set destination operand (reister direct) with value. */
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static unsigned long eval_operand (int op_no)
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inline static void set_operand(int op_no, unsigned long value,
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unsigned long insn_index, unsigned long insn)
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{
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{
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if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
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struct insn_op_struct *opd = op_start[insn_index];
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return op[op_no];
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} else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {
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while (op_no) {
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return eval_reg32 (op[op_no]);
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if(opd->type & OPTYPE_LAST) {
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} else {
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fprintf (stderr, "Instruction requested more operands than it has\n");
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return op[op_no];
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exit (1);
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}
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}
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if((opd->type & OPTYPE_OP) && !(opd->type & OPTYPE_DIS))
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op_no--;
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opd++;
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}
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}
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/* Implementation specific.
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if (!(opd->type & OPTYPE_REG)) {
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Set destination operand (reister direct) with value. */
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inline static void set_operand(int op_no, unsigned long value)
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{
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/* Mark this as destination operand. */
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if (!(op[op_no + MAX_OPERANDS] & OPTYPE_REG)) {
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fprintf (stderr, "Trying to set a non-register operand\n");
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fprintf (stderr, "Trying to set a non-register operand\n");
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exit (1);
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exit (1);
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}
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}
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set_reg32(op[op_no], value);
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set_reg32 (eval_operand_val (insn, opd), value);
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}
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}
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/* Simple and rather slow decoding function based on built automata. */
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/* Simple and rather slow decoding function based on built automata. */
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static inline void decode_execute (struct iqueue_entry *current)
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static inline void decode_execute (struct iqueue_entry *current)
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{
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{
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int insn_index;
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int insn_index;
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current->insn_index = insn_index = insn_decode(current->insn);
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current->insn_index = insn_index = insn_decode(current->insn);
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if (insn_index < 0)
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if (insn_index < 0)
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l_invalid(current);
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l_invalid(current);
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else {
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else {
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op = ¤t->op[0];
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eval_operands (current->insn, insn_index, &breakpoint);
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or32_opcodes[insn_index].exec(current);
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or32_opcodes[insn_index].exec(current);
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}
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}
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if (do_stats) analysis(&iqueue[0]);
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if (do_stats) analysis(&iqueue[0]);
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}
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}
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#define SET_PARAM0(val) set_operand(0, val)
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#define SET_PARAM0(val) set_operand(0, val, current->insn_index, current->insn)
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#define PARAM0 eval_operand(0)
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#define PARAM0 eval_operand(0, current->insn_index, current->insn)
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#define PARAM1 eval_operand(1)
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#define PARAM1 eval_operand(1, current->insn_index, current->insn)
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#define PARAM2 eval_operand(2)
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#define PARAM2 eval_operand(2, current->insn_index, current->insn)
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#include "insnset.c"
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#include "insnset.c"
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#endif /* !SIMPLE_EXECUTION */
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#endif /* !SIMPLE_EXECUTION */
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