/*
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/*
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atahost.h -- ATA Host code simulation
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atahost.h -- ATA Host code simulation
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator
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This file is part of OpenRISC 1000 Architectural Simulator
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version
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(at your option) any later version
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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/*
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/*
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* Definitions for the Opencores ATA Controller Core, Device model
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* Definitions for the Opencores ATA Controller Core, Device model
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*/
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*/
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#ifndef __OR1KSIM_ATAD_H
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#ifndef __OR1KSIM_ATAD_H
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#define __OR1KSIM_ATAD_H
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#define __OR1KSIM_ATAD_H
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#include <stdio.h>
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#include <stdio.h>
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/*
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/*
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ata device debug level
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ata device debug level
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0: don't display debug information
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0: don't display debug information
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1: display general (debug) information
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1: display general (debug) information
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2: display program flow control information
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2: display program flow control information
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3: display internal statemachine flow information
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3: display internal statemachine flow information
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4: display all debug information
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4: display all debug information
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*/
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*/
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#define ATA_DEVICE_DEBUG_LVL 4
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#define ATA_DEVICE_DEBUG_LVL 4
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/* --- Register definitions --- */
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/* --- Register definitions --- */
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/* ----- ATA Registers */
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/* ----- ATA Registers */
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/* These are actually the memory locations where the ATA registers */
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/* These are actually the memory locations where the ATA registers */
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/* can be found in the host system; i.e. as seen from the CPU. */
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/* can be found in the host system; i.e. as seen from the CPU. */
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/* However, this doesn't matter for the simulator. */
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/* However, this doesn't matter for the simulator. */
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#define ATA_ASR 0x78 /* Alternate Status Register (R) */
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#define ATA_ASR 0x78 /* Alternate Status Register (R) */
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#define ATA_CR 0x5c /* Command Register (W) */
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#define ATA_CR 0x5c /* Command Register (W) */
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#define ATA_CHR 0x54 /* Cylinder High Register (R/W) */
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#define ATA_CHR 0x54 /* Cylinder High Register (R/W) */
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#define ATA_CLR 0x50 /* Cylinder Low Register (R/W) */
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#define ATA_CLR 0x50 /* Cylinder Low Register (R/W) */
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#define ATA_DR 0x40 /* Data Register */
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#define ATA_DR 0x40 /* Data Register */
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#define ATA_DCR 0x78 /* Device Control Register (W) */
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#define ATA_DCR 0x78 /* Device Control Register (W) */
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#define ATA_DHR 0x58 /* Device/Head Register (R/W) */
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#define ATA_DHR 0x58 /* Device/Head Register (R/W) */
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#define ATA_ERR 0x44 /* Error Register (R) */
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#define ATA_ERR 0x44 /* Error Register (R) */
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#define ATA_FR 0x44 /* Features Register (W) */
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#define ATA_FR 0x44 /* Features Register (W) */
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#define ATA_SCR 0x48 /* Sector Count Register (R/W) */
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#define ATA_SCR 0x48 /* Sector Count Register (R/W) */
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#define ATA_SNR 0x4c /* Sector Number Register (R/W) */
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#define ATA_SNR 0x4c /* Sector Number Register (R/W) */
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#define ATA_SR 0x5c /* Status Register (R) */
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#define ATA_SR 0x5c /* Status Register (R) */
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#define ATA_DA 0x7c /* Device Address Register (R) */
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#define ATA_DA 0x7c /* Device Address Register (R) */
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/* ATA/ATAPI-5 does not describe Device Status Register */
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/* ATA/ATAPI-5 does not describe Device Status Register */
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/* -------------------------------------- */
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/* -------------------------------------- */
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/* ----- ATA Device bit defenitions ----- */
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/* ----- ATA Device bit defenitions ----- */
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/* -------------------------------------- */
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/* -------------------------------------- */
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/* ----- ATA (Alternate) Status Register */
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/* ----- ATA (Alternate) Status Register */
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#define ATA_SR_BSY 0x80 /* Busy */
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#define ATA_SR_BSY 0x80 /* Busy */
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#define ATA_SR_DRDY 0x40 /* Device Ready */
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#define ATA_SR_DRDY 0x40 /* Device Ready */
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#define ATA_SR_DF 0x20 /* Device Fault */
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#define ATA_SR_DF 0x20 /* Device Fault */
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#define ATA_SR_DSC 0x10 /* Device Seek Complete */
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#define ATA_SR_DSC 0x10 /* Device Seek Complete */
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#define ATA_SR_DRQ 0x08 /* Data Request */
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#define ATA_SR_DRQ 0x08 /* Data Request */
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#define ATA_SR_COR 0x04 /* Corrected data (obsolete) */
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#define ATA_SR_COR 0x04 /* Corrected data (obsolete) */
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#define ATA_SR_IDX 0x02 /* (obsolete) */
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#define ATA_SR_IDX 0x02 /* (obsolete) */
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#define ATA_SR_ERR 0x01 /* Error */
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#define ATA_SR_ERR 0x01 /* Error */
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/* ----- ATA Device Control Register */
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/* ----- ATA Device Control Register */
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/* bits 7-3 are reserved */
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/* bits 7-3 are reserved */
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#define ATA_DCR_RST 0x04 /* Software reset (RST=1, reset) */
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#define ATA_DCR_RST 0x04 /* Software reset (RST=1, reset) */
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#define ATA_DCR_IEN 0x02 /* Interrupt Enable (IEN=0, enabled) */
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#define ATA_DCR_IEN 0x02 /* Interrupt Enable (IEN=0, enabled) */
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/* always write a '0' to bit0 */
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/* always write a '0' to bit0 */
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/* ----- ATA Device Address Register */
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/* ----- ATA Device Address Register */
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/* All values in this register are one's complement (i.e. inverted) */
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/* All values in this register are one's complement (i.e. inverted) */
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#define ATA_DAR_WTG 0x40 /* Write Gate */
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#define ATA_DAR_WTG 0x40 /* Write Gate */
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#define ATA_DAR_H 0x3c /* Head Select */
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#define ATA_DAR_H 0x3c /* Head Select */
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#define ATA_DAR_DS1 0x02 /* Drive select 1 */
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#define ATA_DAR_DS1 0x02 /* Drive select 1 */
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#define ATA_DAR_DS0 0x01 /* Drive select 0 */
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#define ATA_DAR_DS0 0x01 /* Drive select 0 */
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/* ----- Device/Head Register */
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/* ----- Device/Head Register */
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#define ATA_DHR_LBA 0x40 /* LBA/CHS mode ('1'=LBA mode) */
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#define ATA_DHR_LBA 0x40 /* LBA/CHS mode ('1'=LBA mode) */
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#define ATA_DHR_DEV 0x10 /* Device ('0'=dev0, '1'=dev1) */
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#define ATA_DHR_DEV 0x10 /* Device ('0'=dev0, '1'=dev1) */
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#define ATA_DHR_H 0x0f /* Head Select */
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#define ATA_DHR_H 0x0f /* Head Select */
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/* ----- Error Register */
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/* ----- Error Register */
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#define ATA_ERR_BBK 0x80 /* Bad Block */
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#define ATA_ERR_BBK 0x80 /* Bad Block */
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#define ATA_ERR_UNC 0x40 /* Uncorrectable Data Error */
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#define ATA_ERR_UNC 0x40 /* Uncorrectable Data Error */
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#define ATA_ERR_IDNF 0x10 /* ID Not Found */
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#define ATA_ERR_IDNF 0x10 /* ID Not Found */
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#define ATA_ERR_ABT 0x04 /* Aborted Command */
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#define ATA_ERR_ABT 0x04 /* Aborted Command */
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#define ATA_ERR_TON 0x02 /* Track0 Not Found */
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#define ATA_ERR_TON 0x02 /* Track0 Not Found */
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#define ATA_ERR_AMN 0x01 /* Address Mark Not Found */
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#define ATA_ERR_AMN 0x01 /* Address Mark Not Found */
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/* -------------------------- */
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/* -------------------------- */
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/* ----- Device Defines ----- */
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/* ----- Device Defines ----- */
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/* -------------------------- */
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/* -------------------------- */
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/* types for hard disk simulation */
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/* types for hard disk simulation */
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#define TYPE_NO_CONNECT 0
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#define TYPE_NO_CONNECT 0
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#define TYPE_FILE 1
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#define TYPE_FILE 1
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#define TYPE_LOCAL 2
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#define TYPE_LOCAL 2
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/* ----------------------------- */
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/* ----------------------------- */
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/* ----- Statemachine defines -- */
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/* ----- Statemachine defines -- */
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/* ----------------------------- */
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/* ----------------------------- */
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#define ATA_STATE_IDLE 0x00
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#define ATA_STATE_IDLE 0x00
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#define ATA_STATE_SW_RST 0x01
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#define ATA_STATE_SW_RST 0x01
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#define ATA_STATE_HW_RST 0x02
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#define ATA_STATE_HW_RST 0x02
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/* ---------------------------- */
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/* ---------------------------- */
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/* ----- Structs ----- */
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/* ----- Structs ----- */
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/* ---------------------------- */
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/* ---------------------------- */
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typedef struct{
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typedef struct{
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/******* Housekeeping *****************************************/
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/******* Housekeeping *****************************************/
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struct {
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struct {
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/* device number */
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/* device number */
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int dev;
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int dev;
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/* current PIO mode */
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/* current PIO mode */
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int pio_mode;
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int pio_mode;
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/* current DMA mode */
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/* current DMA mode */
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int dma_mode;
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int dma_mode;
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/* databuffer */
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/* databuffer */
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unsigned short dbuf[4096];
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unsigned short dbuf[4096];
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unsigned short *dbuf_ptr;
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unsigned short *dbuf_ptr;
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unsigned short dbuf_cnt;
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unsigned short dbuf_cnt;
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/* current statemachine state */
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/* current statemachine state */
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int state;
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int state;
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/* current CHS translation settings */
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/* current CHS translation settings */
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unsigned int heads_per_cylinder;
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unsigned int heads_per_cylinder;
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unsigned int sectors_per_track;
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unsigned int sectors_per_track;
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} internals;
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} internals;
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/******* ATA Device Registers *********************************/
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/******* ATA Device Registers *********************************/
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struct {
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struct {
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unsigned char command;
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unsigned char command;
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unsigned char cylinder_low;
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unsigned char cylinder_low;
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unsigned char cylinder_high;
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unsigned char cylinder_high;
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unsigned char device_control;
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unsigned char device_control;
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unsigned char device_head;
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unsigned char device_head;
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unsigned char error;
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unsigned char error;
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unsigned char features;
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unsigned char features;
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unsigned char sector_count;
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unsigned char sector_count;
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unsigned char sector_number;
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unsigned char sector_number;
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unsigned char status;
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unsigned char status;
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short dataport_i;
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short dataport_i;
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} regs;
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} regs;
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/******** ata device output signals **************************/
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/******** ata device output signals **************************/
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struct {
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struct {
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int iordy;
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int iordy;
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int intrq;
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int intrq;
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int dmarq;
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int dmarq;
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int pdiagi, pdiago;
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int pdiagi, pdiago;
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int daspi, daspo;
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int daspi, daspo;
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} sigs;
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} sigs;
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/******** simulator settings **********************************/
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/******** simulator settings **********************************/
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/* simulate ata-device */
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/* simulate ata-device */
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char *file; /* Filename (if type == FILE) */
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FILE *stream; /* stream where the simulated device connects to*/
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FILE *stream; /* stream where the simulated device connects to*/
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int type; /* Simulate device using */
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int type; /* Simulate device using */
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/* NO_CONNECT: no device connected (dummy) */
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/* NO_CONNECT: no device connected (dummy) */
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/* FILE : a file */
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/* FILE : a file */
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/* LOCAL : a local stream, e.g./dev/hda1 */
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/* LOCAL : a local stream, e.g./dev/hda1 */
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unsigned long size; /* size in MB of the simulated device */
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unsigned long size; /* size in MB of the simulated device */
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int packet; /* device implements PACKET command set */
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int packet; /* device implements PACKET command set */
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} ata_device;
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} ata_device;
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typedef struct{
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typedef struct{
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ata_device device0, device1;
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ata_device device0, device1;
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} ata_devices;
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} ata_devices;
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/* ------------------------------ */
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/* ------------------------------ */
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/* ----- Device Prototypes ----- */
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/* ----- Device Prototypes ----- */
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/* ------------------------------ */
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/* ------------------------------ */
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int ata_device_debug(int lvl, char *format, ...);
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int ata_device_debug(int lvl, char *format, ...);
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/* all devices */
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/* all devices */
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void ata_devices_init(ata_devices *devices, const char *filename0, const char *filename1);
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void ata_devices_init(ata_devices *devices);
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void ata_devices_hw_reset(ata_devices *devices, int reset_signal);
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void ata_devices_hw_reset(ata_devices *devices, int reset_signal);
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short ata_devices_read(ata_devices *devices, char adr);
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short ata_devices_read(ata_devices *devices, char adr);
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void ata_devices_write(ata_devices *devices, char adr, short value);
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void ata_devices_write(ata_devices *devices, char adr, short value);
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/* single device */
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/* single device */
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void ata_device_init(ata_device *device, int dev, const char *filename);
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void ata_device_init(ata_device *device, int dev);
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void ata_device_hw_reset(ata_device *device, int reset_signal, int daspo, int pdiagi, int daspi);
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void ata_device_hw_reset(ata_device *device, int reset_signal, int daspo, int pdiagi, int daspi);
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void ata_device_do_control_register(ata_device *device);
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void ata_device_do_control_register(ata_device *device);
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void ata_device_do_command_register(ata_device *device);
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void ata_device_do_command_register(ata_device *device);
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void ata_device_write(ata_device *device, char adr, short value);
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void ata_device_write(ata_device *device, char adr, short value);
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/* housekeeping routines */
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/* housekeeping routines */
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FILE *open_file(unsigned long *size, const char *filename);
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FILE *open_file(unsigned long *size, const char *filename);
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FILE *open_local(void);
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FILE *open_local(void);
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#endif
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#endif
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