/*
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/*
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atahost.c -- ATA Host code simulation
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atahost.c -- ATA Host code simulation
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator
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This file is part of OpenRISC 1000 Architectural Simulator
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version
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(at your option) any later version
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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/* get a prototype for 'register_memoryarea()', and 'adjust_rw_delay()' */
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/* get a prototype for 'register_memoryarea()', and 'adjust_rw_delay()' */
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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/* all user defineable settings are in 'atahost_define.h' */
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/* all user defineable settings are in 'atahost_define.h' */
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#include "atahost_define.h"
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#include "atahost_define.h"
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#include "atahost.h"
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#include "atahost.h"
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#include "messages.h"
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#include "messages.h"
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/* reset and initialize ATA host core(s) */
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/* reset and initialize ATA host core(s) */
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void ata_reset(void *dat)
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void ata_reset(void *dat)
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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// reset the core registers
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// reset the core registers
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ata->regs.ctrl = 0x0001;
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ata->regs.ctrl = 0x0001;
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ata->regs.stat = (DEV_ID << 28) | (REV << 24);
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ata->regs.stat = (DEV_ID << 28) | (REV << 24);
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ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
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ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
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ata->regs.txb = 0;
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ata->regs.txb = 0;
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// inform simulator about new read/write delay timings
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// inform simulator about new read/write delay timings
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
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/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
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ata_devices_hw_reset(&ata->devices, 1);
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ata_devices_hw_reset(&ata->devices, 1);
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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/*
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/*
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Read a register
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Read a register
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*/
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*/
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uint32_t ata_read32( oraddr_t addr, void *dat )
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uint32_t ata_read32( oraddr_t addr, void *dat )
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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addr -= ata->baseaddr;
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addr -= ata->baseaddr;
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/* determine if ata_host or ata_device addressed */
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/* determine if ata_host or ata_device addressed */
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if (is_ata_hostadr(addr))
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if (is_ata_hostadr(addr))
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{
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{
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// Accesses to internal register take 2cycles
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// Accesses to internal register take 2cycles
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adjust_rw_delay( ata->baseaddr, 2, 2 );
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adjust_rw_delay( ata->baseaddr, 2, 2 );
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switch( addr ) {
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switch( addr ) {
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case ATA_CTRL :
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case ATA_CTRL :
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return ata -> regs.ctrl;
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return ata -> regs.ctrl;
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case ATA_STAT :
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case ATA_STAT :
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return ata -> regs.stat;
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return ata -> regs.stat;
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case ATA_PCTR :
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case ATA_PCTR :
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return ata -> regs.pctr;
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return ata -> regs.pctr;
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#if (DEV_ID > 1)
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#if (DEV_ID > 1)
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case ATA_PFTR0:
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case ATA_PFTR0:
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return ata -> regs.pftr0;
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return ata -> regs.pftr0;
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case ATA_PFTR1:
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case ATA_PFTR1:
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return ata -> regs.pftr1;
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return ata -> regs.pftr1;
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#endif
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#endif
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#if (DEV_ID > 2)
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#if (DEV_ID > 2)
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case ATA_DTR0 :
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case ATA_DTR0 :
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return ata -> regs.dtr0;
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return ata -> regs.dtr0;
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case ATA_DTR1 :
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case ATA_DTR1 :
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return ata -> regs.dtr1;
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return ata -> regs.dtr1;
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case ATA_RXB :
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case ATA_RXB :
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return ata -> regs.rxb;
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return ata -> regs.rxb;
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#endif
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#endif
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default:
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default:
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return 0;
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return 0;
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}
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}
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}
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}
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else
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else
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/* check if the controller is enabled */
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/* check if the controller is enabled */
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if (ata->regs.ctrl & ATA_IDE_EN)
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if (ata->regs.ctrl & ATA_IDE_EN)
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{
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{
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// make sure simulator uses correct read/write delay timings
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// make sure simulator uses correct read/write delay timings
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#if (DEV_ID > 1)
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#if (DEV_ID > 1)
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if ( (addr & 0x7f) == ATA_DR)
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if ( (addr & 0x7f) == ATA_DR)
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{
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{
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if (ata->devices.dev)
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if (ata->devices.dev)
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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else
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else
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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}
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}
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else
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else
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#endif
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#endif
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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return ata_devices_read(&ata->devices, addr & 0x7f);
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return ata_devices_read(&ata->devices, addr & 0x7f);
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}
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}
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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/*
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/*
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Write a register
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Write a register
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*/
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*/
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void ata_write32( oraddr_t addr, uint32_t value, void *dat )
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void ata_write32( oraddr_t addr, uint32_t value, void *dat )
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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addr -= ata->baseaddr;
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addr -= ata->baseaddr;
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/* determine if ata_host or ata_device addressed */
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/* determine if ata_host or ata_device addressed */
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if (is_ata_hostadr(addr))
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if (is_ata_hostadr(addr))
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{
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{
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// Accesses to internal register take 2cycles
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// Accesses to internal register take 2cycles
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adjust_rw_delay( ata->baseaddr, 2, 2 );
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adjust_rw_delay( ata->baseaddr, 2, 2 );
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switch( addr ) {
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switch( addr ) {
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case ATA_CTRL :
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case ATA_CTRL :
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ata -> regs.ctrl = value;
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ata -> regs.ctrl = value;
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/* check if reset bit set, if so reset ata-devices */
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/* check if reset bit set, if so reset ata-devices */
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if (value & ATA_RST)
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if (value & ATA_RST)
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ata_devices_hw_reset(&ata->devices, 1);
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ata_devices_hw_reset(&ata->devices, 1);
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else
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else
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ata_devices_hw_reset(&ata->devices, 0);
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ata_devices_hw_reset(&ata->devices, 0);
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break;
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break;
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case ATA_STAT :
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case ATA_STAT :
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ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) | (ata -> regs.stat & ATA_IDEIS & value);
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ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) | (ata -> regs.stat & ATA_IDEIS & value);
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break;
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break;
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case ATA_PCTR :
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case ATA_PCTR :
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ata -> regs.pctr = value;
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ata -> regs.pctr = value;
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break;
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break;
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case ATA_PFTR0:
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case ATA_PFTR0:
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ata -> regs.pftr0 = value;
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ata -> regs.pftr0 = value;
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break;
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break;
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case ATA_PFTR1:
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case ATA_PFTR1:
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ata -> regs.pftr1 = value;
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ata -> regs.pftr1 = value;
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break;
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break;
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case ATA_DTR0 :
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case ATA_DTR0 :
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ata -> regs.dtr0 = value;
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ata -> regs.dtr0 = value;
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break;
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break;
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case ATA_DTR1 :
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case ATA_DTR1 :
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ata -> regs.dtr1 = value;
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ata -> regs.dtr1 = value;
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break;
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break;
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case ATA_TXB :
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case ATA_TXB :
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ata -> regs.txb = value;
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ata -> regs.txb = value;
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break;
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break;
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default:
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default:
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/* ERROR-macro currently only supports simple strings. */
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/* ERROR-macro currently only supports simple strings. */
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/*
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/*
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fprintf(stderr, "ERROR : Unknown register for OCIDEC(%1d).\n", DEV_ID );
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fprintf(stderr, "ERROR : Unknown register for OCIDEC(%1d).\n", DEV_ID );
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Tried to show some useful info here.
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Tried to show some useful info here.
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But when using 'DM'-simulator-command, the screen gets filled with these messages.
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But when using 'DM'-simulator-command, the screen gets filled with these messages.
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Thereby eradicating the usefulness of the message
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Thereby eradicating the usefulness of the message
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*/
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*/
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break;
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break;
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}
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}
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}
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}
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else
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else
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/* check if the controller is enabled */
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/* check if the controller is enabled */
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if (ata->regs.ctrl & ATA_IDE_EN)
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if (ata->regs.ctrl & ATA_IDE_EN)
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{
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{
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// make sure simulator uses correct read/write delay timings
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// make sure simulator uses correct read/write delay timings
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#if (DEV_ID > 1)
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#if (DEV_ID > 1)
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if ( (addr & 0x7f) == ATA_DR)
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if ( (addr & 0x7f) == ATA_DR)
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{
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{
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if (ata->devices.dev)
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if (ata->devices.dev)
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
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else
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else
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
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}
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}
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else
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else
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#endif
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#endif
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
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ata_devices_write(&ata->devices, addr & 0x7f, value);
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ata_devices_write(&ata->devices, addr & 0x7f, value);
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}
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}
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}
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}
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/* ========================================================================= */
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/* ========================================================================= */
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|
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/* Dump status */
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/* Dump status */
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void ata_status( void *dat )
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void ata_status( void *dat )
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{
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{
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ata_host *ata = dat;
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ata_host *ata = dat;
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if ( ata->baseaddr == 0 )
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if ( ata->baseaddr == 0 )
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return;
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return;
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PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", DEV_ID, ata->baseaddr );
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PRINTF( "\nOCIDEC-%1d at: 0x%"PRIxADDR"\n", DEV_ID, ata->baseaddr );
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PRINTF( "ATA CTRL : 0x%08X\n", ata->regs.ctrl );
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PRINTF( "ATA CTRL : 0x%08X\n", ata->regs.ctrl );
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PRINTF( "ATA STAT : 0x%08x\n", ata->regs.stat );
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PRINTF( "ATA STAT : 0x%08x\n", ata->regs.stat );
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PRINTF( "ATA PCTR : 0x%08x\n", ata->regs.pctr );
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PRINTF( "ATA PCTR : 0x%08x\n", ata->regs.pctr );
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#if (DEV_ID > 1)
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#if (DEV_ID > 1)
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PRINTF( "ATA FCTR0 : 0x%08lx\n", ata->regs.pftr0 );
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PRINTF( "ATA FCTR0 : 0x%08lx\n", ata->regs.pftr0 );
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PRINTF( "ATA FCTR1 : 0x%08lx\n", ata->regs.pftr1 );
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PRINTF( "ATA FCTR1 : 0x%08lx\n", ata->regs.pftr1 );
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#endif
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#endif
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#if (DEV_ID > 2)
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#if (DEV_ID > 2)
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PRINTF( "ATA DTR0 : 0x%08lx\n", ata->regs.dtr0 );
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PRINTF( "ATA DTR0 : 0x%08lx\n", ata->regs.dtr0 );
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PRINTF( "ATA DTR1 : 0x%08lx\n", ata->regs.dtr1 );
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PRINTF( "ATA DTR1 : 0x%08lx\n", ata->regs.dtr1 );
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PRINTF( "ATA TXD : 0x%08lx\n", ata->regs.txb );
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PRINTF( "ATA TXD : 0x%08lx\n", ata->regs.txb );
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PRINTF( "ATA RXD : 0x%08lx\n", ata->regs.rxb );
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PRINTF( "ATA RXD : 0x%08lx\n", ata->regs.rxb );
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#endif
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#endif
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}
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}
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/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
/*----------------------------------------------------[ ATA Configuration ]---*/
|
/*----------------------------------------------------[ ATA Configuration ]---*/
|
void ata_baseaddr(union param_val val, void *dat)
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void ata_baseaddr(union param_val val, void *dat)
|
{
|
{
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ata_host *ata = dat;
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ata_host *ata = dat;
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ata->baseaddr = val.addr_val;
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ata->baseaddr = val.addr_val;
|
}
|
}
|
|
|
void ata_irq(union param_val val, void *dat)
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void ata_irq(union param_val val, void *dat)
|
{
|
{
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ata_host *ata = dat;
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ata_host *ata = dat;
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ata->irq = val.int_val;
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ata->irq = val.int_val;
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}
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}
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|
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void ata_dev_type0(union param_val val, void *dat)
|
void ata_dev_type0(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
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ata->devices.device0.type = val.int_val;
|
ata->devices.device0.type = val.int_val;
|
}
|
}
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|
|
void ata_dev_file0(union param_val val, void *dat)
|
void ata_dev_file0(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
if(!(ata->devices.device0.file = strdup(val.str_val))) {
|
if(!(ata->devices.device0.file = strdup(val.str_val))) {
|
fprintf(stderr, "Peripheral ATA: Run out of memory\n");
|
fprintf(stderr, "Peripheral ATA: Run out of memory\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
}
|
}
|
|
|
void ata_dev_size0(union param_val val, void *dat)
|
void ata_dev_size0(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->devices.device0.size = val.int_val;
|
ata->devices.device0.size = val.int_val;
|
}
|
}
|
|
|
void ata_dev_packet0(union param_val val, void *dat)
|
void ata_dev_packet0(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->devices.device0.packet = val.int_val;
|
ata->devices.device0.packet = val.int_val;
|
}
|
}
|
|
|
void ata_dev_type1(union param_val val, void *dat)
|
void ata_dev_type1(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->devices.device1.packet = val.int_val;
|
ata->devices.device1.packet = val.int_val;
|
}
|
}
|
|
|
void ata_dev_file1(union param_val val, void *dat)
|
void ata_dev_file1(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
if(!(ata->devices.device1.file = strdup(val.str_val))) {
|
if(!(ata->devices.device1.file = strdup(val.str_val))) {
|
fprintf(stderr, "Peripheral ATA: Run out of memory\n");
|
fprintf(stderr, "Peripheral ATA: Run out of memory\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
}
|
}
|
|
|
void ata_dev_size1(union param_val val, void *dat)
|
void ata_dev_size1(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->devices.device1.size = val.int_val;
|
ata->devices.device1.size = val.int_val;
|
}
|
}
|
|
|
void ata_dev_packet1(union param_val val, void *dat)
|
void ata_dev_packet1(union param_val val, void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
ata->devices.device1.packet = val.int_val;
|
ata->devices.device1.packet = val.int_val;
|
}
|
}
|
|
|
void *ata_sec_start(void)
|
void *ata_sec_start(void)
|
{
|
{
|
ata_host *new = malloc(sizeof(ata_host));
|
ata_host *new = malloc(sizeof(ata_host));
|
|
|
if(!new) {
|
if(!new) {
|
fprintf(stderr, "Peripheral ATA: Run out of memory\n");
|
fprintf(stderr, "Peripheral ATA: Run out of memory\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
|
|
memset(new, 0, sizeof(ata_host));
|
memset(new, 0, sizeof(ata_host));
|
return new;
|
return new;
|
}
|
}
|
|
|
void ata_sec_end(void *dat)
|
void ata_sec_end(void *dat)
|
{
|
{
|
ata_host *ata = dat;
|
ata_host *ata = dat;
|
|
|
/* Connect ata_devices. */
|
/* Connect ata_devices. */
|
ata_devices_init(&ata->devices);
|
ata_devices_init(&ata->devices);
|
|
|
register_memoryarea(ata->baseaddr, ATA_ADDR_SPACE, 4, 0, ata_read32, ata_write32, dat);
|
register_memoryarea(ata->baseaddr, ATA_ADDR_SPACE, 4, 0, ata_read32, ata_write32, dat);
|
|
|
reg_sim_reset(ata_reset, dat);
|
reg_sim_reset(ata_reset, dat);
|
reg_sim_stat(ata_status, dat);
|
reg_sim_stat(ata_status, dat);
|
}
|
}
|
|
|
void reg_ata_sec(void)
|
void reg_ata_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("ata", ata_sec_start, ata_sec_end);
|
struct config_section *sec = reg_config_sec("ata", ata_sec_start, ata_sec_end);
|
|
|
reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
|
reg_config_param(sec, "baseaddr", paramt_addr, ata_baseaddr);
|
reg_config_param(sec, "irq", paramt_int, ata_irq);
|
reg_config_param(sec, "irq", paramt_int, ata_irq);
|
reg_config_param(sec, "dev_type0", paramt_int, ata_dev_type0);
|
reg_config_param(sec, "dev_type0", paramt_int, ata_dev_type0);
|
reg_config_param(sec, "dev_file0", paramt_str, ata_dev_file0);
|
reg_config_param(sec, "dev_file0", paramt_str, ata_dev_file0);
|
reg_config_param(sec, "dev_size0", paramt_int, ata_dev_size0);
|
reg_config_param(sec, "dev_size0", paramt_int, ata_dev_size0);
|
reg_config_param(sec, "dev_packet0", paramt_int, ata_dev_packet0);
|
reg_config_param(sec, "dev_packet0", paramt_int, ata_dev_packet0);
|
reg_config_param(sec, "dev_type1", paramt_int, ata_dev_type1);
|
reg_config_param(sec, "dev_type1", paramt_int, ata_dev_type1);
|
reg_config_param(sec, "dev_file1", paramt_str, ata_dev_file1);
|
reg_config_param(sec, "dev_file1", paramt_str, ata_dev_file1);
|
reg_config_param(sec, "dev_size1", paramt_int, ata_dev_size1);
|
reg_config_param(sec, "dev_size1", paramt_int, ata_dev_size1);
|
reg_config_param(sec, "dev_packet1", paramt_int, ata_dev_packet1);
|
reg_config_param(sec, "dev_packet1", paramt_int, ata_dev_packet1);
|
}
|
}
|
|
|
