/* icache_model.c -- instruction cache simulation
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/* icache_model.c -- instruction cache simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Cache functions.
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/* Cache functions.
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At the moment this functions only simulate functionality of instruction
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At the moment this functions only simulate functionality of instruction
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caches and do not influence on fetche/decode/execute stages and timings.
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caches and do not influence on fetche/decode/execute stages and timings.
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They are here only to verify performance of various cache configurations.
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They are here only to verify performance of various cache configurations.
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*/
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*/
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <errno.h>
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#include <errno.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "icache_model.h"
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#include "icache_model.h"
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#include "except.h"
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#include "except.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "stats.h"
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#include "stats.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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extern struct dev_memarea *cur_area;
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extern struct dev_memarea *cur_area;
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struct ic_set {
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struct ic_set {
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struct {
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struct {
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uint32_t line[MAX_IC_BLOCK_SIZE];
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uint32_t line[MAX_IC_BLOCK_SIZE];
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oraddr_t tagaddr; /* tag address */
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oraddr_t tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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} way[MAX_IC_WAYS];
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} way[MAX_IC_WAYS];
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} ic[MAX_IC_SETS];
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} ic[MAX_IC_SETS];
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void ic_info()
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void ic_info()
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{
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{
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
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PRINTF("ICache not implemented. Set UPR[ICP].\n");
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PRINTF("ICache not implemented. Set UPR[ICP].\n");
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return;
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return;
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}
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}
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PRINTF("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);
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PRINTF("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);
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PRINTF("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);
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PRINTF("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);
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}
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}
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/* First check if instruction is already in the cache and if it is:
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/* First check if instruction is already in the cache and if it is:
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- increment IC read hit stats,
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- increment IC read hit stats,
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- set 'lru' at this way to config.ic.ustates - 1 and
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- set 'lru' at this way to config.ic.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- read insn from the cache line
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- read insn from the cache line
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and if not:
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and if not:
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- increment IC read miss stats
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- increment IC read miss stats
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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- refill cache line
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- refill cache line
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*/
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*/
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uint32_t ic_simulate_fetch(oraddr_t fetchaddr)
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uint32_t ic_simulate_fetch(oraddr_t fetchaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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uint32_t tmp;
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uint32_t tmp;
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/* ICache simulation enabled/disabled. */
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/* ICache simulation enabled/disabled. */
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
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tmp = evalsim_mem32(fetchaddr);
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tmp = evalsim_mem32(fetchaddr);
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if(!cur_area) {
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if(!cur_area) {
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printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
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printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
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fetchaddr);
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fetchaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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return 0;
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return 0;
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} else if (cur_area->log)
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} else if (cur_area->log)
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fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,
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fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,
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tmp);
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tmp);
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return tmp;
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return tmp;
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
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set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
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tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
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tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached instruction? */
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/* Did we find our cached instruction? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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ic_stats.readhit++;
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ic_stats.readhit++;
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for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].lru > ic[set].way[way].lru)
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if (ic[set].way[i].lru > ic[set].way[way].lru)
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[way].lru = config.ic.ustates - 1;
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ic[set].way[way].lru = config.ic.ustates - 1;
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runtime.sim.mem_cycles += config.ic.hitdelay;
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runtime.sim.mem_cycles += config.ic.hitdelay;
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return (ic[set].way[way].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
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return (ic[set].way[way].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
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}
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}
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else { /* No, we didn't. */
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else { /* No, we didn't. */
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int minlru = config.ic.ustates - 1;
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int minlru = config.ic.ustates - 1;
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int minway = 0;
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int minway = 0;
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ic_stats.readmiss++;
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ic_stats.readmiss++;
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for (i = 0; i < config.ic.nways; i++) {
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for (i = 0; i < config.ic.nways; i++) {
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if (ic[set].way[i].lru < minlru) {
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if (ic[set].way[i].lru < minlru) {
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minway = i;
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minway = i;
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minlru = ic[set].way[i].lru;
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minlru = ic[set].way[i].lru;
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}
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}
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}
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}
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for (i = 0; i < (config.ic.blocksize); i += 4) {
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for (i = 0; i < (config.ic.blocksize); i += 4) {
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tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
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tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
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evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
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evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
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if(!cur_area) {
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if(!cur_area) {
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ic[set].way[minway].tagaddr = -1;
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ic[set].way[minway].tagaddr = -1;
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ic[set].way[minway].lru = 0;
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ic[set].way[minway].lru = 0;
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printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
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printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
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fetchaddr);
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fetchaddr);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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except_handle(EXCEPT_BUSERR, cur_vadd);
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return 0;
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return 0;
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} else if (cur_area->log)
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} else if (cur_area->log)
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fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",
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fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",
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fetchaddr, tmp);
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fetchaddr, tmp);
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}
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}
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ic[set].way[minway].tagaddr = tagaddr;
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ic[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].lru)
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if (ic[set].way[i].lru)
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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ic[set].way[minway].lru = config.ic.ustates - 1;
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ic[set].way[minway].lru = config.ic.ustates - 1;
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runtime.sim.mem_cycles += config.ic.missdelay;
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runtime.sim.mem_cycles += config.ic.missdelay;
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return (ic[set].way[minway].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
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return (ic[set].way[minway].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
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}
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}
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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otherwise don't do anything.
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otherwise don't do anything.
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*/
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*/
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void ic_inv(oraddr_t dataaddr)
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void ic_inv(oraddr_t dataaddr)
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{
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{
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int set, way = -1;
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int set, way = -1;
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int i;
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int i;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
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if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / config.ic.blocksize) % config.ic.nsets;
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set = (dataaddr / config.ic.blocksize) % config.ic.nsets;
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tagaddr = (dataaddr / config.ic.blocksize) / config.ic.nsets;
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tagaddr = (dataaddr / config.ic.blocksize) / config.ic.nsets;
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if (!testsprbits(SPR_SR, SPR_SR_ICE)) {
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if (!testsprbits(SPR_SR, SPR_SR_ICE)) {
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for (i = 0; i < config.ic.nways; i++) {
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for (i = 0; i < config.ic.nways; i++) {
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ic[set].way[i].tagaddr = -1;
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ic[set].way[i].tagaddr = -1;
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ic[set].way[i].lru = 0;
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ic[set].way[i].lru = 0;
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}
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}
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return;
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return;
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}
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}
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].tagaddr == tagaddr)
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if (ic[set].way[i].tagaddr == tagaddr)
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way = i;
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way = i;
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/* Did we find our cached data? */
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/* Did we find our cached data? */
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if (way >= 0) { /* Yes, we did. */
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if (way >= 0) { /* Yes, we did. */
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ic[set].way[way].tagaddr = -1;
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ic[set].way[way].tagaddr = -1;
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ic[set].way[way].lru = 0;
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ic[set].way[way].lru = 0;
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}
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}
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}
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}
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/*-----------------------------------------------------[ IC configuration ]---*/
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/*-----------------------------------------------------[ IC configuration ]---*/
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void ic_enabled(union param_val val, void *dat)
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void ic_enabled(union param_val val, void *dat)
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{
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{
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config.ic.enabled = val.int_val;
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config.ic.enabled = val.int_val;
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setsprbits (SPR_UPR, SPR_UPR_ICP, val.int_val ? 1 : 0);
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setsprbits (SPR_UPR, SPR_UPR_ICP, val.int_val ? 1 : 0);
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}
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}
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void ic_nsets(union param_val val, void *dat)
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void ic_nsets(union param_val val, void *dat)
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{
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{
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if (is_power2(val.int_val) && val.int_val <= MAX_IC_SETS){
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if (is_power2(val.int_val) && val.int_val <= MAX_IC_SETS){
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config.ic.nsets = val.int_val;
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config.ic.nsets = val.int_val;
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setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCS,log2(val.int_val));
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setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCS,log2(val.int_val));
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}
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}
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else {
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else {
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char tmp[200];
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char tmp[200];
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sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_IC_SETS);
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sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_IC_SETS);
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CONFIG_ERROR(tmp);
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CONFIG_ERROR(tmp);
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}
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}
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}
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}
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void ic_nways(union param_val val, void *dat)
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void ic_nways(union param_val val, void *dat)
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{
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{
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if (is_power2(val.int_val) && val.int_val <= MAX_IC_WAYS) {
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if (is_power2(val.int_val) && val.int_val <= MAX_IC_WAYS) {
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config.ic.nways = val.int_val;
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config.ic.nways = val.int_val;
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setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCW, log2(val.int_val));
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setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCW, log2(val.int_val));
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}
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}
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else {
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else {
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char tmp[200];
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char tmp[200];
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sprintf (tmp, "value of power of two and lower or equal than %i expected.",
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sprintf (tmp, "value of power of two and lower or equal than %i expected.",
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MAX_IC_WAYS);
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MAX_IC_WAYS);
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CONFIG_ERROR(tmp);
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CONFIG_ERROR(tmp);
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}
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}
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}
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}
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void ic_blocksize(union param_val val, void *dat)
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void ic_blocksize(union param_val val, void *dat)
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{
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{
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if (is_power2(val.int_val)){
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if (is_power2(val.int_val)){
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config.ic.blocksize = val.int_val;
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config.ic.blocksize = val.int_val;
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setsprbits (SPR_ICCFGR, SPR_ICCFGR_CBS,log2(val.int_val));
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setsprbits (SPR_ICCFGR, SPR_ICCFGR_CBS,log2(val.int_val));
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} else
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} else
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CONFIG_ERROR("value of power of two expected.");
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CONFIG_ERROR("value of power of two expected.");
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}
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}
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void ic_ustates(union param_val val, void *dat)
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void ic_ustates(union param_val val, void *dat)
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{
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{
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if (val.int_val >= 2 && val.int_val <= 4)
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if (val.int_val >= 2 && val.int_val <= 4)
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config.ic.ustates = val.int_val;
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config.ic.ustates = val.int_val;
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else
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else
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CONFIG_ERROR("invalid USTATE.");
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CONFIG_ERROR("invalid USTATE.");
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}
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}
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void ic_missdelay(union param_val val, void *dat)
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void ic_missdelay(union param_val val, void *dat)
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{
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{
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config.ic.missdelay = val.int_val;
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config.ic.missdelay = val.int_val;
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}
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}
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void ic_hitdelay(union param_val val, void *dat)
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void ic_hitdelay(union param_val val, void *dat)
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{
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{
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config.ic.hitdelay = val.int_val;
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config.ic.hitdelay = val.int_val;
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}
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}
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void reg_ic_sec(void)
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void reg_ic_sec(void)
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{
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{
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struct config_section *sec = reg_config_sec("ic", NULL, NULL);
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struct config_section *sec = reg_config_sec("ic", NULL, NULL);
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reg_config_param(sec, "enabled", paramt_int, ic_enabled);
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reg_config_param(sec, "enabled", paramt_int, ic_enabled);
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reg_config_param(sec, "nsets", paramt_int, ic_nsets);
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reg_config_param(sec, "nsets", paramt_int, ic_nsets);
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reg_config_param(sec, "nways", paramt_int, ic_nways);
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reg_config_param(sec, "nways", paramt_int, ic_nways);
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reg_config_param(sec, "blocksize", paramt_int, ic_blocksize);
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reg_config_param(sec, "blocksize", paramt_int, ic_blocksize);
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reg_config_param(sec, "ustates", paramt_int, ic_ustates);
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reg_config_param(sec, "ustates", paramt_int, ic_ustates);
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reg_config_param(sec, "missdelay", paramt_int, ic_missdelay);
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reg_config_param(sec, "missdelay", paramt_int, ic_missdelay);
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reg_config_param(sec, "hitdelay", paramt_int, ic_hitdelay);
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reg_config_param(sec, "hitdelay", paramt_int, ic_hitdelay);
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}
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}
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