/* abstract.c -- Abstract entities
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/* abstract.c -- Abstract entities
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Abstract memory and routines that go with this. I need to
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/* Abstract memory and routines that go with this. I need to
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add all sorts of other abstract entities. Currently we have
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add all sorts of other abstract entities. Currently we have
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only memory. */
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only memory. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <ctype.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "parse.h"
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#include "parse.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "labels.h"
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#include "labels.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "support/profile.h"
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#include "support/profile.h"
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#include "dmmu.h"
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#include "dmmu.h"
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#include "dcache_model.h"
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#include "dcache_model.h"
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#include "icache_model.h"
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#include "icache_model.h"
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#include "debug.h"
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#include "debug.h"
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#include "stats.h"
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#include "stats.h"
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extern char *disassembled;
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extern char *disassembled;
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/* Pointer to memory area descriptions that are assigned to individual
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/* Pointer to memory area descriptions that are assigned to individual
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peripheral devices. */
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peripheral devices. */
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struct dev_memarea *dev_list;
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struct dev_memarea *dev_list;
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/* Temporary variable to increase speed. */
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/* Temporary variable to increase speed. */
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struct dev_memarea *cur_area;
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struct dev_memarea *cur_area;
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/* Pointer to memory controller device descriptor. */
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/* Pointer to memory controller device descriptor. */
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struct dev_memarea *mc_area = (struct dev_memarea *)0;
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struct dev_memarea *mc_area = (struct dev_memarea *)0;
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/* These are set by mmu if cache inhibit bit is set for current acces. */
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/* These are set by mmu if cache inhibit bit is set for current acces. */
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int data_ci, insn_ci;
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int data_ci, insn_ci;
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/* Virtual address of current access. */
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/* Virtual address of current access. */
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oraddr_t cur_vadd;
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oraddr_t cur_vadd;
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/* Calculates bit mask to fit the data */
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/* Calculates bit mask to fit the data */
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unsigned int bit_mask (uint32_t data) {
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unsigned int bit_mask (uint32_t data) {
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int i = 0;
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int i = 0;
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data--;
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data--;
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while (data >> i)
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while (data >> i)
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data |= 1 << i++;
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data |= 1 << i++;
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return data;
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return data;
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}
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}
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/* Register read and write function for a memory area.
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/* Register read and write function for a memory area.
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addr is inside the area, if addr & addr_mask == addr_compare
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addr is inside the area, if addr & addr_mask == addr_compare
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(used also by peripheral devices like 16450 UART etc.) */
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(used also by peripheral devices like 16450 UART etc.) */
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void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
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void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
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uint32_t size, unsigned granularity, unsigned mc_dev,
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uint32_t size, unsigned granularity, unsigned mc_dev,
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uint32_t (readfunc)(oraddr_t, void *),
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uint32_t (readfunc)(oraddr_t, void *),
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void (writefunc)(oraddr_t, uint32_t, void *),
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void (writefunc)(oraddr_t, uint32_t, void *),
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void *dat)
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void *dat)
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{
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{
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struct dev_memarea **pptmp;
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struct dev_memarea **pptmp;
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unsigned int size_mask = bit_mask (size);
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unsigned int size_mask = bit_mask (size);
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int found_error = 0;
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int found_error = 0;
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addr_compare &= addr_mask;
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addr_compare &= addr_mask;
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debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
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debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
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addr_mask, addr_compare, addr_compare | bit_mask (size), size,
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addr_mask, addr_compare, addr_compare | bit_mask (size), size,
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granularity);
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granularity);
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/* Go to the end of the list. */
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/* Go to the end of the list. */
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for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
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for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
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if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
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if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
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|| (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
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|| (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
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if (!found_error) {
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if (!found_error) {
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fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
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fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
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fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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", size %08"PRIx32", gran %iB\n",
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", size %08"PRIx32", gran %iB\n",
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addr_mask, addr_compare, addr_compare | bit_mask (size), size,
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addr_mask, addr_compare, addr_compare | bit_mask (size), size,
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granularity);
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granularity);
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}
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}
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found_error = 1;
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found_error = 1;
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fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
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", size %08"PRIx32", gran %iB\n",
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", size %08"PRIx32", gran %iB\n",
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(*pptmp)->addr_mask, (*pptmp)->addr_compare,
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(*pptmp)->addr_mask, (*pptmp)->addr_compare,
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(*pptmp)->addr_compare | (*pptmp)->size_mask,
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(*pptmp)->addr_compare | (*pptmp)->size_mask,
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(*pptmp)->size, (*pptmp)->granularity);
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(*pptmp)->size, (*pptmp)->granularity);
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}
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}
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if (found_error)
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if (found_error)
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exit (-1);
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exit (-1);
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cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
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cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
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if (mc_dev)
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if (mc_dev)
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mc_area = *pptmp;
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mc_area = *pptmp;
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(*pptmp)->addr_mask = addr_mask;
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(*pptmp)->addr_mask = addr_mask;
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(*pptmp)->addr_compare = addr_compare;
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(*pptmp)->addr_compare = addr_compare;
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(*pptmp)->size = size;
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(*pptmp)->size = size;
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(*pptmp)->size_mask = size_mask;
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(*pptmp)->size_mask = size_mask;
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(*pptmp)->granularity = granularity;
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(*pptmp)->granularity = granularity;
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(*pptmp)->readfunc = readfunc;
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(*pptmp)->readfunc = readfunc;
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(*pptmp)->writefunc = writefunc;
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(*pptmp)->writefunc = writefunc;
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(*pptmp)->log = 0;
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(*pptmp)->log = 0;
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(*pptmp)->delayr = 2;
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(*pptmp)->delayr = 2;
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(*pptmp)->delayw = 2;
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(*pptmp)->delayw = 2;
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(*pptmp)->priv_dat = dat;
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(*pptmp)->priv_dat = dat;
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(*pptmp)->chip_select = -1;
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(*pptmp)->chip_select = -1;
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(*pptmp)->next = NULL;
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(*pptmp)->next = NULL;
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}
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}
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/* Register read and write function for a memory area.
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/* Register read and write function for a memory area.
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Memory areas should be aligned. Memory area is rounded up to
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Memory areas should be aligned. Memory area is rounded up to
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fit the nearest 2^n aligment.
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fit the nearest 2^n aligment.
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(used also by peripheral devices like 16450 UART etc.)
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(used also by peripheral devices like 16450 UART etc.)
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If mc_dev is 1, this means that this device will be checked first for match
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If mc_dev is 1, this means that this device will be checked first for match
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and will be accessed in case of overlaping memory spaces.
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and will be accessed in case of overlaping memory spaces.
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Only one device can have this set to 1 (used for memory controller) */
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Only one device can have this set to 1 (used for memory controller) */
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void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
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void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
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unsigned mc_dev,
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unsigned mc_dev,
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uint32_t (readfunc)(oraddr_t, void *),
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uint32_t (readfunc)(oraddr_t, void *),
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void (writefunc)(oraddr_t, uint32_t, void *),
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void (writefunc)(oraddr_t, uint32_t, void *),
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void *dat)
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void *dat)
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{
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{
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unsigned int size_mask = bit_mask (size);
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unsigned int size_mask = bit_mask (size);
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unsigned int addr_mask = ~size_mask;
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unsigned int addr_mask = ~size_mask;
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register_memoryarea_mask (addr_mask, addr & addr_mask,
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register_memoryarea_mask (addr_mask, addr & addr_mask,
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size_mask + 1, granularity, mc_dev,
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size_mask + 1, granularity, mc_dev,
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readfunc, writefunc, dat);
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readfunc, writefunc, dat);
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}
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}
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/* Check if access is to registered area of memory. */
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/* Check if access is to registered area of memory. */
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inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
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inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
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{
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{
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struct dev_memarea *ptmp;
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struct dev_memarea *ptmp;
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/* Check memory controller space first */
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/* Check memory controller space first */
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if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
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if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
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return cur_area = mc_area;
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return cur_area = mc_area;
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/* Check cached value */
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/* Check cached value */
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if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
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if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
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return cur_area;
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return cur_area;
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/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
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/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
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/* Check list of registered devices. */
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/* Check list of registered devices. */
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for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
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for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
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if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
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if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
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return cur_area = ptmp;
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return cur_area = ptmp;
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return cur_area = NULL;
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return cur_area = NULL;
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}
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}
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/* Finds the memory area for the address and adjust the read and write delays for it. */
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/* Finds the memory area for the address and adjust the read and write delays for it. */
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void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
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void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
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{
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{
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if (verify_memoryarea(memaddr)) {
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if (verify_memoryarea(memaddr)) {
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cur_area->delayr = delayr;
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cur_area->delayr = delayr;
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cur_area->delayw = delayw;
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cur_area->delayw = delayw;
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}
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}
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}
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}
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/* for cpu accesses
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/* for cpu accesses
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*
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*
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* STATISTICS: check cpu/common/parse.c
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* STATISTICS: check cpu/common/parse.c
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*/
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*/
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inline uint32_t evalsim_mem32(oraddr_t memaddr)
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inline uint32_t evalsim_mem32(oraddr_t memaddr)
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{
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{
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return(evalsim_mem32_atomic(memaddr, 1));
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return(evalsim_mem32_atomic(memaddr, 1));
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}
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}
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/* for simulator accesses, the ones that cpu wouldn't do */
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/* for simulator accesses, the ones that cpu wouldn't do */
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inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
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inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
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{
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{
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return(evalsim_mem32_atomic(memaddr, 0));
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return(evalsim_mem32_atomic(memaddr, 0));
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}
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}
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uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
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uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
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{
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{
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uint32_t temp = 0;
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uint32_t temp = 0;
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|
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if (verify_memoryarea(memaddr)) {
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if (verify_memoryarea(memaddr)) {
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switch(cur_area->granularity) {
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switch(cur_area->granularity) {
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case 4:
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case 4:
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
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break;
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break;
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case 1:
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case 1:
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
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temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
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temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
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temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
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temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
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temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
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temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
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break;
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break;
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case 2:
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case 2:
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
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temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
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temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
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break;
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break;
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default:
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default:
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/* if you add new memory granularity be sure to check the formula
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/* if you add new memory granularity be sure to check the formula
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* below for the read delay and fix it if necessery
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* below for the read delay and fix it if necessery
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*/
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*/
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PRINTF("unknown/unhandled memory granularuty\n");
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PRINTF("unknown/unhandled memory granularuty\n");
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exit(-1);
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exit(-1);
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}
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}
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if (cpu_access)
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if (cpu_access)
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runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
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runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
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}
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}
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return temp;
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return temp;
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}
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}
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|
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/* for cpu accesses */
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/* for cpu accesses */
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inline uint16_t evalsim_mem16(oraddr_t memaddr)
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inline uint16_t evalsim_mem16(oraddr_t memaddr)
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{
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{
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return(evalsim_mem16_atomic(memaddr, 1));
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return(evalsim_mem16_atomic(memaddr, 1));
|
}
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}
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|
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/* for simulator accesses, the ones that cpu wouldn't do */
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/* for simulator accesses, the ones that cpu wouldn't do */
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inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
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inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
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{
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{
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return(evalsim_mem16_atomic(memaddr, 0));
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return(evalsim_mem16_atomic(memaddr, 0));
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}
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}
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|
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uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
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uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
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{
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{
|
uint32_t temp = 0;
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uint32_t temp = 0;
|
|
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if (verify_memoryarea(memaddr)) {
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if (verify_memoryarea(memaddr)) {
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switch(cur_area->granularity) {
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switch(cur_area->granularity) {
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case 1:
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case 1:
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
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temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
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temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
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if (cpu_access)
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if (cpu_access)
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runtime.sim.mem_cycles += cur_area->delayr * 2;
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runtime.sim.mem_cycles += cur_area->delayr * 2;
|
break;
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break;
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case 2:
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case 2:
|
temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
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temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
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if (cpu_access)
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if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayr;
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runtime.sim.mem_cycles += cur_area->delayr;
|
break;
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break;
|
case 4:
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case 4:
|
temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
|
temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
|
if (memaddr & 2)
|
if (memaddr & 2)
|
temp &= 0xffff;
|
temp &= 0xffff;
|
else
|
else
|
temp >>= 16;
|
temp >>= 16;
|
break;
|
break;
|
default:
|
default:
|
/* if you add new memory granularity be sure to check the formula
|
/* if you add new memory granularity be sure to check the formula
|
* below for the read delay and fix it if necessery
|
* below for the read delay and fix it if necessery
|
*/
|
*/
|
PRINTF("unknown/unhandled memory granularuty\n");
|
PRINTF("unknown/unhandled memory granularuty\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
}
|
}
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for cpu accesses */
|
/* for cpu accesses */
|
inline uint8_t evalsim_mem8(oraddr_t memaddr)
|
inline uint8_t evalsim_mem8(oraddr_t memaddr)
|
{
|
{
|
return(evalsim_mem8_atomic(memaddr, 1));
|
return(evalsim_mem8_atomic(memaddr, 1));
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
|
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
|
{
|
{
|
return(evalsim_mem8_atomic(memaddr, 0));
|
return(evalsim_mem8_atomic(memaddr, 0));
|
}
|
}
|
|
|
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
|
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
|
{
|
{
|
uint32_t temp = 0;
|
uint32_t temp = 0;
|
|
|
if (verify_memoryarea(memaddr)) {
|
if (verify_memoryarea(memaddr)) {
|
switch(cur_area->granularity) {
|
switch(cur_area->granularity) {
|
case 1:
|
case 1:
|
temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
|
temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayr;
|
runtime.sim.mem_cycles += cur_area->delayr;
|
break;
|
break;
|
case 2:
|
case 2:
|
temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
|
temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
|
if (memaddr & 1)
|
if (memaddr & 1)
|
temp &= 0xff;
|
temp &= 0xff;
|
else
|
else
|
temp >>= 8;
|
temp >>= 8;
|
break;
|
break;
|
case 4:
|
case 4:
|
temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
|
temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
|
temp >>= 8 * (3 - (memaddr & 3));
|
temp >>= 8 * (3 - (memaddr & 3));
|
temp &= 0xff;
|
temp &= 0xff;
|
break;
|
break;
|
default:
|
default:
|
/* if you add new memory granularity be sure to check the formula
|
/* if you add new memory granularity be sure to check the formula
|
* below for the read delay and fix it if necessery
|
* below for the read delay and fix it if necessery
|
*/
|
*/
|
PRINTF("unknown/unhandled memory granularuty\n");
|
PRINTF("unknown/unhandled memory granularuty\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
}
|
}
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* Returns 32-bit values from mem array. Big endian version.
|
/* Returns 32-bit values from mem array. Big endian version.
|
*
|
*
|
* this function is only used in dumpmemory() below, so it's
|
* this function is only used in dumpmemory() below, so it's
|
* safe to asume it's for simulator purposes access only,
|
* safe to asume it's for simulator purposes access only,
|
* hence the use of eval_mem32_void()
|
* hence the use of eval_mem32_void()
|
*
|
*
|
* STATISTICS OK.
|
* STATISTICS OK.
|
*/
|
*/
|
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
|
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
temp = evalsim_mem32_void(memaddr);
|
temp = evalsim_mem32_void(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
} else if (cur_area->log)
|
} else if (cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* Returns 32-bit values from mem array. Big endian version.
|
/* Returns 32-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
|
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_READ);
|
mprofile (memaddr, MPROF_32 | MPROF_READ);
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
memaddr = dmmu_translate(memaddr, 0);
|
memaddr = dmmu_translate(memaddr, 0);
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.dc.enabled)
|
if (config.dc.enabled)
|
temp = dc_simulate_read(memaddr, 4);
|
temp = dc_simulate_read(memaddr, 4);
|
else {
|
else {
|
temp = evalsim_mem32(memaddr);
|
temp = evalsim_mem32(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do
|
/* for simulator accesses, the ones that cpu wouldn't do
|
*
|
*
|
* STATISTICS OK
|
* STATISTICS OK
|
*/
|
*/
|
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
|
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
|
int through_dc)
|
int through_dc)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
if (through_mmu)
|
if (through_mmu)
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
|
|
if (through_dc)
|
if (through_dc)
|
temp = dc_simulate_read(memaddr, 4);
|
temp = dc_simulate_read(memaddr, 4);
|
else {
|
else {
|
temp = evalsim_mem32_void(memaddr);
|
temp = evalsim_mem32_void(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
|
") in eval_direct32()\n", memaddr);
|
") in eval_direct32()\n", memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
|
|
return temp;
|
return temp;
|
}
|
}
|
|
|
|
|
/* Returns 32-bit values from mem array. Big endian version.
|
/* Returns 32-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
|
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_FETCH);
|
mprofile (memaddr, MPROF_32 | MPROF_FETCH);
|
// memaddr = simulate_ic_mmu_fetch(memaddr);
|
// memaddr = simulate_ic_mmu_fetch(memaddr);
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
memaddr = immu_translate(memaddr);
|
memaddr = immu_translate(memaddr);
|
|
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
|
|
|
if (config.ic.enabled)
|
if (config.ic.enabled)
|
temp = ic_simulate_fetch(memaddr);
|
temp = ic_simulate_fetch(memaddr);
|
else {
|
else {
|
temp = evalsim_mem32(memaddr);
|
temp = evalsim_mem32(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp);
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp);
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* Returns 16-bit values from mem array. Big endian version.
|
/* Returns 16-bit values from mem array. Big endian version.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
|
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
|
{
|
{
|
uint16_t temp;
|
uint16_t temp;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_16 | MPROF_READ);
|
mprofile (memaddr, MPROF_16 | MPROF_READ);
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
memaddr = dmmu_translate(memaddr, 0);
|
memaddr = dmmu_translate(memaddr, 0);
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.dc.enabled)
|
if (config.dc.enabled)
|
temp = (uint16_t)dc_simulate_read(memaddr, 2);
|
temp = (uint16_t)dc_simulate_read(memaddr, 2);
|
else {
|
else {
|
temp = evalsim_mem16(memaddr);
|
temp = evalsim_mem16(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do
|
/* for simulator accesses, the ones that cpu wouldn't do
|
*
|
*
|
* STATISTICS OK.
|
* STATISTICS OK.
|
*/
|
*/
|
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
|
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
|
int through_dc)
|
int through_dc)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
if (through_mmu)
|
if (through_mmu)
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
|
|
if (through_dc)
|
if (through_dc)
|
temp = dc_simulate_read(memaddr, 2);
|
temp = dc_simulate_read(memaddr, 2);
|
else {
|
else {
|
temp = evalsim_mem16_void(memaddr);
|
temp = evalsim_mem16_void(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
|
PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
|
") in eval_direct16()\n", memaddr);
|
") in eval_direct16()\n", memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
|
|
return temp;
|
return temp;
|
}
|
}
|
|
|
|
|
/* Returns 8-bit values from mem array.
|
/* Returns 8-bit values from mem array.
|
*
|
*
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
* STATISTICS OK (only used for cpu_access, that is architectural access)
|
*/
|
*/
|
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
|
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
|
{
|
{
|
uint8_t temp;
|
uint8_t temp;
|
|
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_8 | MPROF_READ);
|
mprofile (memaddr, MPROF_8 | MPROF_READ);
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
memaddr = dmmu_translate(memaddr, 0);
|
memaddr = dmmu_translate(memaddr, 0);
|
if (except_pending)
|
if (except_pending)
|
return 0;
|
return 0;
|
|
|
if (config.dc.enabled)
|
if (config.dc.enabled)
|
temp = (uint8_t)dc_simulate_read(memaddr, 1);
|
temp = (uint8_t)dc_simulate_read(memaddr, 1);
|
else {
|
else {
|
temp = evalsim_mem8(memaddr);
|
temp = evalsim_mem8(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
|
|
if (config.debug.enabled)
|
if (config.debug.enabled)
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
*breakpoint += CheckDebugUnit(DebugLoadData,temp); /* MM170901 */
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do
|
/* for simulator accesses, the ones that cpu wouldn't do
|
*
|
*
|
* STATISTICS OK.
|
* STATISTICS OK.
|
*/
|
*/
|
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
|
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
|
int through_dc)
|
int through_dc)
|
{
|
{
|
uint8_t temp;
|
uint8_t temp;
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
if (through_mmu)
|
if (through_mmu)
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
|
|
if (through_dc)
|
if (through_dc)
|
temp = (unsigned char)dc_simulate_read(memaddr, 1);
|
temp = (unsigned char)dc_simulate_read(memaddr, 1);
|
else {
|
else {
|
temp = evalsim_mem8_void(memaddr);
|
temp = evalsim_mem8_void(memaddr);
|
if (!cur_area) {
|
if (!cur_area) {
|
PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
|
PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
|
") in eval_direct8()\n", memaddr);
|
") in eval_direct8()\n", memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
temp = 0;
|
temp = 0;
|
}
|
}
|
}
|
}
|
return temp;
|
return temp;
|
}
|
}
|
|
|
/* for cpu accesses */
|
/* for cpu accesses */
|
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
|
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
|
{
|
{
|
return(setsim_mem32_atomic(memaddr, value, 1));
|
return(setsim_mem32_atomic(memaddr, value, 1));
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
|
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
|
{
|
{
|
return(setsim_mem32_atomic(memaddr, value, 0));
|
return(setsim_mem32_atomic(memaddr, value, 0));
|
}
|
}
|
|
|
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
|
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
|
{
|
{
|
if (verify_memoryarea(memaddr)) {
|
if (verify_memoryarea(memaddr)) {
|
switch(cur_area->granularity) {
|
switch(cur_area->granularity) {
|
case 4:
|
case 4:
|
cur_area->writefunc(memaddr, value, cur_area->priv_dat);
|
cur_area->writefunc(memaddr, value, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayw;
|
runtime.sim.mem_cycles += cur_area->delayw;
|
break;
|
break;
|
case 1:
|
case 1:
|
cur_area->writefunc(memaddr , (value >> 24) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr , (value >> 24) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 2, (value >> 8) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 2, (value >> 8) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 3, (value ) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 3, (value ) & 0xFF, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayw * 4;
|
runtime.sim.mem_cycles += cur_area->delayw * 4;
|
break;
|
break;
|
case 2:
|
case 2:
|
cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayw * 2;
|
runtime.sim.mem_cycles += cur_area->delayw * 2;
|
break;
|
break;
|
default:
|
default:
|
/* if you add new memory granularity be sure to check the formula
|
/* if you add new memory granularity be sure to check the formula
|
* below for the read delay and fix it if necessery
|
* below for the read delay and fix it if necessery
|
*/
|
*/
|
PRINTF("unknown/unhandled memory granularuty\n");
|
PRINTF("unknown/unhandled memory granularuty\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
} else {
|
} else {
|
PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
}
|
}
|
}
|
}
|
|
|
/* for cpu accesses */
|
/* for cpu accesses */
|
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
|
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
|
{
|
{
|
return(setsim_mem16_atomic(memaddr, value, 1));
|
return(setsim_mem16_atomic(memaddr, value, 1));
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
|
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
|
{
|
{
|
return(setsim_mem16_atomic(memaddr, value, 0));
|
return(setsim_mem16_atomic(memaddr, value, 0));
|
}
|
}
|
|
|
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
|
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
if (verify_memoryarea(memaddr)) {
|
if (verify_memoryarea(memaddr)) {
|
switch(cur_area->granularity) {
|
switch(cur_area->granularity) {
|
case 1:
|
case 1:
|
cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayw * 2;
|
runtime.sim.mem_cycles += cur_area->delayw * 2;
|
break;
|
break;
|
case 2:
|
case 2:
|
cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
|
cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayw;
|
runtime.sim.mem_cycles += cur_area->delayw;
|
break;
|
break;
|
case 4:
|
case 4:
|
temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
|
temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
|
temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
|
temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
|
temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
|
temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
|
setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
|
setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
|
break;
|
break;
|
default:
|
default:
|
/* if you add new memory granularity be sure to check the formula
|
/* if you add new memory granularity be sure to check the formula
|
* below for the read delay and fix it if necessery
|
* below for the read delay and fix it if necessery
|
*/
|
*/
|
PRINTF("unknown/unhandled memory granularuty\n");
|
PRINTF("unknown/unhandled memory granularuty\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
} else {
|
} else {
|
PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
}
|
}
|
}
|
}
|
|
|
/* for cpu accesses */
|
/* for cpu accesses */
|
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
|
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
|
{
|
{
|
return(setsim_mem8_atomic(memaddr, value, 1));
|
return(setsim_mem8_atomic(memaddr, value, 1));
|
}
|
}
|
|
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
/* for simulator accesses, the ones that cpu wouldn't do */
|
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
|
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
|
{
|
{
|
return(setsim_mem8_atomic(memaddr, value, 0));
|
return(setsim_mem8_atomic(memaddr, value, 0));
|
}
|
}
|
|
|
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
|
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
|
{
|
{
|
uint32_t temp;
|
uint32_t temp;
|
if (verify_memoryarea(memaddr)) {
|
if (verify_memoryarea(memaddr)) {
|
switch (cur_area->granularity) {
|
switch (cur_area->granularity) {
|
case 1:
|
case 1:
|
cur_area->writefunc(memaddr, value, cur_area->priv_dat);
|
cur_area->writefunc(memaddr, value, cur_area->priv_dat);
|
if (cpu_access)
|
if (cpu_access)
|
runtime.sim.mem_cycles += cur_area->delayw;
|
runtime.sim.mem_cycles += cur_area->delayw;
|
break;
|
break;
|
case 2:
|
case 2:
|
temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
|
temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
|
temp &= 0xff << ((memaddr & 1) ? 8 : 0);
|
temp &= 0xff << ((memaddr & 1) ? 8 : 0);
|
temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
|
temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
|
setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
|
setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
|
break;
|
break;
|
case 4:
|
case 4:
|
temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
|
temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
|
temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
|
temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
|
temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
|
temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
|
setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
|
setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
|
break;
|
break;
|
}
|
}
|
} else {
|
} else {
|
PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
|
PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
|
memaddr);
|
memaddr);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
}
|
}
|
}
|
}
|
|
|
/* Set mem, 32-bit. Big endian version.
|
/* Set mem, 32-bit. Big endian version.
|
*
|
*
|
* STATISTICS OK. (the only suspicious usage is in toplevel.c,
|
* STATISTICS OK. (the only suspicious usage is in toplevel.c,
|
* where this instruction is used for patching memory,
|
* where this instruction is used for patching memory,
|
* wether this is cpu or architectual access is yet to
|
* wether this is cpu or architectual access is yet to
|
* be decided)
|
* be decided)
|
*/
|
*/
|
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
|
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
|
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return;
|
return;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
memaddr = dmmu_translate(memaddr, 1);;
|
memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (except_pending)
|
if (except_pending)
|
return;
|
return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
dc_simulate_write(memaddr, value, 4);
|
dc_simulate_write(memaddr, value, 4);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
|
value);
|
value);
|
}
|
}
|
|
|
/*
|
/*
|
* STATISTICS NOT OK.
|
* STATISTICS NOT OK.
|
*/
|
*/
|
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
|
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
|
int through_mmu, int through_dc)
|
int through_mmu, int through_dc)
|
{
|
{
|
|
|
if (memaddr & 3) {
|
if (memaddr & 3) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return;
|
return;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
if (through_mmu) {
|
if (through_mmu) {
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
*/
|
*/
|
memaddr = peek_into_dtlb(memaddr, 1, through_dc);
|
memaddr = peek_into_dtlb(memaddr, 1, through_dc);
|
}
|
}
|
|
|
|
|
/* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
|
/* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
|
* and possibly also memory access times.
|
* and possibly also memory access times.
|
*/
|
*/
|
if (!through_dc)
|
if (!through_dc)
|
PRINTF("WARNING: statistics might not be OK\n");
|
PRINTF("WARNING: statistics might not be OK\n");
|
dc_simulate_write(memaddr, value, 4);
|
dc_simulate_write(memaddr, value, 4);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
|
memaddr, value);
|
memaddr, value);
|
}
|
}
|
|
|
|
|
/* Set mem, 16-bit. Big endian version. */
|
/* Set mem, 16-bit. Big endian version. */
|
|
|
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
|
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
|
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
except_handle (EXCEPT_ALIGN, memaddr);
|
except_handle (EXCEPT_ALIGN, memaddr);
|
return;
|
return;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
memaddr = dmmu_translate(memaddr, 1);;
|
memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (except_pending)
|
if (except_pending)
|
return;
|
return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
dc_simulate_write(memaddr, (unsigned long)value, 2);
|
dc_simulate_write(memaddr, (unsigned long)value, 2);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
|
value);
|
value);
|
}
|
}
|
|
|
/*
|
/*
|
* STATISTICS NOT OK.
|
* STATISTICS NOT OK.
|
*/
|
*/
|
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
|
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
|
int through_mmu, int through_dc)
|
int through_mmu, int through_dc)
|
{
|
{
|
|
|
if (memaddr & 1) {
|
if (memaddr & 1) {
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
|
return;
|
return;
|
}
|
}
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
if (through_mmu) {
|
if (through_mmu) {
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
*/
|
*/
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
}
|
}
|
|
|
/* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
|
/* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
|
* and possibly also memory access times.
|
* and possibly also memory access times.
|
*/
|
*/
|
if (!through_dc)
|
if (!through_dc)
|
PRINTF("WARNING: statistics might not be OK\n");
|
PRINTF("WARNING: statistics might not be OK\n");
|
dc_simulate_write(memaddr, value, 2);
|
dc_simulate_write(memaddr, value, 2);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
|
memaddr, value);
|
memaddr, value);
|
}
|
}
|
|
|
/* Set mem, 8-bit. */
|
/* Set mem, 8-bit. */
|
|
|
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
|
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
|
{
|
{
|
if (config.sim.mprofile)
|
if (config.sim.mprofile)
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
memaddr = dmmu_translate(memaddr, 1);;
|
memaddr = dmmu_translate(memaddr, 1);;
|
/* If we produced exception don't set anything */
|
/* If we produced exception don't set anything */
|
if (except_pending) return;
|
if (except_pending) return;
|
|
|
if (config.debug.enabled) {
|
if (config.debug.enabled) {
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
*breakpoint += CheckDebugUnit(DebugStoreData,value);
|
}
|
}
|
|
|
dc_simulate_write(memaddr, value, 1);
|
dc_simulate_write(memaddr, value, 1);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
|
value);
|
value);
|
}
|
}
|
|
|
/*
|
/*
|
* STATISTICS NOT OK.
|
* STATISTICS NOT OK.
|
*/
|
*/
|
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
|
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
|
int through_mmu, int through_dc)
|
int through_mmu, int through_dc)
|
{
|
{
|
|
|
cur_vadd = memaddr;
|
cur_vadd = memaddr;
|
|
|
if (through_mmu) {
|
if (through_mmu) {
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
/* 0 - no write access, we do not want a DPF exception do we ;)
|
*/
|
*/
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
memaddr = peek_into_dtlb(memaddr, 0, through_dc);
|
}
|
}
|
|
|
/* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
|
/* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
|
* and possibly also memory access times.
|
* and possibly also memory access times.
|
*/
|
*/
|
if (!through_dc)
|
if (!through_dc)
|
PRINTF("WARNING: statistics might not be OK\n");
|
PRINTF("WARNING: statistics might not be OK\n");
|
dc_simulate_write(memaddr, value, 1);
|
dc_simulate_write(memaddr, value, 1);
|
|
|
if (cur_area && cur_area->log)
|
if (cur_area && cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
|
memaddr, value);
|
memaddr, value);
|
}
|
}
|
|
|
|
|
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
|
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
|
{
|
{
|
oraddr_t i, j;
|
oraddr_t i, j;
|
struct label_entry *tmp;
|
struct label_entry *tmp;
|
int ilen = disasm ? 4 : 16;
|
int ilen = disasm ? 4 : 16;
|
|
|
for(i = from; i < to; i += ilen) {
|
for(i = from; i < to; i += ilen) {
|
PRINTF("%"PRIxADDR": ", i);
|
PRINTF("%"PRIxADDR": ", i);
|
for (j = 0; j < ilen;) {
|
for (j = 0; j < ilen;) {
|
if (!disasm) {
|
if (!disasm) {
|
tmp = NULL;
|
tmp = NULL;
|
if (verify_memoryarea(i + j)) {
|
if (verify_memoryarea(i + j)) {
|
struct label_entry *entry;
|
struct label_entry *entry;
|
entry = get_label(i + j);
|
entry = get_label(i + j);
|
if (entry)
|
if (entry)
|
PRINTF("(%s)", entry->name);
|
PRINTF("(%s)", entry->name);
|
PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
|
PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
|
} else PRINTF("XX ");
|
} else PRINTF("XX ");
|
j++;
|
j++;
|
} else {
|
} else {
|
int breakpoint;
|
int breakpoint;
|
uint32_t _insn = read_mem(i, &breakpoint);
|
uint32_t _insn = read_mem(i, &breakpoint);
|
int index = insn_decode (_insn);
|
int index = insn_decode (_insn);
|
int len = insn_len (index);
|
int len = insn_len (index);
|
|
|
tmp = NULL;
|
tmp = NULL;
|
if (verify_memoryarea(i + j)) {
|
if (verify_memoryarea(i + j)) {
|
struct label_entry *entry;
|
struct label_entry *entry;
|
entry = get_label(i + j);
|
entry = get_label(i + j);
|
if (entry)
|
if (entry)
|
PRINTF("(%s)", entry->name);
|
PRINTF("(%s)", entry->name);
|
|
|
PRINTF(": %08"PRIx32" ", _insn);
|
PRINTF(": %08"PRIx32" ", _insn);
|
if (index >= 0) {
|
if (index >= 0) {
|
disassemble_insn (_insn);
|
disassemble_insn (_insn);
|
PRINTF(" %s", disassembled);
|
PRINTF(" %s", disassembled);
|
} else
|
} else
|
PRINTF("<invalid>");
|
PRINTF("<invalid>");
|
} else PRINTF("XXXXXXXX");
|
} else PRINTF("XXXXXXXX");
|
j += len;
|
j += len;
|
}
|
}
|
}
|
}
|
if (nl)
|
if (nl)
|
PRINTF ("\n");
|
PRINTF ("\n");
|
}
|
}
|
}
|
}
|
|
|
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
|
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
|
return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
|
return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
|
}
|
}
|
|
|
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
|
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
|
*(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
|
*(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
|
}
|
}
|
|
|
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
|
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
|
if (config.sim.verbose)
|
if (config.sim.verbose)
|
fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
|
fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
|
PRIxADDR".\n", addr);
|
PRIxADDR".\n", addr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
|
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
|
if (config.sim.verbose)
|
if (config.sim.verbose)
|
fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
|
fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
|
}
|
}
|
|
|
/* Initialize memory table from a config struct */
|
/* Initialize memory table from a config struct */
|
|
|
void init_memory_table ()
|
void init_memory_table ()
|
{
|
{
|
/* If nothing was defined, use default memory block */
|
/* If nothing was defined, use default memory block */
|
if (config.memory.nmemories) {
|
if (config.memory.nmemories) {
|
int i;
|
int i;
|
for (i = 0; i < config.memory.nmemories; i++) {
|
for (i = 0; i < config.memory.nmemories; i++) {
|
oraddr_t start = config.memory.table[i].baseaddr;
|
oraddr_t start = config.memory.table[i].baseaddr;
|
uint32_t length = config.memory.table[i].size;
|
uint32_t length = config.memory.table[i].size;
|
char *type = config.memory.table[i].name;
|
char *type = config.memory.table[i].name;
|
int rd = config.memory.table[i].delayr;
|
int rd = config.memory.table[i].delayr;
|
int wd = config.memory.table[i].delayw;
|
int wd = config.memory.table[i].delayw;
|
int ce = config.memory.table[i].ce;
|
int ce = config.memory.table[i].ce;
|
void *mem = malloc (length);
|
void *mem = malloc (length);
|
|
|
if (config.sim.verbose)
|
if (config.sim.verbose)
|
debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
|
debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
|
start, length, length >> 10, type, ce, rd, wd);
|
start, length, length >> 10, type, ce, rd, wd);
|
|
|
if (!mem) {
|
if (!mem) {
|
fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
|
fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
|
|
register_memoryarea(start, length, 4, 0, &simmem_read_word,
|
register_memoryarea(start, length, 4, 0, &simmem_read_word,
|
&simmem_write_word, mem);
|
&simmem_write_word, mem);
|
cur_area->chip_select = ce;
|
cur_area->chip_select = ce;
|
cur_area->valid = 1;
|
cur_area->valid = 1;
|
cur_area->delayw = wd;
|
cur_area->delayw = wd;
|
cur_area->delayr = rd;
|
cur_area->delayr = rd;
|
if (config.memory.table[i].log[0] != '\0') {
|
if (config.memory.table[i].log[0] != '\0') {
|
if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
|
if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
|
fprintf (stderr, "WARNING: Cannot open '%s'.\n",
|
fprintf (stderr, "WARNING: Cannot open '%s'.\n",
|
config.memory.table[i].log);
|
config.memory.table[i].log);
|
} else
|
} else
|
cur_area->log = NULL;
|
cur_area->log = NULL;
|
}
|
}
|
PRINTF ("\n");
|
PRINTF ("\n");
|
} else {
|
} else {
|
void *mem = malloc (DEFAULT_MEMORY_LEN);
|
void *mem = malloc (DEFAULT_MEMORY_LEN);
|
if (config.sim.verbose)
|
if (config.sim.verbose)
|
fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
|
fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
|
|
|
if (!mem) {
|
if (!mem) {
|
fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
|
fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
|
|
register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
|
register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
|
&simmem_read_word, &simmem_write_word, mem);
|
&simmem_read_word, &simmem_write_word, mem);
|
cur_area->chip_select = 0;
|
cur_area->chip_select = 0;
|
cur_area->valid = 1;
|
cur_area->valid = 1;
|
cur_area->delayw = 1;
|
cur_area->delayw = 1;
|
cur_area->delayr = 1;
|
cur_area->delayr = 1;
|
cur_area->log = NULL;
|
cur_area->log = NULL;
|
}
|
}
|
}
|
}
|
|
|
/* Changes read/write memory in read/write only */
|
/* Changes read/write memory in read/write only */
|
|
|
void lock_memory_table ()
|
void lock_memory_table ()
|
{
|
{
|
struct dev_memarea *ptmp;
|
struct dev_memarea *ptmp;
|
|
|
/* Check list of registered devices. */
|
/* Check list of registered devices. */
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
|
if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
|
ptmp->readfunc = &simmem_read_zero;
|
ptmp->readfunc = &simmem_read_zero;
|
if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
|
if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
|
ptmp->writefunc = &simmem_write_null;
|
ptmp->writefunc = &simmem_write_null;
|
|
|
/* If this mem area is not for memory chip under MC control
|
/* If this mem area is not for memory chip under MC control
|
then this area is valid all the time */
|
then this area is valid all the time */
|
if (ptmp->readfunc != &simmem_read_word) {
|
if (ptmp->readfunc != &simmem_read_word) {
|
ptmp->valid = 1;
|
ptmp->valid = 1;
|
ptmp->chip_select = -1;
|
ptmp->chip_select = -1;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Closes files, etc. */
|
/* Closes files, etc. */
|
|
|
void done_memory_table ()
|
void done_memory_table ()
|
{
|
{
|
struct dev_memarea *ptmp;
|
struct dev_memarea *ptmp;
|
|
|
/* Check list of registered devices. */
|
/* Check list of registered devices. */
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
if (ptmp->log)
|
if (ptmp->log)
|
fclose (ptmp->log);
|
fclose (ptmp->log);
|
}
|
}
|
}
|
}
|
|
|
/* Displays current memory configuration */
|
/* Displays current memory configuration */
|
|
|
void memory_table_status ()
|
void memory_table_status ()
|
{
|
{
|
struct dev_memarea *ptmp;
|
struct dev_memarea *ptmp;
|
|
|
/* Check list of registered devices. */
|
/* Check list of registered devices. */
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
|
PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
|
PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
|
", gran %iB\n",
|
", gran %iB\n",
|
ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
|
ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
|
ptmp->size, ptmp->granularity);
|
ptmp->size, ptmp->granularity);
|
PRINTF ("\t");
|
PRINTF ("\t");
|
if (ptmp->delayr >= 0)
|
if (ptmp->delayr >= 0)
|
PRINTF ("read delay = %i cycles, ", ptmp->delayr);
|
PRINTF ("read delay = %i cycles, ", ptmp->delayr);
|
else
|
else
|
PRINTF ("reads not possible, ");
|
PRINTF ("reads not possible, ");
|
|
|
if (ptmp->delayw >= 0)
|
if (ptmp->delayw >= 0)
|
PRINTF ("write delay = %i cycles", ptmp->delayw);
|
PRINTF ("write delay = %i cycles", ptmp->delayw);
|
else
|
else
|
PRINTF ("writes not possible");
|
PRINTF ("writes not possible");
|
|
|
if (ptmp->log)
|
if (ptmp->log)
|
PRINTF (", (logged)\n");
|
PRINTF (", (logged)\n");
|
else
|
else
|
PRINTF ("\n");
|
PRINTF ("\n");
|
}
|
}
|
}
|
}
|
|
|
/* Outputs time in pretty form to dest string */
|
/* Outputs time in pretty form to dest string */
|
|
|
char *generate_time_pretty (char *dest, long time_ps)
|
char *generate_time_pretty (char *dest, long time_ps)
|
{
|
{
|
int exp3 = 0;
|
int exp3 = 0;
|
if (time_ps) {
|
if (time_ps) {
|
while ((time_ps % 1000) == 0) {
|
while ((time_ps % 1000) == 0) {
|
time_ps /= 1000;
|
time_ps /= 1000;
|
exp3++;
|
exp3++;
|
}
|
}
|
}
|
}
|
sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
|
sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
|
return dest;
|
return dest;
|
}
|
}
|
|
|
