/* except.c -- Simulation of OR1K exceptions
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/* except.c -- Simulation of OR1K exceptions
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "execute.h"
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#include "execute.h"
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extern int delay_insn;
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extern int delay_insn;
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extern oraddr_t pcprev;
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extern oraddr_t pcprev;
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extern oraddr_t pcdelay;
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extern oraddr_t pcdelay;
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int except_pending = 0;
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int except_pending = 0;
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static const char *except_names[] = {
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static const char *except_names[] = {
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NULL,
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NULL,
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"Reset",
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"Reset",
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"Bus Error",
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"Bus Error",
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"Data Page Fault",
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"Data Page Fault",
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"Insn Page Fault",
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"Insn Page Fault",
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"Tick timer",
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"Tick timer",
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"Alignment",
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"Alignment",
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"Illegal instruction",
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"Illegal instruction",
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"Interrupt",
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"Interrupt",
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"Data TLB Miss",
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"Data TLB Miss",
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"Insn TLB Miss",
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"Insn TLB Miss",
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"Range",
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"Range",
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"System Call",
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"System Call",
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"Trap" };
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"Trap" };
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static const char *except_name(oraddr_t except)
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static const char *except_name(oraddr_t except)
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{
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{
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return except_names[except >> 8];
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return except_names[except >> 8];
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}
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}
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/* Asserts OR1K exception. */
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/* Asserts OR1K exception. */
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void except_handle(oraddr_t except, oraddr_t ea)
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void except_handle(oraddr_t except, oraddr_t ea)
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{
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{
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if(debug_ignore_exception (except))
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if(debug_ignore_exception (except))
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return;
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return;
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except_pending = 1;
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except_pending = 1;
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if (config.sim.verbose)
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if (config.sim.verbose)
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR
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", cycles %lld, #%lld\n",
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", cycles %lld, #%lld\n",
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except, except_name(except), pcprev, ea, pc, pcnext, pcdelay,
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except, except_name(except), pcprev, ea, pc, pcnext, pcdelay,
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runtime.sim.cycles, runtime.cpu.instructions);
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runtime.sim.cycles, runtime.cpu.instructions);
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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pcnext = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000);
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switch(except) {
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switch(except) {
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/* EPCR is irrelevent */
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/* EPCR is irrelevent */
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case EXCEPT_RESET:
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case EXCEPT_RESET:
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break;
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break;
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/* EPCR is loaded with address of instruction that caused the exception */
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/* EPCR is loaded with address of instruction that caused the exception */
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/* All these exceptions happen during a simulated instruction */
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/* All these exceptions happen during a simulated instruction */
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case EXCEPT_BUSERR:
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case EXCEPT_BUSERR:
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case EXCEPT_DPF:
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case EXCEPT_DPF:
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case EXCEPT_IPF:
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case EXCEPT_IPF:
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case EXCEPT_ALIGN:
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case EXCEPT_ALIGN:
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case EXCEPT_ILLEGAL:
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case EXCEPT_ILLEGAL:
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case EXCEPT_DTLBMISS:
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case EXCEPT_DTLBMISS:
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case EXCEPT_ITLBMISS:
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case EXCEPT_ITLBMISS:
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case EXCEPT_RANGE:
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case EXCEPT_RANGE:
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case EXCEPT_TRAP:
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case EXCEPT_TRAP:
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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break;
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break;
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/* EPCR is loaded with address of next not-yet-executed instruction */
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/* EPCR is loaded with address of next not-yet-executed instruction */
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case EXCEPT_SYSCALL:
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case EXCEPT_SYSCALL:
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mtspr(SPR_EPCR_BASE, (pc + 4) - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, (pc + 4) - (delay_insn ? 4 : 0));
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break;
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break;
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/* These exceptions happen AFTER (or before) an instruction has been
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/* These exceptions happen AFTER (or before) an instruction has been
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* simulated, therefore the pc already points to the *next* instruction */
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* simulated, therefore the pc already points to the *next* instruction */
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case EXCEPT_TICK:
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case EXCEPT_TICK:
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case EXCEPT_INT:
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case EXCEPT_INT:
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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mtspr(SPR_EPCR_BASE, pc - (delay_insn ? 4 : 0));
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/* If we don't update the pc now, then it will only happen *after* the next
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/* If we don't update the pc now, then it will only happen *after* the next
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* instruction (There would be serious problems if the next instruction just
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* instruction (There would be serious problems if the next instruction just
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* happens to be a branch), when it should happen NOW. */
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* happens to be a branch), when it should happen NOW. */
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pc = pcnext;
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pc = pcnext;
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pcnext += 4;
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pcnext += 4;
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break;
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break;
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}
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}
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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/* Address translation is always disabled when starting exception. */
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/* Address translation is always disabled when starting exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SM); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE | SPR_SR_TEE)); /* Disable interrupts. */
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delay_insn = 0;
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delay_insn = 0;
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}
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}
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