/* except.c -- Simulation of OR1K exceptions
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/* except.c -- Simulation of OR1K exceptions
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "abstract.h"
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#include "abstract.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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static void except_handle_backend(int,unsigned long,unsigned long);
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extern int cont_run;
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extern int cont_run;
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extern struct iqueue_entry iqueue[20];
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extern struct iqueue_entry iqueue[20];
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extern unsigned long pc;
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extern unsigned long pc;
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extern unsigned long pcnext;
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extern unsigned long pcnext;
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extern unsigned long pc_phy;
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extern unsigned long pc_phy;
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extern struct iqueue_entry iqueue[];
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extern struct iqueue_entry iqueue[];
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extern int delay_insn;
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extern int delay_insn;
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int cycle_delay = 0; /* Added by CZ 27/05/01 */
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int cycle_delay = 0; /* Added by CZ 27/05/01 */
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struct _pending pending;
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struct _pending pending;
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void ClearPendingException()
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/* Discards all pending exceptions */
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{
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void clear_pending_exception()
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if(pending.valid && pending.type != EXCEPT_RESET)
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{
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{
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pending.valid = 0;
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pending.valid = 0;
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pending.type = 0;
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pending.type = 0;
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pending.address = 0;
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pending.address = 0;
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pending.saved = 0;
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pending.saved = 0;
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}
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}
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}
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/* The delayed_pc and delayed_pcnext are fields which hold
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the original value of the PC across breakpoint exceptions
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in the case of a development interface. Due to an implementation
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issues, DIR injected instructions can modify these values
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when in fact they should not. So we save and restore them
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later on. */
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static unsigned long delayed_pc = 0;
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static unsigned long delayed_pcnext = 0;
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static int delayed_pc_valid = 0;
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void ClearPreparedPCState()
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{
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delayed_pc_valid = 0;
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}
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/* This routine is never called if the cpu is not stalled...
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i.e. cpu_stalled == 0. _execute_update_pc is called
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directly in that case. This routine exists to sort out
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the difference between a single step break and a full
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software break. */
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void PrepareExceptionPC(unsigned long t_pc,unsigned long t_pcnext)
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{
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/* If a real exception occurred which has stalled
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the CPU, we are expecting to halt before the end
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of the instruction. Otherwise, if it is a single
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step that has caused the halt, we are expected to
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complete the entire instruction and stop after
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it is finished. */
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if(pending.valid)
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/* Asserts OR1K exception. */
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{
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delayed_pc = t_pc;
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delayed_pcnext = t_pcnext;
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delayed_pc_valid = 1;
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}
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else
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_execute_update_pc(t_pc,t_pcnext);
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}
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void PrepareException()
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{
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if(delayed_pc_valid)
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{
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pc = delayed_pc;
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pcnext = delayed_pcnext;
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pc_phy = simulate_ic_mmu_fetch(pc);
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if (verify_memoryarea(pc_phy))
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except_handle(EXCEPT_BUSERR, pc);
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delayed_pc_valid = delayed_pc = delayed_pcnext = 0;
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}
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if(pending.valid)
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except_handle_backend(pending.type,pending.address,pending.saved);
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}
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/* Handle OR1K exceptions. */
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void except_handle(int except, unsigned long ea)
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void except_handle(int except, unsigned long ea)
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{
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{
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if(debug_ignore_exception (except)) {
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clear_pending_exception ();
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} else {
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pending.valid = 1;
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pending.valid = 1;
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pending.type = except;
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pending.type = except;
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pending.address = ea;
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pending.address = ea;
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if (delay_insn)
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if (delay_insn)
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pending.saved = pc - 4;
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pending.saved = pc - 4;
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else
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else
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pending.saved = pc;
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pending.saved = pc;
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printf("Exception 0x%x (%s): insn_addr 0x%x, EA 0x%x, pc: 0x%x, pcnext: 0x%x\n",
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if(DebugCheckException(except))
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except, EXCEPT_NAME(except), iqueue[0].insn_addr, ea, pc, pcnext);
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{
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pending.valid = 0;
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pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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}
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else
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{
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printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));
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printf("Iqueue[0].insn_addr: 0x%x Eff ADDR: 0x%x\n", iqueue[0].insn_addr, ea);
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printf(" pc: 0x%x pcnext: 0x%x\n", pc, pcnext);
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}
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}
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cycle_delay = 0; /* An exception stalls the CPU 0 clock cycles */
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cycle_delay = 0; /* An exception stalls the CPU 0 clock cycles */
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}
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}
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static void except_handle_backend(int except, unsigned long ea, unsigned long pc_saved)
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/* Actually handles exception */
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void except_handle_backend (int except, unsigned long ea, unsigned long pc_saved)
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{
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{
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/* Ignore masked exceptions */
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/* Ignore masked exceptions */
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if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
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if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {
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if (config.sim.verbose)
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if (config.sim.verbose)
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printf("INFO: Exception occured while exception detection was disabled.\n");
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printf("INFO: Exception occured while exception detection was disabled.\n");
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return;
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return;
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}
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}
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#if ONLY_VIRTUAL_MACHINE
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#if ONLY_VIRTUAL_MACHINE
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fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");
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cont_run = 0;
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cont_run = 0;
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#else
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#else
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if (delay_insn) {
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if (delay_insn) {
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printf("INFO: Exception during execution of delay slot insn.\n");
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printf("INFO: Exception during execution of delay slot insn.\n");
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pc -= 4;
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pc -= 4;
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}
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}
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#if 0
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#if 0
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if ((pcnext != (pc + 4)) && (except != EXCEPT_ITLBMISS)) { /* Always execute delay slot insn */
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if ((pcnext != (pc + 4)) && (except != EXCEPT_ITLBMISS)) { /* Always execute delay slot insn */
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printf("XXXXXXXXXXXXXX\n");
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printf("XXXXXXXXXXXXXX\n");
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fetch(); /* before starting with exception */
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fetch(); /* before starting with exception */
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decode(&iqueue[0]); /* (itlbmiss is special case) */
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decode(&iqueue[0]); /* (itlbmiss is special case) */
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execute();
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execute();
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}
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}
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#endif
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#endif
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pc_saved = pc & ~0x3;
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pc_saved = pc & ~0x3;
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if (except == EXCEPT_ILLEGAL)
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if (except == EXCEPT_ILLEGAL)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_ALIGN)
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else if (except == EXCEPT_ALIGN)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_DTLBMISS)
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else if (except == EXCEPT_DTLBMISS)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_DPF)
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else if (except == EXCEPT_DPF)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_BUSERR)
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else if (except == EXCEPT_BUSERR)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_TRAP)
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else if (except == EXCEPT_TRAP)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else if (except == EXCEPT_RANGE)
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else if (except == EXCEPT_RANGE)
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mtspr(SPR_EPCR_BASE, pending.saved);
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mtspr(SPR_EPCR_BASE, pending.saved);
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else
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else
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mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EPCR_BASE, pc_saved);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_EEAR_BASE, ea);
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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mtspr(SPR_ESR_BASE, mfspr(SPR_SR));
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/* Address translation is always disabled when starting exception. */
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/* Address translation is always disabled when starting exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE); /* Disable overflow flag exception. */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV); /* SUPV mode */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR); /* Disable interrupts. */
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mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR); /* Disable interrupts. */
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pending.valid = 0;
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clear_pending_exception ();
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pending.type = 0;
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pending.address = 0;
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pending.saved = 0;
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pc = (unsigned long)except;
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pc = (unsigned long)except;
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/* This has been removed. All exceptions (not just SYSCALL) suffer
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/* This has been removed. All exceptions (not just SYSCALL) suffer
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from the same problem. The solution is to continue just like
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from the same problem. The solution is to continue just like
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the pipeline would, and issue the exception on the next
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the pipeline would, and issue the exception on the next
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clock cycle. We assume now that this function is being called
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clock cycle. We assume now that this function is being called
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->BEFORE<- the instruction fetch and after the previous update
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->BEFORE<- the instruction fetch and after the previous update
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which always yields the correct behavior. This has the added
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which always yields the correct behavior. This has the added
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advantage that a debugger can prevent an exception from
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advantage that a debugger can prevent an exception from
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taking place by resetting the pc. */
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taking place by resetting the pc. */
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#if 0
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#if 0
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/* MM: We do pc update after the execute (in the simulator), so we
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/* MM: We do pc update after the execute (in the simulator), so we
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decrease it by 4 so that next instruction points to first exception
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decrease it by 4 so that next instruction points to first exception
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instruction. Do NOT comment this out. */
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instruction. Do NOT comment this out. */
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if (except == EXCEPT_SYSCALL)
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if (except == EXCEPT_SYSCALL)
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pc -= 4;
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pc -= 4;
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#endif
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#endif
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pcnext = pc+4;
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pcnext = pc + 4;
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/* Added by CZ 27/05/01 */
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/* Added by CZ 27/05/01 */
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pc_phy = pc; /* An exception always turns off the MMU, so
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pc_phy = pc; /* An exception always turns off the MMU, so
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pc is always pc_phy */
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pc is always pc_phy */
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#endif
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#endif
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}
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}
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