OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [or1k/] [except.h] - Diff between revs 1386 and 1419

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 1386 Rev 1419
/* except.h -- OR1K architecture specific exceptions
/* except.h -- OR1K architecture specific exceptions
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
 
This file is part of OpenRISC 1000 Architectural Simulator.
This file is part of OpenRISC 1000 Architectural Simulator.
 
 
This program is free software; you can redistribute it and/or modify
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
(at your option) any later version.
 
 
This program is distributed in the hope that it will be useful,
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
GNU General Public License for more details.
 
 
You should have received a copy of the GNU General Public License
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
#ifndef _EXCEPT_H_
#ifndef _EXCEPT_H_
#define _EXCEPT_H_
#define _EXCEPT_H_
 
 
/* Define if you want pure virtual machine simulation (no exceptions etc.) */
/* Define if you want pure virtual machine simulation (no exceptions etc.) */
#define ONLY_VIRTUAL_MACHINE 0
#define ONLY_VIRTUAL_MACHINE 0
 
 
/* Definition of OR1K exceptions */
/* Definition of OR1K exceptions */
 
 
#define EXCEPT_RESET    0x0100
#define EXCEPT_RESET    0x0100
#define EXCEPT_BUSERR   0x0200
#define EXCEPT_BUSERR   0x0200
#define EXCEPT_DPF      0x0300
#define EXCEPT_DPF      0x0300
#define EXCEPT_IPF      0x0400
#define EXCEPT_IPF      0x0400
#define EXCEPT_TICK     0x0500
#define EXCEPT_TICK     0x0500
#define EXCEPT_ALIGN    0x0600
#define EXCEPT_ALIGN    0x0600
#define EXCEPT_ILLEGAL  0x0700
#define EXCEPT_ILLEGAL  0x0700
#define EXCEPT_INT      0x0800
#define EXCEPT_INT      0x0800
#define EXCEPT_DTLBMISS 0x0900
#define EXCEPT_DTLBMISS 0x0900
#define EXCEPT_ITLBMISS 0x0a00
#define EXCEPT_ITLBMISS 0x0a00
#define EXCEPT_RANGE    0x0b00
#define EXCEPT_RANGE    0x0b00
#define EXCEPT_SYSCALL  0x0c00
#define EXCEPT_SYSCALL  0x0c00
#define EXCEPT_TRAP     0x0e00
#define EXCEPT_TRAP     0x0e00
 
 
/* Non maskable exceptions */
/* Non maskable exceptions */
#define IS_NME(E) ((E) == EXCEPT_RESET)
#define IS_NME(E) ((E) == EXCEPT_RESET)
 
 
/* Prototypes */
/* Prototypes */
void except_handle(oraddr_t except, oraddr_t ea);
void except_handle(oraddr_t except, oraddr_t ea);
 
 
/* Has an exception been raised in this cycle ? */
/* Has an exception been raised in this cycle ? */
extern int except_pending;
extern int except_pending;
 
 
#endif
#endif
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.