/* debug_unit.c -- Simulation of Or1k debug unit
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/* debug_unit.c -- Simulation of Or1k debug unit
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/*
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/*
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This is an architectural level simulation of the Or1k debug
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This is an architectural level simulation of the Or1k debug
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unit as described in OpenRISC 1000 System Architecture Manual,
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unit as described in OpenRISC 1000 System Architecture Manual,
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v. 0.1 on 22 April, 2001. This unit is described in Section 13.
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v. 0.1 on 22 April, 2001. This unit is described in Section 13.
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Every attempt has been made to be as accurate as possible with
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Every attempt has been made to be as accurate as possible with
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respect to the registers and the behavior. There are no known
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respect to the registers and the behavior. There are no known
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limitations at this time.
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limitations at this time.
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*/
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*/
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//#define DEBUG_JTAG 0
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//#define DEBUG_JTAG 0
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "except.h"
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#include "except.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "parse.h"
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#include "parse.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "gdb.h"
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#include "gdb.h"
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#include "except.h"
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#include "except.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "debug.h"
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#include "debug.h"
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DevelopmentInterface development;
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DevelopmentInterface development;
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/* External STALL signal to debug interface */
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/* External STALL signal to debug interface */
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int in_reset = 0;
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int in_reset = 0;
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/* Current watchpoint state */
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/* Current watchpoint state */
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unsigned long watchpoints = 0;
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unsigned long watchpoints = 0;
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static int calculate_watchpoints(DebugUnitAction action, unsigned long udata);
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static int calculate_watchpoints(DebugUnitAction action, unsigned long udata);
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void set_stall_state(int state)
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void set_stall_state(int state)
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{
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{
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development.riscop &= ~RISCOP_STALL;
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development.riscop &= ~RISCOP_STALL;
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development.riscop |= state ? RISCOP_STALL : 0;
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development.riscop |= state ? RISCOP_STALL : 0;
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if(testsprbits(SPR_DMR1, SPR_DMR1_DXFW)) /* If debugger disabled */
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if(testsprbits(SPR_DMR1, SPR_DMR1_DXFW)) /* If debugger disabled */
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state = 0;
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state = 0;
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runtime.cpu.stalled = state;
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runtime.cpu.stalled = state;
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}
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}
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void du_reset()
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void du_reset()
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{
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{
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development.riscop = 0;
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development.riscop = 0;
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set_stall_state (0);
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set_stall_state (0);
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}
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}
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void du_clock()
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void du_clock()
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{
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{
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watchpoints=0;
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watchpoints=0;
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};
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};
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int CheckDebugUnit(DebugUnitAction action, unsigned long udata)
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int CheckDebugUnit(DebugUnitAction action, unsigned long udata)
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{
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{
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/* Do not stop, if we have debug module disabled or during reset */
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/* Do not stop, if we have debug module disabled or during reset */
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if(!config.debug.enabled || in_reset)
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if(!config.debug.enabled || in_reset)
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return 0;
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return 0;
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/* If we're single stepping, always stop */
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/* If we're single stepping, always stop */
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if((action == DebugInstructionFetch) && testsprbits (SPR_DMR1, SPR_DMR1_ST))
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if((action == DebugInstructionFetch) && testsprbits (SPR_DMR1, SPR_DMR1_ST))
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return 1;
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return 1;
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/* is any watchpoint enabled to generate a break or count? If not, ignore */
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/* is any watchpoint enabled to generate a break or count? If not, ignore */
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if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
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if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC))
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return calculate_watchpoints(action, udata);
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return calculate_watchpoints(action, udata);
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return 0;
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return 0;
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}
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}
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/* Checks whether we should stall the RISC or cause an exception */
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/* Checks whether we should stall the RISC or cause an exception */
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static int calculate_watchpoints(DebugUnitAction action, unsigned long udata)
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static int calculate_watchpoints(DebugUnitAction action, unsigned long udata)
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{
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{
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int breakpoint = 0;
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int breakpoint = 0;
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int i, bit;
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int i, bit;
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/* Hopefully this loop would be unrolled run at max. speed */
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/* Hopefully this loop would be unrolled run at max. speed */
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for(i = 0, bit = 1; i < 11; i++, bit <<= 1) {
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for(i = 0, bit = 1; i < 11; i++, bit <<= 1) {
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int chain1, chain2;
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int chain1, chain2;
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int match = 0;
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int match = 0;
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int DCR_hit = 0;
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int DCR_hit = 0;
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/* Calculate first 8 matchpoints, result is put into DCR_hit */
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/* Calculate first 8 matchpoints, result is put into DCR_hit */
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if (i < 8) {
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if (i < 8) {
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unsigned long dcr = mfspr(SPR_DCR(i));
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unsigned long dcr = mfspr(SPR_DCR(i));
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unsigned long dcr_ct = dcr & SPR_DCR_CT; /* the CT field alone */
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unsigned long dcr_ct = dcr & SPR_DCR_CT; /* the CT field alone */
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/* Is this matchpoint a propos for the current action? */
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/* Is this matchpoint a propos for the current action? */
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if ( ((dcr & SPR_DCR_DP) && dcr_ct) && /* DVR/DCP pair present */
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if ( ((dcr & SPR_DCR_DP) && dcr_ct) && /* DVR/DCP pair present */
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(((action==DebugInstructionFetch) && (dcr_ct == SPR_DCR_CT_IFEA)) ||
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(((action==DebugInstructionFetch) && (dcr_ct == SPR_DCR_CT_IFEA)) ||
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((action==DebugLoadAddress) && ((dcr_ct == SPR_DCR_CT_LEA) ||
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((action==DebugLoadAddress) && ((dcr_ct == SPR_DCR_CT_LEA) ||
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(dcr_ct == SPR_DCR_CT_LSEA))) ||
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(dcr_ct == SPR_DCR_CT_LSEA))) ||
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((action==DebugStoreAddress) && ((dcr_ct == SPR_DCR_CT_SEA) ||
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((action==DebugStoreAddress) && ((dcr_ct == SPR_DCR_CT_SEA) ||
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(dcr_ct == SPR_DCR_CT_LSEA))) ||
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(dcr_ct == SPR_DCR_CT_LSEA))) ||
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((action==DebugLoadData) && ((dcr_ct == SPR_DCR_CT_LD) ||
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((action==DebugLoadData) && ((dcr_ct == SPR_DCR_CT_LD) ||
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(dcr_ct == SPR_DCR_CT_LSD))) ||
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(dcr_ct == SPR_DCR_CT_LSD))) ||
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((action==DebugStoreData) && ((dcr_ct == SPR_DCR_CT_SD) ||
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((action==DebugStoreData) && ((dcr_ct == SPR_DCR_CT_SD) ||
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(dcr_ct == SPR_DCR_CT_LSD)))) ) {
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(dcr_ct == SPR_DCR_CT_LSD)))) ) {
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unsigned long op1 = udata;
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unsigned long op1 = udata;
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unsigned long op2 = mfspr (SPR_DVR(i));
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unsigned long op2 = mfspr (SPR_DVR(i));
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/* Perform signed comparison? */
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/* Perform signed comparison? */
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if (dcr & SPR_DCR_SC) {
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if (dcr & SPR_DCR_SC) {
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long sop1 = op1, sop2 = op2; /* Convert to signed */
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long sop1 = op1, sop2 = op2; /* Convert to signed */
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switch(dcr & SPR_DCR_CC) {
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switch(dcr & SPR_DCR_CC) {
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case SPR_DCR_CC_MASKED: DCR_hit = sop1 & sop2; break;
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case SPR_DCR_CC_MASKED: DCR_hit = sop1 & sop2; break;
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case SPR_DCR_CC_EQUAL: DCR_hit = sop1 == sop2; break;
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case SPR_DCR_CC_EQUAL: DCR_hit = sop1 == sop2; break;
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case SPR_DCR_CC_NEQUAL: DCR_hit = sop1 != sop2; break;
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case SPR_DCR_CC_NEQUAL: DCR_hit = sop1 != sop2; break;
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case SPR_DCR_CC_LESS: DCR_hit = sop1 < sop2; break;
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case SPR_DCR_CC_LESS: DCR_hit = sop1 < sop2; break;
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case SPR_DCR_CC_LESSE: DCR_hit = sop1 <= sop2; break;
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case SPR_DCR_CC_LESSE: DCR_hit = sop1 <= sop2; break;
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case SPR_DCR_CC_GREAT: DCR_hit = sop1 > sop2; break;
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case SPR_DCR_CC_GREAT: DCR_hit = sop1 > sop2; break;
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case SPR_DCR_CC_GREATE: DCR_hit = sop1 >= sop2; break;
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case SPR_DCR_CC_GREATE: DCR_hit = sop1 >= sop2; break;
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}
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}
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} else {
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} else {
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switch(dcr & SPR_DCR_CC) {
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switch(dcr & SPR_DCR_CC) {
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case SPR_DCR_CC_MASKED: DCR_hit = op1 & op2; break;
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case SPR_DCR_CC_MASKED: DCR_hit = op1 & op2; break;
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case SPR_DCR_CC_EQUAL: DCR_hit = op1 == op2; break;
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case SPR_DCR_CC_EQUAL: DCR_hit = op1 == op2; break;
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case SPR_DCR_CC_NEQUAL: DCR_hit = op1 != op2; break;
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case SPR_DCR_CC_NEQUAL: DCR_hit = op1 != op2; break;
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case SPR_DCR_CC_LESS: DCR_hit = op1 < op2; break;
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case SPR_DCR_CC_LESS: DCR_hit = op1 < op2; break;
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case SPR_DCR_CC_LESSE: DCR_hit = op1 <= op2; break;
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case SPR_DCR_CC_LESSE: DCR_hit = op1 <= op2; break;
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case SPR_DCR_CC_GREAT: DCR_hit = op1 > op2; break;
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case SPR_DCR_CC_GREAT: DCR_hit = op1 > op2; break;
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case SPR_DCR_CC_GREATE: DCR_hit = op1 >= op2; break;
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case SPR_DCR_CC_GREATE: DCR_hit = op1 >= op2; break;
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}
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}
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}
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}
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}
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}
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}
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}
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/* Chain matchpoints */
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/* Chain matchpoints */
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switch(i) {
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switch(i) {
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case 0:
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case 0:
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chain1 = chain2 = DCR_hit;
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chain1 = chain2 = DCR_hit;
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break;
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break;
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case 8:
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case 8:
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chain1 = getsprbits(SPR_DWCR0, SPR_DWCR_COUNT) == getsprbits(SPR_DWCR0,
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chain1 = getsprbits(SPR_DWCR0, SPR_DWCR_COUNT) == getsprbits(SPR_DWCR0,
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SPR_DWCR_MATCH);
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SPR_DWCR_MATCH);
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chain2 = watchpoints & (1 << 7);
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chain2 = watchpoints & (1 << 7);
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break;
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break;
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case 9:
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case 9:
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chain1 = getsprbits(SPR_DWCR1, SPR_DWCR_COUNT) == getsprbits (SPR_DWCR1,
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chain1 = getsprbits(SPR_DWCR1, SPR_DWCR_COUNT) == getsprbits (SPR_DWCR1,
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SPR_DWCR_MATCH);
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SPR_DWCR_MATCH);
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chain2 = watchpoints & (1 << 8);
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chain2 = watchpoints & (1 << 8);
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break;
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break;
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case 10:
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case 10:
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/* TODO: External watchpoint - not yet handled! */
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/* TODO: External watchpoint - not yet handled! */
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#if 0
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#if 0
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chain1 = external_watchpoint;
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chain1 = external_watchpoint;
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chain2 = watchpoints & (1 << 9);
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chain2 = watchpoints & (1 << 9);
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#else
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#else
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chain1 = chain2 = 0;
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chain1 = chain2 = 0;
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#endif
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#endif
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break;
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break;
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default:
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default:
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chain1 = DCR_hit;
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chain1 = DCR_hit;
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chain2 = watchpoints & (bit >> 1);
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chain2 = watchpoints & (bit >> 1);
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break;
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break;
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}
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}
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switch(getsprbits(SPR_DMR1, SPR_DMR1_CW0 << i)) {
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switch(getsprbits(SPR_DMR1, SPR_DMR1_CW0 << i)) {
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case 0: match = chain1; break;
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case 0: match = chain1; break;
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case 1: match = chain1 && chain2; break;
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case 1: match = chain1 && chain2; break;
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case 2: match = chain1 || chain2; break;
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case 2: match = chain1 || chain2; break;
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}
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}
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/* Increment counters & generate counter break */
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/* Increment counters & generate counter break */
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if(match) {
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if(match) {
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/* watchpoint did not appear before in this clock cycle */
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/* watchpoint did not appear before in this clock cycle */
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if(!(watchpoints & bit)) {
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if(!(watchpoints & bit)) {
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int counter = (getsprbits(SPR_DMR2, SPR_DMR2_AWTC) & bit) ? 1 : 0;
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int counter = (getsprbits(SPR_DMR2, SPR_DMR2_AWTC) & bit) ? 1 : 0;
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int enabled = counter ? getsprbits(SPR_DMR2, SPR_DMR2_WCE1) :
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int enabled = counter ? getsprbits(SPR_DMR2, SPR_DMR2_WCE1) :
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getsprbits(SPR_DMR2, SPR_DMR2_WCE0);
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getsprbits(SPR_DMR2, SPR_DMR2_WCE0);
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if(enabled)
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if(enabled)
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setsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT,
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setsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT,
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getsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT) + 1);
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getsprbits(SPR_DWCR0 + counter, SPR_DWCR_COUNT) + 1);
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watchpoints |= bit;
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watchpoints |= bit;
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}
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}
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/* should this watchpoint generate a breakpoint? */
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/* should this watchpoint generate a breakpoint? */
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if(getsprbits(SPR_DMR2, SPR_DMR2_WGB) & bit)
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if(getsprbits(SPR_DMR2, SPR_DMR2_WGB) & bit)
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breakpoint = 1;
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breakpoint = 1;
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}
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}
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}
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}
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return breakpoint;
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return breakpoint;
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}
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}
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static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
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static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
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int DebugGetRegister(unsigned int address, unsigned long* data)
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int DebugGetRegister(unsigned int address, unsigned long* data)
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{
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{
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int err=0;
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int err=0;
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#ifdef DEBUG_JTAG
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#ifdef DEBUG_JTAG
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PRINTF("Debug get register %x\n",address);
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PRINTF("Debug get register %x\n",address);
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fflush(stdout);
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fflush(stdout);
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#endif
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#endif
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switch(current_scan_chain)
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switch(current_scan_chain)
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{
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{
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case JTAG_CHAIN_DEBUG_UNIT:
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case JTAG_CHAIN_DEBUG_UNIT:
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*data = mfspr (address);
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*data = mfspr (address);
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debug (2, "READ (%08x) = %08x\n", address, *data);
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debug (2, "READ (%08x) = %08x\n", address, *data);
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if (runtime.sim.fspr_log) {
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if (runtime.sim.fspr_log) {
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fprintf(runtime.sim.fspr_log, "Read from SPR : [%08X] -> [%08lX]\n",
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fprintf(runtime.sim.fspr_log, "Read from SPR : [%08X] -> [%08lX]\n",
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address, *data);
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address, *data);
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}
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}
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break;
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break;
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case JTAG_CHAIN_TRACE:
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case JTAG_CHAIN_TRACE:
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*data = 0; /* Scan chain not yet implemented */
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*data = 0; /* Scan chain not yet implemented */
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break;
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break;
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case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
err = get_devint_reg(address,data);
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err = get_devint_reg(address,data);
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break;
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break;
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case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
err = debug_get_mem(address,data);
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err = debug_get_mem(address,data);
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break;
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break;
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}
|
}
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#ifdef DEBUG_JTAG
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#ifdef DEBUG_JTAG
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PRINTF("!get reg %x\n", *data);
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PRINTF("!get reg %x\n", *data);
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fflush(stdout);
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fflush(stdout);
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#endif
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#endif
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return err;
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return err;
|
}
|
}
|
|
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int DebugSetRegister(unsigned int address,unsigned long data)
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int DebugSetRegister(unsigned int address,unsigned long data)
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{
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{
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int err=0;
|
int err=0;
|
#ifdef DEBUG_JTAG
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#ifdef DEBUG_JTAG
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PRINTF("Debug set register %x <- %x\n", address, data);
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PRINTF("Debug set register %x <- %x\n", address, data);
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fflush(stdout);
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fflush(stdout);
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#endif
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#endif
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switch(current_scan_chain)
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switch(current_scan_chain)
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{
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{
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case JTAG_CHAIN_DEBUG_UNIT:
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case JTAG_CHAIN_DEBUG_UNIT:
|
debug (2, "WRITE (%08x) = %08lx\n", address, data);
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debug (2, "WRITE (%08x) = %08lx\n", address, data);
|
if (runtime.sim.fspr_log) {
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if (runtime.sim.fspr_log) {
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fprintf(runtime.sim.fspr_log, "Write to SPR : [%08X] <- [%08lX]\n",
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fprintf(runtime.sim.fspr_log, "Write to SPR : [%08X] <- [%08lX]\n",
|
address, data);
|
address, data);
|
}
|
}
|
mtspr(address, data);
|
mtspr(address, data);
|
break;
|
break;
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_TRACE:
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
break;
|
break;
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
err = set_devint_reg (address, data);
|
err = set_devint_reg (address, data);
|
break;
|
break;
|
case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
err = debug_set_mem (address, data);
|
err = debug_set_mem (address, data);
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
PRINTF("!set reg\n");
|
PRINTF("!set reg\n");
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
return err;
|
return err;
|
}
|
}
|
|
|
int DebugSetChain(int chain)
|
int DebugSetChain(int chain)
|
{
|
{
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
PRINTF("Debug set chain %x\n",chain);
|
PRINTF("Debug set chain %x\n",chain);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
switch(chain)
|
switch(chain)
|
{
|
{
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
current_scan_chain = chain;
|
current_scan_chain = chain;
|
break;
|
break;
|
default: /* All other chains not implemented */
|
default: /* All other chains not implemented */
|
return JTAG_PROXY_INVALID_CHAIN;
|
return JTAG_PROXY_INVALID_CHAIN;
|
}
|
}
|
|
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
PRINTF("!set chain\n");
|
PRINTF("!set chain\n");
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
return 0;
|
return 0;
|
}
|
}
|
|
|
void sim_reset ();
|
void sim_reset ();
|
|
|
/* Sets development interface register */
|
/* Sets development interface register */
|
int set_devint_reg(unsigned int address, unsigned long data)
|
int set_devint_reg(unsigned int address, unsigned long data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
unsigned long value = data;
|
unsigned long value = data;
|
int old_value;
|
int old_value;
|
|
|
switch(address) {
|
switch(address) {
|
case DEVELOPINT_MODER: development.moder = value; break;
|
case DEVELOPINT_MODER: development.moder = value; break;
|
case DEVELOPINT_TSEL: development.tsel = value; break;
|
case DEVELOPINT_TSEL: development.tsel = value; break;
|
case DEVELOPINT_QSEL: development.qsel = value; break;
|
case DEVELOPINT_QSEL: development.qsel = value; break;
|
case DEVELOPINT_SSEL: development.ssel = value; break;
|
case DEVELOPINT_SSEL: development.ssel = value; break;
|
case DEVELOPINT_RISCOP:
|
case DEVELOPINT_RISCOP:
|
old_value = (development.riscop & RISCOP_RESET) != 0;
|
old_value = (development.riscop & RISCOP_RESET) != 0;
|
development.riscop = value;
|
development.riscop = value;
|
in_reset = (development.riscop & RISCOP_RESET) != 0;
|
in_reset = (development.riscop & RISCOP_RESET) != 0;
|
/* Reset the cpu on the negative edge of RESET */
|
/* Reset the cpu on the negative edge of RESET */
|
if(old_value && !in_reset)
|
if(old_value && !in_reset)
|
sim_reset(); /* Reset all units */
|
sim_reset(); /* Reset all units */
|
set_stall_state((development.riscop & RISCOP_STALL) != 0);
|
set_stall_state((development.riscop & RISCOP_STALL) != 0);
|
break;
|
break;
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP10: development.recwp[address - DEVELOPINT_RECWP0] = value; break;
|
case DEVELOPINT_RECWP10: development.recwp[address - DEVELOPINT_RECWP0] = value; break;
|
case DEVELOPINT_RECBP0: development.recbp = value; break;
|
case DEVELOPINT_RECBP0: development.recbp = value; break;
|
default:
|
default:
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
PRINTF("set_devint_reg %08x = %08x\n", address, data);
|
PRINTF("set_devint_reg %08x = %08x\n", address, data);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Gets development interface register */
|
/* Gets development interface register */
|
int get_devint_reg(unsigned int address,unsigned long *data)
|
int get_devint_reg(unsigned int address,unsigned long *data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
unsigned long value = 0;
|
unsigned long value = 0;
|
|
|
switch(address) {
|
switch(address) {
|
case DEVELOPINT_MODER: value = development.moder; break;
|
case DEVELOPINT_MODER: value = development.moder; break;
|
case DEVELOPINT_TSEL: value = development.tsel; break;
|
case DEVELOPINT_TSEL: value = development.tsel; break;
|
case DEVELOPINT_QSEL: value = development.qsel; break;
|
case DEVELOPINT_QSEL: value = development.qsel; break;
|
case DEVELOPINT_SSEL: value = development.ssel; break;
|
case DEVELOPINT_SSEL: value = development.ssel; break;
|
case DEVELOPINT_RISCOP: value = development.riscop; break;
|
case DEVELOPINT_RISCOP: value = development.riscop; break;
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP10: value = development.recwp[address - DEVELOPINT_RECWP0]; break;
|
case DEVELOPINT_RECWP10: value = development.recwp[address - DEVELOPINT_RECWP0]; break;
|
case DEVELOPINT_RECBP0: value = development.recbp; break;
|
case DEVELOPINT_RECBP0: value = development.recbp; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
}
|
}
|
|
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
PRINTF("get_devint_reg %08x = %08x\n", address, value);
|
PRINTF("get_devint_reg %08x = %08x\n", address, value);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
*data = value;
|
*data = value;
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Writes to bus address */
|
/* Writes to bus address */
|
int debug_set_mem (unsigned int address,unsigned long data)
|
int debug_set_mem (unsigned int address,unsigned long data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
debug (2, "MEMWRITE (%08x) = %08lx\n", address, data);
|
debug (2, "MEMWRITE (%08x) = %08lx\n", address, data);
|
|
|
|
|
if(!verify_memoryarea(address))
|
if(!verify_memoryarea(address))
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
else {
|
else {
|
// circumvent the read-only check usually done for mem accesses
|
// circumvent the read-only check usually done for mem accesses
|
// data is in host order, because that's what set_direct32 needs
|
// data is in host order, because that's what set_direct32 needs
|
set_direct32(address, data, NULL, 0, 0);
|
set_direct32(address, data, NULL, 0, 0);
|
}
|
}
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Reads from bus address */
|
/* Reads from bus address */
|
int debug_get_mem(unsigned int address,unsigned long *data)
|
int debug_get_mem(unsigned int address,unsigned long *data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
if(!verify_memoryarea(address))
|
if(!verify_memoryarea(address))
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
else
|
else
|
{
|
{
|
*data=eval_direct32(address, NULL, 0, 0);
|
*data=eval_direct32(address, NULL, 0, 0);
|
}
|
}
|
debug (2, "MEMREAD (%08x) = %08lx\n", address, *data);
|
debug (2, "MEMREAD (%08x) = %08lx\n", address, *data);
|
return err;
|
return err;
|
}
|
}
|
|
|
/* debug_ignore_exception returns 1 if the exception should be ignored. */
|
/* debug_ignore_exception returns 1 if the exception should be ignored. */
|
int debug_ignore_exception (unsigned long except)
|
int debug_ignore_exception (unsigned long except)
|
{
|
{
|
int result = 0;
|
int result = 0;
|
unsigned long dsr = mfspr (SPR_DSR);
|
unsigned long dsr = mfspr (SPR_DSR);
|
unsigned long drr = mfspr (SPR_DRR);
|
unsigned long drr = mfspr (SPR_DRR);
|
|
|
#if DEBUG_JTAG
|
#if DEBUG_JTAG
|
PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr);
|
PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr);
|
#endif
|
#endif
|
|
|
switch(except) {
|
switch(except) {
|
case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break;
|
case EXCEPT_RESET: drr |= result = dsr & SPR_DSR_RSTE; break;
|
case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break;
|
case EXCEPT_BUSERR: drr |= result = dsr & SPR_DSR_BUSEE; break;
|
case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break;
|
case EXCEPT_DPF: drr |= result = dsr & SPR_DSR_DPFE; break;
|
case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break;
|
case EXCEPT_IPF: drr |= result = dsr & SPR_DSR_IPFE; break;
|
case EXCEPT_TICK: drr |= result = dsr & SPR_DSR_TTE; break;
|
case EXCEPT_TICK: drr |= result = dsr & SPR_DSR_TTE; break;
|
case EXCEPT_ALIGN: drr |= result = dsr & SPR_DSR_AE; break;
|
case EXCEPT_ALIGN: drr |= result = dsr & SPR_DSR_AE; break;
|
case EXCEPT_ILLEGAL: drr |= result = dsr & SPR_DSR_IIE; break;
|
case EXCEPT_ILLEGAL: drr |= result = dsr & SPR_DSR_IIE; break;
|
case EXCEPT_INT: drr |= result = dsr & SPR_DSR_IE; break;
|
case EXCEPT_INT: drr |= result = dsr & SPR_DSR_IE; break;
|
case EXCEPT_DTLBMISS: drr |= result = dsr & SPR_DSR_DME; break;
|
case EXCEPT_DTLBMISS: drr |= result = dsr & SPR_DSR_DME; break;
|
case EXCEPT_ITLBMISS: drr |= result = dsr & SPR_DSR_IME; break;
|
case EXCEPT_ITLBMISS: drr |= result = dsr & SPR_DSR_IME; break;
|
case EXCEPT_RANGE: drr |= result = dsr & SPR_DSR_RE; break;
|
case EXCEPT_RANGE: drr |= result = dsr & SPR_DSR_RE; break;
|
case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break;
|
case EXCEPT_SYSCALL: drr |= result = dsr & SPR_DSR_SCE; break;
|
case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break;
|
case EXCEPT_TRAP: drr |= result = dsr & SPR_DSR_TE; break;
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
#if DEBUG_JTAG
|
#if DEBUG_JTAG
|
PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result);
|
PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result);
|
#endif
|
#endif
|
|
|
mtspr (SPR_DRR, drr);
|
mtspr (SPR_DRR, drr);
|
set_stall_state (result != 0);
|
set_stall_state (result != 0);
|
return (result != 0);
|
return (result != 0);
|
}
|
}
|
|
|
/*--------------------------------------------------[ Debug configuration ]---*/
|
/*--------------------------------------------------[ Debug configuration ]---*/
|
void debug_enabled(union param_val val, void *dat)
|
void debug_enabled(union param_val val, void *dat)
|
{
|
{
|
config.debug.enabled = val.int_val;
|
config.debug.enabled = val.int_val;
|
}
|
}
|
|
|
void debug_gdb_enabled(union param_val val, void *dat)
|
void debug_gdb_enabled(union param_val val, void *dat)
|
{
|
{
|
config.debug.gdb_enabled = val.int_val;
|
config.debug.gdb_enabled = val.int_val;
|
}
|
}
|
|
|
void debug_server_port(union param_val val, void *dat)
|
void debug_server_port(union param_val val, void *dat)
|
{
|
{
|
config.debug.server_port = val.int_val;
|
config.debug.server_port = val.int_val;
|
}
|
}
|
|
|
void debug_vapi_id(union param_val val, void *dat)
|
void debug_vapi_id(union param_val val, void *dat)
|
{
|
{
|
config.debug.vapi_id = val.int_val;
|
config.debug.vapi_id = val.int_val;
|
}
|
}
|
|
|
void reg_debug_sec(void)
|
void reg_debug_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("debug", NULL, NULL);
|
struct config_section *sec = reg_config_sec("debug", NULL, NULL);
|
|
|
reg_config_param(sec, "enabled", paramt_int, debug_enabled);
|
reg_config_param(sec, "enabled", paramt_int, debug_enabled);
|
reg_config_param(sec, "gdb_enabled", paramt_int, debug_gdb_enabled);
|
reg_config_param(sec, "gdb_enabled", paramt_int, debug_gdb_enabled);
|
reg_config_param(sec, "server_port", paramt_int, debug_server_port);
|
reg_config_param(sec, "server_port", paramt_int, debug_server_port);
|
reg_config_param(sec, "vapi_id", paramt_int, debug_server_port);
|
reg_config_param(sec, "vapi_id", paramt_int, debug_server_port);
|
}
|
}
|
|
|
