/* debug_unit.c -- Simulation of Or1k debug unit
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/* debug_unit.c -- Simulation of Or1k debug unit
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/*
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/*
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This is an architectural level simulation of the Or1k debug
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This is an architectural level simulation of the Or1k debug
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unit as described in OpenRISC 1000 System Architecture Manual,
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unit as described in OpenRISC 1000 System Architecture Manual,
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v. 0.1 on 22 April, 2001. This unit is described in Section 13.
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v. 0.1 on 22 April, 2001. This unit is described in Section 13.
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Every attempt has been made to be as accurate as possible with
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Every attempt has been made to be as accurate as possible with
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respect to the registers and the behavior. There are no known
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respect to the registers and the behavior. There are no known
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limitations at this time.
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limitations at this time.
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include <inttypes.h>
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#include <inttypes.h>
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#include "debug_unit.h"
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#include "debug_unit.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "except.h"
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#include "except.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "parse.h"
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#include "parse.h"
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#include "trace.h"
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#include "trace.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "../gdb.h"
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#include "../gdb.h"
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#include "../cpu/or1k/except.h"
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#include "../cpu/or1k/except.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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DebugUnit debug_unit;
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DebugUnit debug_unit;
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DevelopmentInterface development;
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DevelopmentInterface development;
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typedef enum {
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typedef enum {
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false = 0,
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false = 0,
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true = 1,
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true = 1,
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} Boolean;
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} Boolean;
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static void ExecuteInducedInstruction(unsigned long);
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static void ExecuteInducedInstruction(unsigned long);
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/* External STALL signal to debug interface */
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/* External STALL signal to debug interface */
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int cpu_stalled = false;
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int cpu_stalled = false;
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int in_reset = false;
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int in_reset = false;
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/* An induced instruction has been written to the DIR register */
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/* An induced instruction has been written to the DIR register */
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static Boolean induced = false;
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static Boolean induced = false;
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static unsigned long induced_insn;
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static unsigned long induced_insn;
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/* A flag to indicate that we must perform an ic mmu cycle */
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/* A flag to indicate that we must perform an ic mmu cycle */
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static Boolean lookup_physical_address = false;
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static Boolean lookup_physical_address = false;
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/* Variables for implementing ExecuteInducedInstruction */
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/* Variables for implementing ExecuteInducedInstruction */
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extern unsigned long pc;
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extern unsigned long pc;
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extern unsigned long pcnext;
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extern unsigned long pcnext;
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extern unsigned long pcdelay;
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extern unsigned long pcdelay;
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extern unsigned long pc_phy;
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extern unsigned long pc_phy;
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extern int delay_insn;
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extern int delay_insn;
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static void GetIQueueEntry(struct iqueue_entry*);
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static void GetIQueueEntry(struct iqueue_entry*);
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static int CalculateWatchpoints(void);
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static int CalculateWatchpoints(void);
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static int watchpoint[10];
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static int watchpoint[10];
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/* This function returns true if an induced instruction has
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/* This function returns true if an induced instruction has
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been inserted into the instruction stream. It will remove
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been inserted into the instruction stream. It will remove
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that instruction and return the result. This function is
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that instruction and return the result. This function is
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called from the fetch() routine. */
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called from the fetch() routine. */
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int OverrideFetch(unsigned long* insn)
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int OverrideFetch(unsigned long* insn)
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{
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{
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int valid = induced;
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int valid = induced;
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induced = false;
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induced = false;
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if(valid)
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if(valid)
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*insn = induced_insn;
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*insn = induced_insn;
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return valid;
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return valid;
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}
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}
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void InduceImmediateInstruction(unsigned long insn)
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void InduceImmediateInstruction(unsigned long insn)
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{
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{
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induced = true;
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induced = true;
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induced_insn = insn;
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induced_insn = insn;
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if(in_reset)
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if(in_reset)
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return;
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return;
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if(cpu_stalled)
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if(cpu_stalled)
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{
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{
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ExecuteInducedInstruction(insn);
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ExecuteInducedInstruction(insn);
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induced_insn = 0;
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induced_insn = 0;
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induced = false;
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induced = false;
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}
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}
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}
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}
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void SetCPUStallState(int state)
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void SetCPUStallState(int state)
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{
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{
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if(debug_unit.DMR1.DXFW) /* If debugger disabled */
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if(debug_unit.DMR1.DXFW) /* If debugger disabled */
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state = false;
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state = false;
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if(state == cpu_stalled)
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if(state == cpu_stalled)
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return;
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return;
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if(state && induced)
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if(state && induced)
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{
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{
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ExecuteInducedInstruction(induced_insn);
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ExecuteInducedInstruction(induced_insn);
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induced_insn = 0;
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induced_insn = 0;
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induced = false;
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induced = false;
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}
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}
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cpu_stalled = state;
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cpu_stalled = state;
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}
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}
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void ResetDebugUnit()
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void ResetDebugUnit()
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{
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{
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memset(&debug_unit,'\0',sizeof(DebugUnit));
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memset(&debug_unit,'\0',sizeof(DebugUnit));
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cpu_stalled = 0;
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cpu_stalled = 0;
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}
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}
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#ifdef DEBUGMOD_OFF
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#ifdef DEBUGMOD_OFF
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#define CheckDebugUnit(x,y) 0
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#define CheckDebugUnit(x,y) 0
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#else
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#else
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inline int CheckDebugUnit(DebugUnitAction action,unsigned long udata)
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inline int CheckDebugUnit(DebugUnitAction action,unsigned long udata)
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{
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{
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int i;
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int i;
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DCR_CT_Settings condition = DCR_CT_Disabled;
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DCR_CT_Settings condition = DCR_CT_Disabled;
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long data = (long)udata;
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long data = (long)udata;
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int match;
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int match;
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if(DEBUG_ENABLED || in_reset)
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if(DEBUG_ENABLED || in_reset)
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return 0;
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return 0;
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/* If we're single stepping, always stop */
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/* If we're single stepping, always stop */
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if(debug_unit.DMR1.ST && action == DebugInstructionFetch)
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if(debug_unit.DMR1.ST && action == DebugInstructionFetch)
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return 1;
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return 1;
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switch(action)
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switch(action)
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{
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{
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case DebugInstructionFetch: condition = DCR_CT_InsnAddress; break;
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case DebugInstructionFetch: condition = DCR_CT_InsnAddress; break;
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case DebugLoadAddress: condition = DCR_CT_LoadAddress; break;
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case DebugLoadAddress: condition = DCR_CT_LoadAddress; break;
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case DebugStoreAddress: condition = DCR_CT_StoreAddress; break;
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case DebugStoreAddress: condition = DCR_CT_StoreAddress; break;
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case DebugLoadData: condition = DCR_CT_LoadData; break;
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case DebugLoadData: condition = DCR_CT_LoadData; break;
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case DebugStoreData: condition = DCR_CT_StoreData; break;
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case DebugStoreData: condition = DCR_CT_StoreData; break;
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}
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}
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for(i=0;i<8;i++)
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for(i=0;i<8;i++)
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{
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{
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if(debug_unit.DCR[i].DP == DCR_DP_Absent)
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if(debug_unit.DCR[i].DP == DCR_DP_Absent)
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continue;
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continue;
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if(debug_unit.DCR[i].CT == condition)
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if(debug_unit.DCR[i].CT == condition)
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{
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{
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if(debug_unit.DCR[i].SC == DCR_SC_Signed)
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if(debug_unit.DCR[i].SC == DCR_SC_Signed)
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{
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{
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switch(debug_unit.DCR[i].CC)
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switch(debug_unit.DCR[i].CC)
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{
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{
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case DCR_CC_Equal: match = data == (int)debug_unit.DVR[i]; break;
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case DCR_CC_Equal: match = data == (int)debug_unit.DVR[i]; break;
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case DCR_CC_LessThan: match = data < (int)debug_unit.DVR[i]; break;
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case DCR_CC_LessThan: match = data < (int)debug_unit.DVR[i]; break;
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case DCR_CC_LessEqual: match = data <= (int)debug_unit.DVR[i]; break;
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case DCR_CC_LessEqual: match = data <= (int)debug_unit.DVR[i]; break;
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case DCR_CC_GreaterThan: match = data > (int)debug_unit.DVR[i]; break;
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case DCR_CC_GreaterThan: match = data > (int)debug_unit.DVR[i]; break;
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case DCR_CC_GreaterEqual: match = data >= (int)debug_unit.DVR[i]; break;
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case DCR_CC_GreaterEqual: match = data >= (int)debug_unit.DVR[i]; break;
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case DCR_CC_NotEqual: match = data != (int)debug_unit.DVR[i]; break;
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case DCR_CC_NotEqual: match = data != (int)debug_unit.DVR[i]; break;
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default: match = 0; break;
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default: match = 0; break;
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}
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}
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}
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}
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else
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else
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{
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{
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switch(debug_unit.DCR[i].CC)
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switch(debug_unit.DCR[i].CC)
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{
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{
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case DCR_CC_Equal: match = udata == debug_unit.DVR[i]; break;
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case DCR_CC_Equal: match = udata == debug_unit.DVR[i]; break;
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case DCR_CC_LessThan: match = udata < debug_unit.DVR[i]; break;
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case DCR_CC_LessThan: match = udata < debug_unit.DVR[i]; break;
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case DCR_CC_LessEqual: match = udata <= debug_unit.DVR[i]; break;
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case DCR_CC_LessEqual: match = udata <= debug_unit.DVR[i]; break;
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case DCR_CC_GreaterThan: match = udata > debug_unit.DVR[i]; break;
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case DCR_CC_GreaterThan: match = udata > debug_unit.DVR[i]; break;
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case DCR_CC_GreaterEqual: match = udata >= debug_unit.DVR[i]; break;
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case DCR_CC_GreaterEqual: match = udata >= debug_unit.DVR[i]; break;
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case DCR_CC_NotEqual: match = udata != debug_unit.DVR[i]; break;
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case DCR_CC_NotEqual: match = udata != debug_unit.DVR[i]; break;
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default: match = 0; break;
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default: match = 0; break;
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}
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}
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}
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}
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}
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}
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match <<= i;
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match <<= i;
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debug_unit.DCR_hit &= ~match; /* Clear DCR compare if it has changed */
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debug_unit.DCR_hit &= ~match; /* Clear DCR compare if it has changed */
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debug_unit.DCR_hit |= match; /* Save the state of each DCR compare */
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debug_unit.DCR_hit |= match; /* Save the state of each DCR compare */
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}
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}
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return CalculateWatchpoints();
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return CalculateWatchpoints();
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}
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}
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#endif
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#endif
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static int CalculateWatchpoints()
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static int CalculateWatchpoints()
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{
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{
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int spec[11];
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int spec[11];
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int breakpoint = 0;
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int breakpoint = 0;
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int i,bit;
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int i,bit;
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spec[0] = debug_unit.DMR1.CW0;
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spec[0] = debug_unit.DMR1.CW0;
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spec[1] = debug_unit.DMR1.CW1;
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spec[1] = debug_unit.DMR1.CW1;
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spec[2] = debug_unit.DMR1.CW2;
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spec[2] = debug_unit.DMR1.CW2;
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spec[3] = debug_unit.DMR1.CW3;
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spec[3] = debug_unit.DMR1.CW3;
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spec[4] = debug_unit.DMR1.CW4;
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spec[4] = debug_unit.DMR1.CW4;
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spec[5] = debug_unit.DMR1.CW5;
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spec[5] = debug_unit.DMR1.CW5;
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spec[6] = debug_unit.DMR1.CW6;
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spec[6] = debug_unit.DMR1.CW6;
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spec[7] = debug_unit.DMR1.CW7;
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spec[7] = debug_unit.DMR1.CW7;
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spec[8] = debug_unit.DMR1.CW8;
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spec[8] = debug_unit.DMR1.CW8;
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spec[9] = debug_unit.DMR1.CW9;
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spec[9] = debug_unit.DMR1.CW9;
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spec[10] = debug_unit.DMR1.CW10;
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spec[10] = debug_unit.DMR1.CW10;
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for(i=0,bit=1;i<11;i++,bit<<=1)
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for(i=0,bit=1;i<11;i++,bit<<=1)
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{
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{
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int chain1,chain2;
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int chain1,chain2;
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int match = 0;
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int match = 0;
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switch(i)
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switch(i)
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{
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{
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case 0:
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case 0:
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chain1 = chain2 = debug_unit.DCR_hit & 0x01;
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chain1 = chain2 = debug_unit.DCR_hit & 0x01;
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break;
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break;
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case 8:
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case 8:
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chain1 = debug_unit.DWCR[0].COUNT == debug_unit.DWCR[0].MATCH;
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chain1 = debug_unit.DWCR[0].COUNT == debug_unit.DWCR[0].MATCH;
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chain2 = debug_unit.watchpoint & (1 << 7);
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chain2 = debug_unit.watchpoint & (1 << 7);
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break;
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break;
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case 9:
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case 9:
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chain1 = debug_unit.DWCR[1].COUNT == debug_unit.DWCR[1].MATCH;
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chain1 = debug_unit.DWCR[1].COUNT == debug_unit.DWCR[1].MATCH;
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chain2 = debug_unit.watchpoint & (1 << 8);
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chain2 = debug_unit.watchpoint & (1 << 8);
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break;
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break;
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case 10:
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case 10:
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chain1 = debug_unit.DCR_hit & 0x100; /* External hit */
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chain1 = debug_unit.DCR_hit & 0x100; /* External hit */
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chain2 = debug_unit.watchpoint & (1 << 9);
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chain2 = debug_unit.watchpoint & (1 << 9);
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break;
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break;
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default:
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default:
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chain1 = debug_unit.DCR_hit & bit;
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chain1 = debug_unit.DCR_hit & bit;
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chain2 = debug_unit.watchpoint & (bit >> 1);
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chain2 = debug_unit.watchpoint & (bit >> 1);
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break;
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break;
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}
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}
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switch(spec[i])
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switch(spec[i])
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{
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{
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case 0: match = chain1; break;
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case 0: match = chain1; break;
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case 1: match = chain1 && chain2; break;
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case 1: match = chain1 && chain2; break;
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case 2: match = chain1 || chain2; break;
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case 2: match = chain1 || chain2; break;
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default:
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default:
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break;
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break;
|
}
|
}
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|
|
if(match & !(debug_unit.watchpoint & bit))
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if(match & !(debug_unit.watchpoint & bit))
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{
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{
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int counter = (debug_unit.DMR2.AWPC & bit) ? 1 : 0;
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int counter = (debug_unit.DMR2.AWPC & bit) ? 1 : 0;
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int enabled = counter ? debug_unit.DMR2.WCE1 : debug_unit.DMR2.WCE0;
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int enabled = counter ? debug_unit.DMR2.WCE1 : debug_unit.DMR2.WCE0;
|
|
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if(enabled)
|
if(enabled)
|
debug_unit.DWCR[counter].COUNT++;
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debug_unit.DWCR[counter].COUNT++;
|
|
|
if(debug_unit.DMR2.WGB & bit)
|
if(debug_unit.DMR2.WGB & bit)
|
breakpoint = 1;
|
breakpoint = 1;
|
}
|
}
|
|
|
debug_unit.watchpoint &= ~bit;
|
debug_unit.watchpoint &= ~bit;
|
debug_unit.watchpoint |= bit;
|
debug_unit.watchpoint |= bit;
|
}
|
}
|
|
|
return breakpoint;
|
return breakpoint;
|
}
|
}
|
|
|
static void GetIQueueEntry(struct iqueue_entry* iq_entry)
|
static void GetIQueueEntry(struct iqueue_entry* iq_entry)
|
{
|
{
|
iq_entry->insn = induced_insn;
|
iq_entry->insn = induced_insn;
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iq_entry->insn_index = insn_decode(induced_insn);
|
iq_entry->insn_index = insn_decode(induced_insn);
|
iq_entry->insn_addr = pc_phy;
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iq_entry->insn_addr = pc_phy;
|
iq_entry->op[0] = 0;
|
iq_entry->op[0] = 0;
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iq_entry->op[MAX_OPERANDS] = OPTYPE_LAST;
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iq_entry->op[MAX_OPERANDS] = OPTYPE_LAST;
|
}
|
}
|
|
|
static void ExecuteInducedInstruction(unsigned long insn)
|
static void ExecuteInducedInstruction(unsigned long insn)
|
{
|
{
|
struct iqueue_entry iq_entry;
|
struct iqueue_entry iq_entry;
|
unsigned long pc_saved = pc;
|
unsigned long pc_saved = pc;
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unsigned long pcnext_saved = pcnext;
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unsigned long pcnext_saved = pcnext;
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unsigned long pcdelay_saved = pcdelay;
|
unsigned long pcdelay_saved = pcdelay;
|
unsigned long pc_phy_saved = pc_phy;
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unsigned long pc_phy_saved = pc_phy;
|
|
|
GetIQueueEntry(&iq_entry);
|
GetIQueueEntry(&iq_entry);
|
decode_execute(&iq_entry);
|
decode_execute(&iq_entry);
|
|
|
pc = pc_saved;
|
pc = pc_saved;
|
pcnext = pcnext_saved;
|
pcnext = pcnext_saved;
|
pcdelay = pcdelay_saved;
|
pcdelay = pcdelay_saved;
|
pc_phy = pc_phy_saved;
|
pc_phy = pc_phy_saved;
|
}
|
}
|
|
|
static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
|
static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
|
|
|
int DebugGetRegister(unsigned int address,int32_t* data)
|
int DebugGetRegister(unsigned int address,int32_t* data)
|
{
|
{
|
int err;
|
int err;
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
printf("Debug get register %x\n",address);
|
printf("Debug get register %x\n",address);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
switch(current_scan_chain)
|
switch(current_scan_chain)
|
{
|
{
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_DEBUG_UNIT:
|
err = GetDebugUnitRegister(address,data);
|
err = GetDebugUnitRegister(address,data);
|
break;
|
break;
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_TRACE:
|
*data = 0; /* Scan chain not yet implemented */
|
*data = 0; /* Scan chain not yet implemented */
|
err = 0;
|
err = 0;
|
break;
|
break;
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
err = GetDevelopmentInterfaceRegister(address,data);
|
err = GetDevelopmentInterfaceRegister(address,data);
|
break;
|
break;
|
case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
err = GetWishboneMemory(address,data);
|
err = GetWishboneMemory(address,data);
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
printf("!get reg %x\n", *data);
|
printf("!get reg %x\n", *data);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
return err;
|
return err;
|
}
|
}
|
|
|
int DebugSetRegister(unsigned int address,int32_t data)
|
int DebugSetRegister(unsigned int address,int32_t data)
|
{
|
{
|
int err;
|
int err;
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
printf("Debug set register %x <- %x\n",address, data);
|
printf("Debug set register %x <- %x\n",address, data);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
switch(current_scan_chain)
|
switch(current_scan_chain)
|
{
|
{
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_DEBUG_UNIT:
|
err = SetDebugUnitRegister(address,data);
|
err = SetDebugUnitRegister(address,data);
|
break;
|
break;
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_TRACE:
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
break;
|
break;
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
err = SetDevelopmentInterfaceRegister(address,data);
|
err = SetDevelopmentInterfaceRegister(address,data);
|
break;
|
break;
|
case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
err = SetWishboneMemory(address,data);
|
err = SetWishboneMemory(address,data);
|
break;
|
break;
|
}
|
}
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
printf("!set reg\n");
|
printf("!set reg\n");
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
return err;
|
return err;
|
}
|
}
|
|
|
int DebugSetChain(int chain)
|
int DebugSetChain(int chain)
|
{
|
{
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
printf("Debug set chain %x\n",chain);
|
printf("Debug set chain %x\n",chain);
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
switch(chain)
|
switch(chain)
|
{
|
{
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_DEBUG_UNIT:
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_TRACE:
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_DEVELOPMENT:
|
case JTAG_CHAIN_WISHBONE:
|
case JTAG_CHAIN_WISHBONE:
|
current_scan_chain = chain;
|
current_scan_chain = chain;
|
break;
|
break;
|
default: /* All other chains not implemented */
|
default: /* All other chains not implemented */
|
return JTAG_PROXY_INVALID_CHAIN;
|
return JTAG_PROXY_INVALID_CHAIN;
|
}
|
}
|
|
|
#ifdef DEBUG_JTAG
|
#ifdef DEBUG_JTAG
|
printf("!set chain\n");
|
printf("!set chain\n");
|
fflush(stdout);
|
fflush(stdout);
|
#endif
|
#endif
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Nearly all compilers today store these bit fields as a packed structure
|
/* Nearly all compilers today store these bit fields as a packed structure
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
to be working in a non standard environment, you may need to rewrite
|
to be working in a non standard environment, you may need to rewrite
|
this routine or the SET_REG32 macro. */
|
this routine or the SET_REG32 macro. */
|
int SetDevelopmentInterfaceRegister(unsigned int address,uint32_t data)
|
int SetDevelopmentInterfaceRegister(unsigned int address,uint32_t data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
uint32_t value = data;
|
uint32_t value = data;
|
int old_value;
|
int old_value;
|
char *t_ptr = (char*)&development.RISCOP;
|
char *t_ptr = (char*)&development.RISCOP;
|
|
|
switch(address)
|
switch(address)
|
{
|
{
|
case DEVELOPINT_MODER:
|
case DEVELOPINT_MODER:
|
SET_REG32(development.MODER,value);
|
SET_REG32(development.MODER,value);
|
break;
|
break;
|
case DEVELOPINT_TSEL:
|
case DEVELOPINT_TSEL:
|
SET_REG32(development.TSEL,value);
|
SET_REG32(development.TSEL,value);
|
break;
|
break;
|
case DEVELOPINT_QSEL:
|
case DEVELOPINT_QSEL:
|
SET_REG32(development.QSEL,value);
|
SET_REG32(development.QSEL,value);
|
break;
|
break;
|
case DEVELOPINT_SSEL:
|
case DEVELOPINT_SSEL:
|
SET_REG32(development.SSEL,value);
|
SET_REG32(development.SSEL,value);
|
break;
|
break;
|
case DEVELOPINT_RISCOP:
|
case DEVELOPINT_RISCOP:
|
old_value = development.RISCOP.RESET;
|
old_value = development.RISCOP.RESET;
|
SET_REG32(development.RISCOP,value);
|
SET_REG32(development.RISCOP,value);
|
|
|
in_reset = development.RISCOP.RESET;
|
in_reset = development.RISCOP.RESET;
|
|
|
/* Reset the cpu on the negative edge of RESET */
|
/* Reset the cpu on the negative edge of RESET */
|
if(old_value && !development.RISCOP.RESET)
|
if(old_value && !development.RISCOP.RESET)
|
{
|
{
|
uart_reset();
|
uart_reset();
|
tick_reset();
|
tick_reset();
|
pm_reset();
|
pm_reset();
|
pic_reset();
|
pic_reset();
|
reset(); /* Old or new mode */
|
reset(); /* Old or new mode */
|
}
|
}
|
|
|
SetCPUStallState(development.RISCOP.RISCSTALL);
|
SetCPUStallState(development.RISCOP.RISCSTALL);
|
break;
|
break;
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP10:
|
case DEVELOPINT_RECWP10:
|
SET_REG32(development.RECWP[address-DEVELOPINT_RECWP0],value);
|
SET_REG32(development.RECWP[address-DEVELOPINT_RECWP0],value);
|
break;
|
break;
|
case DEVELOPINT_RECBP0:
|
case DEVELOPINT_RECBP0:
|
SET_REG32(development.RECBP[0],value);
|
SET_REG32(development.RECBP[0],value);
|
break;
|
break;
|
default:
|
default:
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
break;
|
break;
|
}
|
}
|
return err;
|
return err;
|
}
|
}
|
|
|
int GetDevelopmentInterfaceRegister(unsigned int address,uint32_t *data)
|
int GetDevelopmentInterfaceRegister(unsigned int address,uint32_t *data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
uint32_t value = 0;
|
uint32_t value = 0;
|
|
|
switch(address)
|
switch(address)
|
{
|
{
|
case DEVELOPINT_MODER: GET_REG32(development.MODER,value); break;
|
case DEVELOPINT_MODER: GET_REG32(development.MODER,value); break;
|
case DEVELOPINT_TSEL: GET_REG32(development.TSEL,value); break;
|
case DEVELOPINT_TSEL: GET_REG32(development.TSEL,value); break;
|
case DEVELOPINT_QSEL: GET_REG32(development.QSEL,value); break;
|
case DEVELOPINT_QSEL: GET_REG32(development.QSEL,value); break;
|
case DEVELOPINT_SSEL: GET_REG32(development.SSEL,value); break;
|
case DEVELOPINT_SSEL: GET_REG32(development.SSEL,value); break;
|
case DEVELOPINT_RISCOP: GET_REG32(development.RISCOP,value); break;
|
case DEVELOPINT_RISCOP: GET_REG32(development.RISCOP,value); break;
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP0:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP1:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP2:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP3:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP4:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP5:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP6:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP7:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP8:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP9:
|
case DEVELOPINT_RECWP10: GET_REG32(development.RECWP[address-DEVELOPINT_RECWP0],value); break;
|
case DEVELOPINT_RECWP10: GET_REG32(development.RECWP[address-DEVELOPINT_RECWP0],value); break;
|
case DEVELOPINT_RECBP0: GET_REG32(development.RECBP[0],value); break;
|
case DEVELOPINT_RECBP0: GET_REG32(development.RECBP[0],value); break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
}
|
}
|
|
|
*data = value;
|
*data = value;
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Nearly all compilers today store these bit fields as a packed structure
|
/* Nearly all compilers today store these bit fields as a packed structure
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
to be working in a non standard environment, you may need to rewrite
|
to be working in a non standard environment, you may need to rewrite
|
this routine or the SET_REG32 macro. */
|
this routine or the SET_REG32 macro. */
|
int SetDebugUnitRegister(unsigned int address,uint32_t data)
|
int SetDebugUnitRegister(unsigned int address,uint32_t data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
uint32_t value = data;
|
uint32_t value = data;
|
int old_value;
|
int old_value;
|
int group = address >> 11;
|
int group = address >> 11;
|
|
|
address &= 0x07FF;
|
address &= 0x07FF;
|
|
|
/*****************************************************/
|
/*****************************************************/
|
/* TEMPORARY!!!! */
|
/* TEMPORARY!!!! */
|
/*****************************************************/
|
/*****************************************************/
|
if(group == 6)
|
if(group == 6)
|
address -= 32;
|
address -= 32;
|
|
|
if(group == 6)
|
if(group == 6)
|
{
|
{
|
switch(address)
|
switch(address)
|
{
|
{
|
case DEBUGINT_DVR0:
|
case DEBUGINT_DVR0:
|
case DEBUGINT_DVR1:
|
case DEBUGINT_DVR1:
|
case DEBUGINT_DVR2:
|
case DEBUGINT_DVR2:
|
case DEBUGINT_DVR3:
|
case DEBUGINT_DVR3:
|
case DEBUGINT_DVR4:
|
case DEBUGINT_DVR4:
|
case DEBUGINT_DVR5:
|
case DEBUGINT_DVR5:
|
case DEBUGINT_DVR6:
|
case DEBUGINT_DVR6:
|
case DEBUGINT_DVR7:
|
case DEBUGINT_DVR7:
|
printf("DVR %d set to 0x%08x\n",address-DEBUGINT_DVR0,value);
|
printf("DVR %d set to 0x%08x\n",address-DEBUGINT_DVR0,value);
|
SET_REG32(debug_unit.DVR[address-DEBUGINT_DVR0],value);
|
SET_REG32(debug_unit.DVR[address-DEBUGINT_DVR0],value);
|
break;
|
break;
|
case DEBUGINT_DCR0:
|
case DEBUGINT_DCR0:
|
case DEBUGINT_DCR1:
|
case DEBUGINT_DCR1:
|
case DEBUGINT_DCR2:
|
case DEBUGINT_DCR2:
|
case DEBUGINT_DCR3:
|
case DEBUGINT_DCR3:
|
case DEBUGINT_DCR4:
|
case DEBUGINT_DCR4:
|
case DEBUGINT_DCR5:
|
case DEBUGINT_DCR5:
|
case DEBUGINT_DCR6:
|
case DEBUGINT_DCR6:
|
case DEBUGINT_DCR7:
|
case DEBUGINT_DCR7:
|
printf("DCR %d set to 0x%08x\n",address-DEBUGINT_DCR0,value);
|
printf("DCR %d set to 0x%08x\n",address-DEBUGINT_DCR0,value);
|
SET_REG32(debug_unit.DCR[address-DEBUGINT_DCR0],value);
|
SET_REG32(debug_unit.DCR[address-DEBUGINT_DCR0],value);
|
break;
|
break;
|
case DEBUGINT_DMR1:
|
case DEBUGINT_DMR1:
|
SET_REG32(debug_unit.DMR1,value);
|
SET_REG32(debug_unit.DMR1,value);
|
break;
|
break;
|
case DEBUGINT_DMR2:
|
case DEBUGINT_DMR2:
|
SET_REG32(debug_unit.DMR2,value);
|
SET_REG32(debug_unit.DMR2,value);
|
break;
|
break;
|
case DEBUGINT_DWCR0:
|
case DEBUGINT_DWCR0:
|
SET_REG32(debug_unit.DWCR[0],value);
|
SET_REG32(debug_unit.DWCR[0],value);
|
break;
|
break;
|
case DEBUGINT_DWCR1:
|
case DEBUGINT_DWCR1:
|
SET_REG32(debug_unit.DWCR[1],value);
|
SET_REG32(debug_unit.DWCR[1],value);
|
break;
|
break;
|
case DEBUGINT_DSR:
|
case DEBUGINT_DSR:
|
SET_REG32(debug_unit.DSR,value);
|
SET_REG32(debug_unit.DSR,value);
|
break;
|
break;
|
case DEBUGINT_DRR:
|
case DEBUGINT_DRR:
|
SET_REG32(debug_unit.DRR,value);
|
SET_REG32(debug_unit.DRR,value);
|
break;
|
break;
|
case DEBUGINT_DIR:
|
case DEBUGINT_DIR:
|
InduceImmediateInstruction(value);
|
InduceImmediateInstruction(value);
|
break;
|
break;
|
default:
|
default:
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
else if(group == 0)
|
else if(group == 0)
|
{
|
{
|
extern unsigned long reg[32];
|
extern unsigned long reg[32];
|
|
|
if(!address)
|
if(!address)
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
else if(address < 32)
|
else if(address < 32)
|
{
|
{
|
/* Assume that a write to the PC implies
|
/* Assume that a write to the PC implies
|
that the debugging software has recognized
|
that the debugging software has recognized
|
the exception and wants to do something
|
the exception and wants to do something
|
else instead. */
|
else instead. */
|
|
|
if(address == SPR_PC)
|
if(address == SPR_NPC)
|
{
|
{
|
ClearPendingException();
|
ClearPendingException();
|
ClearPreparedPCState();
|
ClearPreparedPCState();
|
}
|
}
|
mtspr(address,data);
|
mtspr(address,data);
|
}
|
}
|
else if(address >= 0x0400 && address < 0x0420)
|
else if(address >= 0x0400 && address < 0x0420)
|
reg[address - 0x0400] = data;
|
reg[address - 0x0400] = data;
|
else if(address < 0x0600 || address >= 0x0620)
|
else if(address < 0x0600 || address >= 0x0620)
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
}
|
}
|
else
|
else
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
|
|
return err;
|
return err;
|
}
|
}
|
|
|
int GetDebugUnitRegister(unsigned int address,uint32_t *data)
|
int GetDebugUnitRegister(unsigned int address,uint32_t *data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
uint32_t value = 0;
|
uint32_t value = 0;
|
int group = address >> 11;
|
int group = address >> 11;
|
|
|
address &= 0x07FF;
|
address &= 0x07FF;
|
|
|
/*****************************************************/
|
/*****************************************************/
|
/* TEMPORARY!!!! */
|
/* TEMPORARY!!!! */
|
/*****************************************************/
|
/*****************************************************/
|
if(group == 6)
|
if(group == 6)
|
address -= 32;
|
address -= 32;
|
|
|
if(group == 6)
|
if(group == 6)
|
{
|
{
|
switch(address)
|
switch(address)
|
{
|
{
|
case DEBUGINT_DVR0:
|
case DEBUGINT_DVR0:
|
case DEBUGINT_DVR1:
|
case DEBUGINT_DVR1:
|
case DEBUGINT_DVR2:
|
case DEBUGINT_DVR2:
|
case DEBUGINT_DVR3:
|
case DEBUGINT_DVR3:
|
case DEBUGINT_DVR4:
|
case DEBUGINT_DVR4:
|
case DEBUGINT_DVR5:
|
case DEBUGINT_DVR5:
|
case DEBUGINT_DVR6:
|
case DEBUGINT_DVR6:
|
case DEBUGINT_DVR7: GET_REG32(debug_unit.DVR[address-DEBUGINT_DVR0],value); break;
|
case DEBUGINT_DVR7: GET_REG32(debug_unit.DVR[address-DEBUGINT_DVR0],value); break;
|
case DEBUGINT_DCR0:
|
case DEBUGINT_DCR0:
|
case DEBUGINT_DCR1:
|
case DEBUGINT_DCR1:
|
case DEBUGINT_DCR2:
|
case DEBUGINT_DCR2:
|
case DEBUGINT_DCR3:
|
case DEBUGINT_DCR3:
|
case DEBUGINT_DCR4:
|
case DEBUGINT_DCR4:
|
case DEBUGINT_DCR5:
|
case DEBUGINT_DCR5:
|
case DEBUGINT_DCR6:
|
case DEBUGINT_DCR6:
|
case DEBUGINT_DCR7: GET_REG32(debug_unit.DCR[address-DEBUGINT_DCR0],value); break;
|
case DEBUGINT_DCR7: GET_REG32(debug_unit.DCR[address-DEBUGINT_DCR0],value); break;
|
case DEBUGINT_DMR1: GET_REG32(debug_unit.DMR1,value); break;
|
case DEBUGINT_DMR1: GET_REG32(debug_unit.DMR1,value); break;
|
case DEBUGINT_DMR2: GET_REG32(debug_unit.DMR2,value); break;
|
case DEBUGINT_DMR2: GET_REG32(debug_unit.DMR2,value); break;
|
case DEBUGINT_DWCR0: GET_REG32(debug_unit.DWCR[0],value); break;
|
case DEBUGINT_DWCR0: GET_REG32(debug_unit.DWCR[0],value); break;
|
case DEBUGINT_DWCR1: GET_REG32(debug_unit.DWCR[1],value); break;
|
case DEBUGINT_DWCR1: GET_REG32(debug_unit.DWCR[1],value); break;
|
case DEBUGINT_DSR: GET_REG32(debug_unit.DSR,value); break;
|
case DEBUGINT_DSR: GET_REG32(debug_unit.DSR,value); break;
|
case DEBUGINT_DRR: GET_REG32(debug_unit.DRR,value); break;
|
case DEBUGINT_DRR: GET_REG32(debug_unit.DRR,value); break;
|
case DEBUGINT_DIR: err = JTAG_PROXY_ACCESS_EXCEPTION; break;
|
case DEBUGINT_DIR: err = JTAG_PROXY_ACCESS_EXCEPTION; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
}
|
}
|
}
|
}
|
else if(group == 0)
|
else if(group == 0)
|
{
|
{
|
extern unsigned long reg[32];
|
extern unsigned long reg[32];
|
|
|
if(address < 32)
|
if(address < 32)
|
value = mfspr(address);
|
value = mfspr(address);
|
else if(address >= 0x0400 && address < 0x0420)
|
else if(address >= 0x0400 && address < 0x0420)
|
value = reg[address - 0x400];
|
value = reg[address - 0x400];
|
else if(address >= 0x0600 && address < 0x0620)
|
else if(address >= 0x0600 && address < 0x0620)
|
value = 0;
|
value = 0;
|
else
|
else
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
}
|
}
|
else
|
else
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
|
|
*data = value;
|
*data = value;
|
return err;
|
return err;
|
}
|
}
|
|
|
/* Nearly all compilers today store these bit fields as a packed structure
|
/* Nearly all compilers today store these bit fields as a packed structure
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
to be working in a non standard environment, you may need to rewrite
|
to be working in a non standard environment, you may need to rewrite
|
this routine or the SET_REG32 macro. */
|
this routine or the SET_REG32 macro. */
|
int SetWishboneMemory(unsigned int address,uint32_t data)
|
int SetWishboneMemory(unsigned int address,uint32_t data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
uint32_t value = data;
|
uint32_t value = data;
|
int old_value;
|
int old_value;
|
int group = address >> 11;
|
int group = address >> 11;
|
|
|
address <<= 2;
|
address <<= 2;
|
|
|
if(!verify_memoryarea(address))
|
if(!verify_memoryarea(address))
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
else
|
else
|
{
|
{
|
unsigned char t_data[4];
|
unsigned char t_data[4];
|
int *tmp = (int*)t_data;
|
int *tmp = (int*)t_data;
|
extern char null_str[1]; /* From cpu/common/parse.c */
|
extern char null_str[1]; /* From cpu/common/parse.c */
|
int i;
|
int i;
|
|
|
*tmp = htonl(data); /* We have already converted to host order */
|
*tmp = htonl(data); /* We have already converted to host order */
|
|
|
setsim_mem8(address++, t_data[0]); /* Back to network byte order */
|
setsim_mem8(address++, t_data[0]); /* Back to network byte order */
|
setsim_mem8(address++, t_data[1]);
|
setsim_mem8(address++, t_data[1]);
|
setsim_mem8(address++, t_data[2]);
|
setsim_mem8(address++, t_data[2]);
|
setsim_mem8(address++, t_data[3]);
|
setsim_mem8(address++, t_data[3]);
|
}
|
}
|
return err;
|
return err;
|
}
|
}
|
|
|
int GetWishboneMemory(unsigned int address,uint32_t *data)
|
int GetWishboneMemory(unsigned int address,uint32_t *data)
|
{
|
{
|
int err = 0;
|
int err = 0;
|
uint32_t value = 0;
|
uint32_t value = 0;
|
int group = address >> 11;
|
int group = address >> 11;
|
|
|
address <<= 2;
|
address <<= 2;
|
|
|
if(!verify_memoryarea(address))
|
if(!verify_memoryarea(address))
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
else
|
else
|
{
|
{
|
unsigned char t_data[4];
|
unsigned char t_data[4];
|
int *tmp = (int*)t_data;
|
int *tmp = (int*)t_data;
|
int bp;
|
int bp;
|
|
|
t_data[0] = evalsim_mem8(address++);
|
t_data[0] = evalsim_mem8(address++);
|
t_data[1] = evalsim_mem8(address++);
|
t_data[1] = evalsim_mem8(address++);
|
t_data[2] = evalsim_mem8(address++);
|
t_data[2] = evalsim_mem8(address++);
|
t_data[3] = evalsim_mem8(address++); /* Already in network byte order */
|
t_data[3] = evalsim_mem8(address++); /* Already in network byte order */
|
|
|
*data = ntohl(*tmp); /* But we assume it is in host order later */
|
*data = ntohl(*tmp); /* But we assume it is in host order later */
|
}
|
}
|
return err;
|
return err;
|
}
|
}
|
|
|
/* DebugCheckException returns 1 if the exception should be ignored.
|
/* DebugCheckException returns 1 if the exception should be ignored.
|
Currently, this is true only if the exception is a breakpoint
|
Currently, this is true only if the exception is a breakpoint
|
exception and debug_unit.DMR1.ST is set. Sorry, this is a quick
|
exception and debug_unit.DMR1.ST is set. Sorry, this is a quick
|
hack to disable processing of breakpoint exceptions on single
|
hack to disable processing of breakpoint exceptions on single
|
stepping. Just one of those historical accidents. Feel free
|
stepping. Just one of those historical accidents. Feel free
|
to rewrite the behavior. */
|
to rewrite the behavior. */
|
int DebugCheckException(int exception)
|
int DebugCheckException(int exception)
|
{
|
{
|
int result = 0;
|
int result = 0;
|
|
|
switch(exception)
|
switch(exception)
|
{
|
{
|
case EXCEPT_RESET: result = debug_unit.DRR.RSTE = debug_unit.DSR.RSTE; break;
|
case EXCEPT_RESET: result = debug_unit.DRR.RSTE = debug_unit.DSR.RSTE; break;
|
case EXCEPT_BUSERR: result = debug_unit.DRR.BUSEE = debug_unit.DSR.BUSEE; break;
|
case EXCEPT_BUSERR: result = debug_unit.DRR.BUSEE = debug_unit.DSR.BUSEE; break;
|
case EXCEPT_DPF: result = debug_unit.DRR.DPFE = debug_unit.DSR.DPFE; break;
|
case EXCEPT_DPF: result = debug_unit.DRR.DPFE = debug_unit.DSR.DPFE; break;
|
case EXCEPT_IPF: result = debug_unit.DRR.IPFE = debug_unit.DSR.IPFE; break;
|
case EXCEPT_IPF: result = debug_unit.DRR.IPFE = debug_unit.DSR.IPFE; break;
|
case EXCEPT_LPINT: result = debug_unit.DRR.LPINTE = debug_unit.DSR.LPINTE; break;
|
case EXCEPT_LPINT: result = debug_unit.DRR.LPINTE = debug_unit.DSR.LPINTE; break;
|
case EXCEPT_ALIGN: result = debug_unit.DRR.AE = debug_unit.DSR.AE; break;
|
case EXCEPT_ALIGN: result = debug_unit.DRR.AE = debug_unit.DSR.AE; break;
|
case EXCEPT_ILLEGAL: result = debug_unit.DRR.IIE = debug_unit.DSR.IIE; break;
|
case EXCEPT_ILLEGAL: result = debug_unit.DRR.IIE = debug_unit.DSR.IIE; break;
|
case EXCEPT_HPINT: result = debug_unit.DRR.HPINTE = debug_unit.DSR.HPINTE; break;
|
case EXCEPT_HPINT: result = debug_unit.DRR.HPINTE = debug_unit.DSR.HPINTE; break;
|
case EXCEPT_DTLBMISS: result = debug_unit.DRR.DME = debug_unit.DSR.DME; break;
|
case EXCEPT_DTLBMISS: result = debug_unit.DRR.DME = debug_unit.DSR.DME; break;
|
case EXCEPT_ITLBMISS: result = debug_unit.DRR.IME = debug_unit.DSR.IME; break;
|
case EXCEPT_ITLBMISS: result = debug_unit.DRR.IME = debug_unit.DSR.IME; break;
|
case EXCEPT_RANGE: result = debug_unit.DRR.RE = debug_unit.DSR.RE; break;
|
case EXCEPT_RANGE: result = debug_unit.DRR.RE = debug_unit.DSR.RE; break;
|
case EXCEPT_SYSCALL: result = debug_unit.DRR.SCE = debug_unit.DSR.SCE; break;
|
case EXCEPT_SYSCALL: result = debug_unit.DRR.SCE = debug_unit.DSR.SCE; break;
|
case EXCEPT_BREAK: result = debug_unit.DRR.BE = debug_unit.DSR.BE; break;
|
case EXCEPT_BREAK: result = debug_unit.DRR.BE = debug_unit.DSR.BE; break;
|
case EXCEPT_TRAP: result = debug_unit.DRR.TE = debug_unit.DSR.TE; break;
|
case EXCEPT_TRAP: result = debug_unit.DRR.TE = debug_unit.DSR.TE; break;
|
default:
|
default:
|
break;
|
break;
|
}
|
}
|
|
|
if(result)
|
if(result)
|
SetCPUStallState(true);
|
SetCPUStallState(true);
|
|
|
return (debug_unit.DMR1.ST && exception == EXCEPT_BREAK);
|
return (debug_unit.DMR1.ST && exception == EXCEPT_BREAK);
|
}
|
}
|
|
|
