/* 16450.c -- Simulation of 8250/16450 serial UART
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/* 16450.c -- Simulation of 8250/16450 serial UART
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
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/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
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via file streams, we can't simulate modem control lines coming from the
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via file streams, we can't simulate modem control lines coming from the
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DCE and similar details of communication with the DCE.
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DCE and similar details of communication with the DCE.
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This simulated UART device is intended for basic UART device driver
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This simulated UART device is intended for basic UART device driver
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verification. From device driver perspective this device looks like a
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verification. From device driver perspective this device looks like a
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regular UART but never reports and modem control lines changes (the
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regular UART but never reports and modem control lines changes (the
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only DCE responses are incoming characters from the file stream).
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only DCE responses are incoming characters from the file stream).
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "16450.h"
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#include "16450.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "pic.h"
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#include "pic.h"
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#include "vapi.h"
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#include "vapi.h"
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#include "sched.h"
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#include "sched.h"
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#include "channel.h"
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#include "channel.h"
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#include "debug.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL(uart);
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DEFAULT_DEBUG_CHANNEL(uart);
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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/* Number of clock cycles (one clock cycle is one call to the uart_clock())
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before a single character is transmitted or received. */
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before a single character is transmitted or received. */
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static unsigned long char_clks(int dll, int dlh, int lcr)
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static unsigned long char_clks(int dll, int dlh, int lcr)
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{
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{
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unsigned int bauds_per_char = 2;
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unsigned int bauds_per_char = 2;
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unsigned long char_clks = ((dlh << 8) + dll);
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unsigned long char_clks = ((dlh << 8) + dll);
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if (lcr & UART_LCR_PARITY)
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if (lcr & UART_LCR_PARITY)
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bauds_per_char += 2;
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bauds_per_char += 2;
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/* stop bits 1 or two */
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/* stop bits 1 or two */
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if (lcr & UART_LCR_STOP)
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if (lcr & UART_LCR_STOP)
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bauds_per_char += 4;
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bauds_per_char += 4;
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else
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else
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if ((lcr & 0x3) != 0)
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if ((lcr & 0x3) != 0)
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bauds_per_char += 2;
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bauds_per_char += 2;
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else
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else
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bauds_per_char += 3;
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bauds_per_char += 3;
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bauds_per_char += 10 + ((lcr & 0x3) << 1);
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bauds_per_char += 10 + ((lcr & 0x3) << 1);
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return (char_clks * bauds_per_char) >> 1;
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return (char_clks * bauds_per_char) >> 1;
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}
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}
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/* Set a specific UART register with value. */
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/* Set a specific UART register with value. */
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void uart_write_byte(oraddr_t addr, uint32_t value, void *dat)
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void uart_write_byte(oraddr_t addr, uint32_t value, void *dat)
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{
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{
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struct dev_16450 *uart = dat;
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struct dev_16450 *uart = dat;
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TRACE("uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);
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TRACE("uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);
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if (uart->regs.lcr & UART_LCR_DLAB) {
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if (uart->regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
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uart->regs.dll = value;
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uart->regs.dll = value;
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uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
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uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
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TRACE("\tSetting char_clks to %li (%02x, %02x, %02x)\n", uart->char_clks,
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TRACE("\tSetting char_clks to %li (%02x, %02x, %02x)\n", uart->char_clks,
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uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
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uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
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return;
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return;
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case UART_DLH:
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case UART_DLH:
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uart->regs.dlh = value;
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uart->regs.dlh = value;
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return;
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return;
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}
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}
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}
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}
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_TXBUF:
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case UART_TXBUF:
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if (uart->istat.txbuf_full < uart->fifo_len) {
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if (uart->istat.txbuf_full < uart->fifo_len) {
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uart->istat.txbuf_full++;
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uart->istat.txbuf_full++;
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uart->regs.txbuf[uart->istat.txbuf_head] = value;
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uart->regs.txbuf[uart->istat.txbuf_head] = value;
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uart->istat.txbuf_head = (uart->istat.txbuf_head + 1) % uart->fifo_len;
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uart->istat.txbuf_head = (uart->istat.txbuf_head + 1) % uart->fifo_len;
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} else
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} else
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uart->regs.txbuf[uart->istat.txbuf_head] = value;
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uart->regs.txbuf[uart->istat.txbuf_head] = value;
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uart->regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
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uart->regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
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if (uart->regs.iir & UART_IIR_THRI)
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if (uart->regs.iir & UART_IIR_THRI)
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uart->istat.thre_int = 0;
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uart->istat.thre_int = 0;
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break;
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break;
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case UART_FCR:
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case UART_FCR:
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uart->regs.fcr = value & UART_VALID_FCR;
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uart->regs.fcr = value & UART_VALID_FCR;
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if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))
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if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))
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|| (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))
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|| (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))
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value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
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value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
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uart->fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
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uart->fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
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if (value & UART_FCR_RTXFI) {
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if (value & UART_FCR_RTXFI) {
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uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
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uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
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uart->istat.txbuf_full = 0;
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uart->istat.txbuf_full = 0;
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uart->regs.lsr |= UART_LSR_TXBUFE;
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uart->regs.lsr |= UART_LSR_TXBUFE;
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// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
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// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
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uart->istat.thre_int = (uart->fifo_len == 16);
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uart->istat.thre_int = (uart->fifo_len == 16);
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}
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}
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if (value & UART_FCR_RRXFI) {
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if (value & UART_FCR_RRXFI) {
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uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
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uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
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uart->istat.rxbuf_full = 0;
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uart->istat.rxbuf_full = 0;
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uart->regs.lsr &= ~UART_LSR_RDRDY;
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uart->regs.lsr &= ~UART_LSR_RDRDY;
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}
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}
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break;
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break;
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case UART_IER:
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case UART_IER:
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uart->regs.ier = value & UART_VALID_IER;
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uart->regs.ier = value & UART_VALID_IER;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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uart->regs.lcr = value & UART_VALID_LCR;
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uart->regs.lcr = value & UART_VALID_LCR;
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uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
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uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
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break;
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break;
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case UART_MCR:
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case UART_MCR:
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uart->regs.mcr = value & UART_VALID_MCR;
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uart->regs.mcr = value & UART_VALID_MCR;
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break;
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break;
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case UART_SCR:
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case UART_SCR:
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uart->regs.scr = value;
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uart->regs.scr = value;
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break;
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break;
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default:
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default:
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TRACE("write out of range (addr %x)\n", addr);
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TRACE("write out of range (addr %x)\n", addr);
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}
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}
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}
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}
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/* Read a specific UART register. */
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/* Read a specific UART register. */
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uint32_t uart_read_byte(oraddr_t addr, void *dat)
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uint32_t uart_read_byte(oraddr_t addr, void *dat)
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{
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{
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struct dev_16450 *uart = dat;
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struct dev_16450 *uart = dat;
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uint8_t value = 0;
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uint8_t value = 0;
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TRACE("uart_read_byte(%"PRIxADDR")", addr);
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TRACE("uart_read_byte(%"PRIxADDR")", addr);
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if (uart->regs.lcr & UART_LCR_DLAB) {
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if (uart->regs.lcr & UART_LCR_DLAB) {
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_DLL:
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case UART_DLL:
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value = uart->regs.dll;
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value = uart->regs.dll;
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TRACE("= %"PRIx8"\n", value);
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TRACE("= %"PRIx8"\n", value);
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return value;
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return value;
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case UART_DLH:
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case UART_DLH:
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value = uart->regs.dlh;
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value = uart->regs.dlh;
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TRACE("= %"PRIx8"\n", value);
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TRACE("= %"PRIx8"\n", value);
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return value;
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return value;
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}
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}
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}
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}
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switch (addr % UART_ADDR_SPACE) {
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switch (addr % UART_ADDR_SPACE) {
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case UART_RXBUF:
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case UART_RXBUF:
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{ /* Print out FIFO for debugging */
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{ /* Print out FIFO for debugging */
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int i;
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int i;
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TRACE("(%i/%i, %i, %i:", uart->istat.rxbuf_full, uart->fifo_len,
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TRACE("(%i/%i, %i, %i:", uart->istat.rxbuf_full, uart->fifo_len,
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uart->istat.rxbuf_head, uart->istat.rxbuf_tail);
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uart->istat.rxbuf_head, uart->istat.rxbuf_tail);
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for (i = 0; i < uart->istat.rxbuf_full; i++)
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for (i = 0; i < uart->istat.rxbuf_full; i++)
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TRACE("%02x ", uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) % uart->fifo_len]);
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TRACE("%02x ", uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) % uart->fifo_len]);
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TRACE(")");
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TRACE(")");
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}
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}
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if (uart->istat.rxbuf_full) {
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if (uart->istat.rxbuf_full) {
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value = uart->regs.rxbuf[uart->istat.rxbuf_tail];
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value = uart->regs.rxbuf[uart->istat.rxbuf_tail];
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uart->istat.rxbuf_tail = (uart->istat.rxbuf_tail + 1) % uart->fifo_len;
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uart->istat.rxbuf_tail = (uart->istat.rxbuf_tail + 1) % uart->fifo_len;
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uart->istat.rxbuf_full--;
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uart->istat.rxbuf_full--;
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}
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}
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if (uart->istat.rxbuf_full)
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if (uart->istat.rxbuf_full)
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uart->regs.lsr |= UART_LSR_RDRDY;
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uart->regs.lsr |= UART_LSR_RDRDY;
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else
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else
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uart->regs.lsr &= ~UART_LSR_RDRDY;
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uart->regs.lsr &= ~UART_LSR_RDRDY;
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|
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uart->istat.timeout_count = 0;
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uart->istat.timeout_count = 0;
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break;
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break;
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case UART_IER:
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case UART_IER:
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value = uart->regs.ier & UART_VALID_IER;
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value = uart->regs.ier & UART_VALID_IER;
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break;
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break;
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case UART_IIR:
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case UART_IIR:
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value = (uart->regs.iir & UART_VALID_IIR) | 0xc0;
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value = (uart->regs.iir & UART_VALID_IIR) | 0xc0;
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if (uart->regs.iir & UART_IIR_THRI)
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if (uart->regs.iir & UART_IIR_THRI)
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uart->istat.thre_int = 0;
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uart->istat.thre_int = 0;
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break;
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break;
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case UART_LCR:
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case UART_LCR:
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value = uart->regs.lcr & UART_VALID_LCR;
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value = uart->regs.lcr & UART_VALID_LCR;
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break;
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break;
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case UART_MCR:
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case UART_MCR:
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value = 0;
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value = 0;
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break;
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break;
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case UART_LSR:
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case UART_LSR:
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value = uart->regs.lsr & UART_VALID_LSR;
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value = uart->regs.lsr & UART_VALID_LSR;
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uart->regs.lsr &=
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uart->regs.lsr &=
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~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
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~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
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| UART_LSR_FRAME | UART_LSR_RXERR);
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| UART_LSR_FRAME | UART_LSR_RXERR);
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break;
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break;
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case UART_MSR:
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case UART_MSR:
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value = uart->regs.msr & UART_VALID_MSR;
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value = uart->regs.msr & UART_VALID_MSR;
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uart->regs.msr = 0;
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uart->regs.msr = 0;
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break;
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break;
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case UART_SCR:
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case UART_SCR:
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value = uart->regs.scr;
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value = uart->regs.scr;
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break;
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break;
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default:
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default:
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TRACE("read out of range (addr %"PRIxADDR")\n", addr);
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TRACE("read out of range (addr %"PRIxADDR")\n", addr);
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}
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}
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TRACE(" = %"PRIx8"\n", value);
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TRACE(" = %"PRIx8"\n", value);
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return value;
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return value;
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}
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}
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|
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/* Function that handles incoming VAPI data. */
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/* Function that handles incoming VAPI data. */
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void uart_vapi_read (unsigned long id, unsigned long data, void *dat)
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void uart_vapi_read (unsigned long id, unsigned long data, void *dat)
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{
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{
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struct dev_16450 *uart = dat;
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struct dev_16450 *uart = dat;
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TRACE("UART: id %08lx, data %08lx\n", id, data);
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TRACE("UART: id %08lx, data %08lx\n", id, data);
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uart->vapi_buf[uart->vapi_buf_head_ptr] = data;
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uart->vapi_buf[uart->vapi_buf_head_ptr] = data;
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uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
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uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
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if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr) {
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if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr) {
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fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
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fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
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exit (1);
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exit (1);
|
}
|
}
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}
|
}
|
|
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static void send_char (struct dev_16450 *uart, int bits_send)
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static void send_char (struct dev_16450 *uart, int bits_send)
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{
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{
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PRINTF ("%c", (char)uart->iregs.txser);
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PRINTF ("%c", (char)uart->iregs.txser);
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TRACE("TX \'%c\' via UART at %"PRIxADDR"...\n", (char)uart->iregs.txser,
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TRACE("TX \'%c\' via UART at %"PRIxADDR"...\n", (char)uart->iregs.txser,
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uart->baseaddr);
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uart->baseaddr);
|
if (uart->regs.mcr & UART_MCR_LOOP)
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if (uart->regs.mcr & UART_MCR_LOOP)
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uart->iregs.loopback = uart->iregs.txser;
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uart->iregs.loopback = uart->iregs.txser;
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else {
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else {
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/* Send to either VAPI or to file */
|
/* Send to either VAPI or to file */
|
if (uart->vapi_id) {
|
if (uart->vapi_id) {
|
int par, pe, fe, nbits;
|
int par, pe, fe, nbits;
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int j, data;
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int j, data;
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unsigned long packet = 0;
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unsigned long packet = 0;
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|
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nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
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nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
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/* Encode a packet */
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/* Encode a packet */
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packet = uart->iregs.txser & ((1 << nbits) - 1);
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packet = uart->iregs.txser & ((1 << nbits) - 1);
|
|
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/* Calculate parity */
|
/* Calculate parity */
|
for (j = 0, par = 0; j < nbits; j++)
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for (j = 0, par = 0; j < nbits; j++)
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par ^= (packet >> j) & 1;
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par ^= (packet >> j) & 1;
|
|
|
if (uart->regs.lcr & UART_LCR_PARITY) {
|
if (uart->regs.lcr & UART_LCR_PARITY) {
|
if (uart->regs.lcr & UART_LCR_SPAR) {
|
if (uart->regs.lcr & UART_LCR_SPAR) {
|
packet |= 1 << nbits;
|
packet |= 1 << nbits;
|
} else {
|
} else {
|
if (uart->regs.lcr & UART_LCR_EPAR)
|
if (uart->regs.lcr & UART_LCR_EPAR)
|
packet |= par << nbits;
|
packet |= par << nbits;
|
else
|
else
|
packet |= (par ^ 1) << nbits;
|
packet |= (par ^ 1) << nbits;
|
}
|
}
|
nbits++;
|
nbits++;
|
}
|
}
|
packet |= 1 << (nbits++);
|
packet |= 1 << (nbits++);
|
if (uart->regs.lcr & UART_LCR_STOP)
|
if (uart->regs.lcr & UART_LCR_STOP)
|
packet |= 1 << (nbits++);
|
packet |= 1 << (nbits++);
|
|
|
/* Decode a packet */
|
/* Decode a packet */
|
nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;
|
nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;
|
data = packet & ((1 << nbits) - 1);
|
data = packet & ((1 << nbits) - 1);
|
|
|
/* Calculate parity, including parity bit */
|
/* Calculate parity, including parity bit */
|
for (j = 0, par = 0; j < nbits + 1; j++)
|
for (j = 0, par = 0; j < nbits + 1; j++)
|
par ^= (packet >> j) & 1;
|
par ^= (packet >> j) & 1;
|
|
|
if (uart->vapi.lcr & UART_LCR_PARITY) {
|
if (uart->vapi.lcr & UART_LCR_PARITY) {
|
if (uart->vapi.lcr & UART_LCR_SPAR) {
|
if (uart->vapi.lcr & UART_LCR_SPAR) {
|
pe = !((packet >> nbits) & 1);
|
pe = !((packet >> nbits) & 1);
|
} else {
|
} else {
|
if (uart->vapi.lcr & UART_LCR_EPAR)
|
if (uart->vapi.lcr & UART_LCR_EPAR)
|
pe = par != 0;
|
pe = par != 0;
|
else
|
else
|
pe = par != 1;
|
pe = par != 1;
|
}
|
}
|
nbits++;
|
nbits++;
|
} else
|
} else
|
pe = 0;
|
pe = 0;
|
|
|
fe = ((packet >> (nbits++)) & 1) ^ 1;
|
fe = ((packet >> (nbits++)) & 1) ^ 1;
|
if (uart->vapi.lcr & UART_LCR_STOP)
|
if (uart->vapi.lcr & UART_LCR_STOP)
|
fe |= ((packet >> (nbits++)) & 1) ^ 1;
|
fe |= ((packet >> (nbits++)) & 1) ^ 1;
|
|
|
TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);
|
TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);
|
data |= (uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.lcr << 8);
|
data |= (uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.lcr << 8);
|
PRINTF ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
|
PRINTF ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
|
TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
|
TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
|
vapi_send (uart->vapi_id, data);
|
vapi_send (uart->vapi_id, data);
|
} else {
|
} else {
|
char buffer[1] = { uart->iregs.txser & 0xFF };
|
char buffer[1] = { uart->iregs.txser & 0xFF };
|
channel_write(uart->channel, buffer, 1);
|
channel_write(uart->channel, buffer, 1);
|
}
|
}
|
}
|
}
|
uart->istat.txser_full = 0;
|
uart->istat.txser_full = 0;
|
uart->istat.txser_clks = 0;
|
uart->istat.txser_clks = 0;
|
}
|
}
|
|
|
/* Adds a character to the FIFO */
|
/* Adds a character to the FIFO */
|
|
|
void uart_add_char (struct dev_16450 *uart, int ch)
|
void uart_add_char (struct dev_16450 *uart, int ch)
|
{
|
{
|
if (uart->istat.rxbuf_full + 1 > uart->fifo_len)
|
if (uart->istat.rxbuf_full + 1 > uart->fifo_len)
|
uart->regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
uart->regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
|
else {
|
else {
|
TRACE("add %02x\n", ch);
|
TRACE("add %02x\n", ch);
|
uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;
|
uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;
|
uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;
|
uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;
|
uart->istat.rxbuf_full++;
|
uart->istat.rxbuf_full++;
|
}
|
}
|
uart->regs.lsr |= UART_LSR_RDRDY;
|
uart->regs.lsr |= UART_LSR_RDRDY;
|
uart->istat.timeout_count = 0;
|
uart->istat.timeout_count = 0;
|
}
|
}
|
|
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
|
/* Simulation hook. Must be called every clock cycle to simulate all UART
|
devices. It does internal functional UART simulation. */
|
devices. It does internal functional UART simulation. */
|
void uart_clock16 (void *dat)
|
void uart_clock16 (void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
int retval;
|
int retval;
|
|
|
/* Schedule for later */
|
/* Schedule for later */
|
SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
|
SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
|
|
|
TRACE("Running uart clock:\n");
|
TRACE("Running uart clock:\n");
|
|
|
/* If VAPI is not selected, UART communicates with two file streams;
|
/* If VAPI is not selected, UART communicates with two file streams;
|
if VAPI is selected, we use VAPI streams. */
|
if VAPI is selected, we use VAPI streams. */
|
/* if txfs is corrupted, skip this uart. */
|
/* if txfs is corrupted, skip this uart. */
|
if (!uart->vapi_id && !channel_ok(uart->channel)) return;
|
if (!uart->vapi_id && !channel_ok(uart->channel)) return;
|
|
|
TRACE("\tChannel stream or VAPI checks out ok\n");
|
TRACE("\tChannel stream or VAPI checks out ok\n");
|
|
|
if (uart->vapi.next_break_cnt >= 0)
|
if (uart->vapi.next_break_cnt >= 0)
|
if (--uart->vapi.next_break_cnt < 0) {
|
if (--uart->vapi.next_break_cnt < 0) {
|
if (!(uart->vapi.cur_break = uart->vapi.next_break))
|
if (!(uart->vapi.cur_break = uart->vapi.next_break))
|
uart->istat.break_set = 0;
|
uart->istat.break_set = 0;
|
}
|
}
|
|
|
/***************** Transmit *****************/
|
/***************** Transmit *****************/
|
TRACE("\tuart->istat.txser_full = %i\n", uart->istat.txser_full);
|
TRACE("\tuart->istat.txser_full = %i\n", uart->istat.txser_full);
|
TRACE("\tuart->istat.txbuf_full = %i\n", uart->istat.txser_full);
|
TRACE("\tuart->istat.txbuf_full = %i\n", uart->istat.txser_full);
|
TRACE("\tuart->char_clks = %li\n", uart->char_clks);
|
TRACE("\tuart->char_clks = %li\n", uart->char_clks);
|
if (!uart->istat.txser_full) {
|
if (!uart->istat.txser_full) {
|
// uart->regs.lsr |= UART_LSR_TXBUFE;
|
// uart->regs.lsr |= UART_LSR_TXBUFE;
|
if (uart->istat.txbuf_full) {
|
if (uart->istat.txbuf_full) {
|
uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
|
uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
|
uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
|
uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
|
uart->istat.txser_full = 1;
|
uart->istat.txser_full = 1;
|
uart->istat.txbuf_full--;
|
uart->istat.txbuf_full--;
|
uart->regs.lsr &= ~UART_LSR_TXSERE;
|
uart->regs.lsr &= ~UART_LSR_TXSERE;
|
|
|
// When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,
|
// When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,
|
// the THRE interrupt is raised when THR transitions from full to empty.
|
// the THRE interrupt is raised when THR transitions from full to empty.
|
if (!uart->istat.txbuf_full) {
|
if (!uart->istat.txbuf_full) {
|
uart->istat.thre_int = 1;
|
uart->istat.thre_int = 1;
|
uart->regs.lsr |= UART_LSR_TXBUFE;
|
uart->regs.lsr |= UART_LSR_TXBUFE;
|
}
|
}
|
} else {
|
} else {
|
uart->regs.lsr |= UART_LSR_TXSERE;
|
uart->regs.lsr |= UART_LSR_TXSERE;
|
}
|
}
|
} else if (uart->char_clks <= uart->istat.txser_clks++) {
|
} else if (uart->char_clks <= uart->istat.txser_clks++) {
|
send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
|
send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
|
} else {
|
} else {
|
/* We are still sending char here*/
|
/* We are still sending char here*/
|
|
|
/* Check if we set the break bit */
|
/* Check if we set the break bit */
|
if (uart->regs.lcr & UART_LCR_SBC) {
|
if (uart->regs.lcr & UART_LCR_SBC) {
|
if (!uart->vapi.break_sent) {
|
if (!uart->vapi.break_sent) {
|
#if 0
|
#if 0
|
/* Send broken frame */
|
/* Send broken frame */
|
int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;
|
int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;
|
send_char(i, nbits_sent);
|
send_char(i, nbits_sent);
|
#endif
|
#endif
|
/* Send one break signal */
|
/* Send one break signal */
|
vapi_send (uart->vapi_id, UART_LCR_SBC << 8);
|
vapi_send (uart->vapi_id, UART_LCR_SBC << 8);
|
uart->vapi.break_sent = 1;
|
uart->vapi.break_sent = 1;
|
}
|
}
|
/* mark as character was sent */
|
/* mark as character was sent */
|
uart->istat.txser_full = 0;
|
uart->istat.txser_full = 0;
|
uart->istat.txser_clks = 0;
|
uart->istat.txser_clks = 0;
|
} else
|
} else
|
uart->vapi.break_sent = 0;
|
uart->vapi.break_sent = 0;
|
|
|
}
|
}
|
|
|
/***************** Receive *****************/
|
/***************** Receive *****************/
|
|
|
/* Is there a break? */
|
/* Is there a break? */
|
if (uart->vapi.cur_break) {
|
if (uart->vapi.cur_break) {
|
uart->vapi.cur_break_cnt++;
|
uart->vapi.cur_break_cnt++;
|
if (uart->vapi.cur_break_cnt > UART_BREAK_COUNT * uart->vapi.char_clks) {
|
if (uart->vapi.cur_break_cnt > UART_BREAK_COUNT * uart->vapi.char_clks) {
|
if (!uart->istat.break_set) {
|
if (!uart->istat.break_set) {
|
unsigned lsr;
|
unsigned lsr;
|
uart->istat.break_set = 1;
|
uart->istat.break_set = 1;
|
lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
|
lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
|
PRINTF ("[%x]\n", uart->regs.lsr);
|
PRINTF ("[%x]\n", uart->regs.lsr);
|
uart->istat.rxser_full = 0;
|
uart->istat.rxser_full = 0;
|
uart->istat.rxser_clks = 0;
|
uart->istat.rxser_clks = 0;
|
uart_add_char (uart, lsr << 8);
|
uart_add_char (uart, lsr << 8);
|
} else
|
} else
|
uart->vapi.cur_break_cnt = 0;
|
uart->vapi.cur_break_cnt = 0;
|
}
|
}
|
if (uart->istat.rxser_full) {
|
if (uart->istat.rxser_full) {
|
uart->istat.rxser_full = 0;
|
uart->istat.rxser_full = 0;
|
uart->istat.rxser_clks = 0;
|
uart->istat.rxser_clks = 0;
|
}
|
}
|
} else {
|
} else {
|
if (uart->istat.rxser_full) {
|
if (uart->istat.rxser_full) {
|
if (uart->char_clks <= uart->istat.rxser_clks++) {
|
if (uart->char_clks <= uart->istat.rxser_clks++) {
|
/* Set unused character bits to zero and allow lsr register in fifo */
|
/* Set unused character bits to zero and allow lsr register in fifo */
|
uart->iregs.rxser &= ((1 << ((uart->regs.lcr & 3) + 5)) - 1) | 0xff00;
|
uart->iregs.rxser &= ((1 << ((uart->regs.lcr & 3) + 5)) - 1) | 0xff00;
|
TRACE("\tReceiving 0x%02lx'%c' via UART (at %"PRIxADDR"...\n",
|
TRACE("\tReceiving 0x%02lx'%c' via UART (at %"PRIxADDR"...\n",
|
uart->iregs.rxser, (char)uart->iregs.rxser, uart->baseaddr);
|
uart->iregs.rxser, (char)uart->iregs.rxser, uart->baseaddr);
|
PRINTF ("%c", (char)uart->iregs.rxser);
|
PRINTF ("%c", (char)uart->iregs.rxser);
|
uart->istat.rxser_full = 0;
|
uart->istat.rxser_full = 0;
|
uart->istat.rxser_clks = 0;
|
uart->istat.rxser_clks = 0;
|
uart_add_char (uart, uart->iregs.rxser);
|
uart_add_char (uart, uart->iregs.rxser);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Check if there is something waiting, and put it into rxser */
|
/* Check if there is something waiting, and put it into rxser */
|
if (uart->regs.mcr & UART_MCR_LOOP) {
|
if (uart->regs.mcr & UART_MCR_LOOP) {
|
uart->iregs.rxser = uart->iregs.loopback;
|
uart->iregs.rxser = uart->iregs.loopback;
|
uart->istat.rxser_full = 1;
|
uart->istat.rxser_full = 1;
|
} else {
|
} else {
|
if (!uart->vapi_id) {
|
if (!uart->vapi_id) {
|
if(uart->istat.rxser_full == 0) {
|
if(uart->istat.rxser_full == 0) {
|
if (uart->slowdown)
|
if (uart->slowdown)
|
uart->slowdown--;
|
uart->slowdown--;
|
else {
|
else {
|
char buffer[1];
|
char buffer[1];
|
retval = channel_read(uart->channel, buffer, 1);
|
retval = channel_read(uart->channel, buffer, 1);
|
if(retval < 0)
|
if(retval < 0)
|
perror(uart->channel_str);
|
perror(uart->channel_str);
|
else if(retval > 0) {
|
else if(retval > 0) {
|
uart->iregs.rxser = (unsigned char)buffer[0];
|
uart->iregs.rxser = (unsigned char)buffer[0];
|
uart->istat.rxser_full = 1;
|
uart->istat.rxser_full = 1;
|
} else
|
} else
|
uart->slowdown = UART_FGETC_SLOWDOWN;
|
uart->slowdown = UART_FGETC_SLOWDOWN;
|
}
|
}
|
}
|
}
|
} else { /* VAPI */
|
} else { /* VAPI */
|
int received = 0;
|
int received = 0;
|
/* do not handle commands while receiving */
|
/* do not handle commands while receiving */
|
if (uart->istat.rxser_full) return;
|
if (uart->istat.rxser_full) return;
|
while (!received) {
|
while (!received) {
|
if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr) {
|
if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr) {
|
unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];
|
unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];
|
TRACE("\tHandling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,
|
TRACE("\tHandling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,
|
uart->vapi_buf_tail_ptr);
|
uart->vapi_buf_tail_ptr);
|
uart->vapi_buf_tail_ptr = (uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
uart->vapi_buf_tail_ptr = (uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
|
switch (data >> 24) {
|
switch (data >> 24) {
|
case 0x00:
|
case 0x00:
|
uart->vapi.lcr = (data >> 8) & 0xff;
|
uart->vapi.lcr = (data >> 8) & 0xff;
|
/* Put data into rx fifo */
|
/* Put data into rx fifo */
|
uart->iregs.rxser = data & 0xff;
|
uart->iregs.rxser = data & 0xff;
|
uart->vapi.char_clks = char_clks (uart->vapi.dll, uart->vapi.dlh, uart->vapi.lcr);
|
uart->vapi.char_clks = char_clks (uart->vapi.dll, uart->vapi.dlh, uart->vapi.lcr);
|
if ((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC)
|
if ((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC)
|
|| uart->vapi.char_clks != uart->char_clks
|
|| uart->vapi.char_clks != uart->char_clks
|
|| uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW) {
|
|| uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW) {
|
WARN("WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
WARN("WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
|
uart->vapi.lcr & ~UART_LCR_SBC, uart->regs.lcr & ~UART_LCR_SBC);
|
uart->vapi.lcr & ~UART_LCR_SBC, uart->regs.lcr & ~UART_LCR_SBC);
|
/* Set error bits */
|
/* Set error bits */
|
uart->iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
|
uart->iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
|
if (uart->regs.lcr & UART_LCR_PARITY) uart->iregs.rxser |= UART_LSR_PARITY << 8;
|
if (uart->regs.lcr & UART_LCR_PARITY) uart->iregs.rxser |= UART_LSR_PARITY << 8;
|
}
|
}
|
uart->istat.rxser_full = 1;
|
uart->istat.rxser_full = 1;
|
received = 1;
|
received = 1;
|
break;
|
break;
|
case 0x01:
|
case 0x01:
|
uart->vapi.dll = (data >> 0) & 0xff;
|
uart->vapi.dll = (data >> 0) & 0xff;
|
uart->vapi.dlh = (data >> 8) & 0xff;
|
uart->vapi.dlh = (data >> 8) & 0xff;
|
break;
|
break;
|
case 0x02:
|
case 0x02:
|
uart->vapi.lcr = (data >> 8) & 0xff;
|
uart->vapi.lcr = (data >> 8) & 0xff;
|
break;
|
break;
|
case 0x03:
|
case 0x03:
|
uart->vapi.skew = (signed short)(data & 0xffff);
|
uart->vapi.skew = (signed short)(data & 0xffff);
|
break;
|
break;
|
case 0x04:
|
case 0x04:
|
uart->vapi.next_break_cnt = data & 0xffff;
|
uart->vapi.next_break_cnt = data & 0xffff;
|
uart->vapi.next_break = (data >> 16) & 1;
|
uart->vapi.next_break = (data >> 16) & 1;
|
break;
|
break;
|
default:
|
default:
|
WARN ("WARNING: Invalid vapi command %02lx\n", data >> 24);
|
WARN ("WARNING: Invalid vapi command %02lx\n", data >> 24);
|
break;
|
break;
|
}
|
}
|
} else break;
|
} else break;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/***************** Loopback *****************/
|
/***************** Loopback *****************/
|
if (uart->regs.mcr & UART_MCR_LOOP) {
|
if (uart->regs.mcr & UART_MCR_LOOP) {
|
TRACE("uart_clock: Loopback\n");
|
TRACE("uart_clock: Loopback\n");
|
if ((uart->regs.mcr & UART_MCR_AUX2) !=
|
if ((uart->regs.mcr & UART_MCR_AUX2) !=
|
((uart->regs.msr & UART_MSR_DCD) >> 4))
|
((uart->regs.msr & UART_MSR_DCD) >> 4))
|
uart->regs.msr |= UART_MSR_DDCD;
|
uart->regs.msr |= UART_MSR_DDCD;
|
if ((uart->regs.mcr & UART_MCR_AUX1) <
|
if ((uart->regs.mcr & UART_MCR_AUX1) <
|
((uart->regs.msr & UART_MSR_RI) >> 4))
|
((uart->regs.msr & UART_MSR_RI) >> 4))
|
uart->regs.msr |= UART_MSR_TERI;
|
uart->regs.msr |= UART_MSR_TERI;
|
if ((uart->regs.mcr & UART_MCR_RTS) !=
|
if ((uart->regs.mcr & UART_MCR_RTS) !=
|
((uart->regs.msr & UART_MSR_CTS) >> 3))
|
((uart->regs.msr & UART_MSR_CTS) >> 3))
|
uart->regs.msr |= UART_MSR_DCTS;
|
uart->regs.msr |= UART_MSR_DCTS;
|
if ((uart->regs.mcr & UART_MCR_DTR) !=
|
if ((uart->regs.mcr & UART_MCR_DTR) !=
|
((uart->regs.msr & UART_MSR_DSR) >> 5))
|
((uart->regs.msr & UART_MSR_DSR) >> 5))
|
uart->regs.msr |= UART_MSR_DDSR;
|
uart->regs.msr |= UART_MSR_DDSR;
|
uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
|
uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
|
| UART_MSR_DSR | UART_MSR_CTS);
|
| UART_MSR_DSR | UART_MSR_CTS);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
|
uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
|
}
|
}
|
|
|
if (uart->regs.lsr & UART_LSR_RDRDY)
|
if (uart->regs.lsr & UART_LSR_RDRDY)
|
uart->istat.timeout_count++;
|
uart->istat.timeout_count++;
|
|
|
/* Update LSR error bits from the ones from rx FIFO */
|
/* Update LSR error bits from the ones from rx FIFO */
|
if (uart->istat.rxbuf_full) {
|
if (uart->istat.rxbuf_full) {
|
uart->regs.lsr |= uart->regs.rxbuf[uart->istat.rxbuf_tail] >> 8;
|
uart->regs.lsr |= uart->regs.rxbuf[uart->istat.rxbuf_tail] >> 8;
|
/* we must delete the lsr status, so that we can clear it from lsr */
|
/* we must delete the lsr status, so that we can clear it from lsr */
|
uart->regs.rxbuf[uart->istat.rxbuf_tail] &= 0xff;
|
uart->regs.rxbuf[uart->istat.rxbuf_tail] &= 0xff;
|
}
|
}
|
|
|
/* Interrupt detection in proper priority order. */
|
/* Interrupt detection in proper priority order. */
|
uart->regs.iir = UART_IIR_NO_INT;
|
uart->regs.iir = UART_IIR_NO_INT;
|
if (uart->regs.ier & UART_IER_RLSI && /* Receiver LS */
|
if (uart->regs.ier & UART_IER_RLSI && /* Receiver LS */
|
uart->regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
uart->regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
| UART_LSR_FRAME | UART_LSR_BREAK)) {
|
uart->regs.iir = UART_IIR_RLSI;
|
uart->regs.iir = UART_IIR_RLSI;
|
} else if ((uart->regs.ier & UART_IER_RDI) /* RD available */
|
} else if ((uart->regs.ier & UART_IER_RDI) /* RD available */
|
&& (uart->istat.rxbuf_full >= UART_FIFO_TRIGGER(uart->regs.fcr >> 6))
|
&& (uart->istat.rxbuf_full >= UART_FIFO_TRIGGER(uart->regs.fcr >> 6))
|
&& (uart->regs.lsr & UART_LSR_RDRDY)) {
|
&& (uart->regs.lsr & UART_LSR_RDRDY)) {
|
uart->regs.iir = UART_IIR_RDI;
|
uart->regs.iir = UART_IIR_RDI;
|
} else if ((uart->regs.ier & UART_IER_RDI) /* timeout */
|
} else if ((uart->regs.ier & UART_IER_RDI) /* timeout */
|
&& (uart->istat.timeout_count >= UART_CHAR_TIMEOUT * uart->char_clks)
|
&& (uart->istat.timeout_count >= UART_CHAR_TIMEOUT * uart->char_clks)
|
&& (uart->istat.rxbuf_head != uart->istat.rxbuf_tail)) {
|
&& (uart->istat.rxbuf_head != uart->istat.rxbuf_tail)) {
|
uart->regs.iir = UART_IIR_CTI;
|
uart->regs.iir = UART_IIR_CTI;
|
} else if (uart->regs.ier & UART_IER_THRI && /* Transm. empty */
|
} else if (uart->regs.ier & UART_IER_THRI && /* Transm. empty */
|
uart->istat.thre_int == 1) {
|
uart->istat.thre_int == 1) {
|
uart->regs.iir = UART_IIR_THRI;
|
uart->regs.iir = UART_IIR_THRI;
|
} else if (uart->regs.ier & UART_IER_MSI && /* Modem status */
|
} else if (uart->regs.ier & UART_IER_MSI && /* Modem status */
|
uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
| UART_MSR_TERI | UART_MSR_DDCD)) {
|
uart->regs.iir = UART_IIR_MSI;
|
uart->regs.iir = UART_IIR_MSI;
|
}
|
}
|
if (!(uart->regs.iir & UART_IIR_NO_INT)) {
|
if (!(uart->regs.iir & UART_IIR_NO_INT)) {
|
TRACE("\tuart->regs.iir = %i\t", uart->regs.iir);
|
TRACE("\tuart->regs.iir = %i\t", uart->regs.iir);
|
report_interrupt(uart->irq);
|
report_interrupt(uart->irq);
|
}
|
}
|
}
|
}
|
|
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
/* Reset. It initializes all registers of all UART devices to zero values,
|
(re)opens all RX/TX file streams and places devices in memory address
|
(re)opens all RX/TX file streams and places devices in memory address
|
space. */
|
space. */
|
void uart_reset(void *dat)
|
void uart_reset(void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
|
|
if(uart->vapi_id) {
|
if(uart->vapi_id) {
|
vapi_install_handler(uart->vapi_id, uart_vapi_read, dat);
|
vapi_install_handler(uart->vapi_id, uart_vapi_read, dat);
|
} else if (uart->channel_str && uart->channel_str[0]) { /* Try to create stream. */
|
} else if (uart->channel_str && uart->channel_str[0]) { /* Try to create stream. */
|
if(uart->channel)
|
if(uart->channel)
|
channel_close(uart->channel);
|
channel_close(uart->channel);
|
else
|
else
|
uart->channel = channel_init(uart->channel_str);
|
uart->channel = channel_init(uart->channel_str);
|
if(channel_open(uart->channel) < 0) {
|
if(channel_open(uart->channel) < 0) {
|
WARN ("WARNING: UART has problems with channel \"%s\".\n", uart->channel_str);
|
WARN ("WARNING: UART has problems with channel \"%s\".\n", uart->channel_str);
|
} else if (config.sim.verbose)
|
} else if (config.sim.verbose)
|
PRINTF("UART at 0x%"PRIxADDR" uses ", uart->baseaddr);
|
PRINTF("UART at 0x%"PRIxADDR" uses ", uart->baseaddr);
|
} else {
|
} else {
|
WARN ("WARNING: UART at %"PRIxADDR" has no vapi nor channel specified\n", uart->baseaddr);
|
WARN ("WARNING: UART at %"PRIxADDR" has no vapi nor channel specified\n", uart->baseaddr);
|
}
|
}
|
|
|
if (uart->uart16550)
|
if (uart->uart16550)
|
uart->fifo_len = 16;
|
uart->fifo_len = 16;
|
else
|
else
|
uart->fifo_len = 1;
|
uart->fifo_len = 1;
|
|
|
uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
|
uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
|
uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
|
uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
|
|
|
uart->istat.txser_full = uart->istat.rxser_full = 0;
|
uart->istat.txser_full = uart->istat.rxser_full = 0;
|
uart->istat.txbuf_full = uart->istat.rxbuf_full = 0;
|
uart->istat.txbuf_full = uart->istat.rxbuf_full = 0;
|
|
|
uart->istat.txser_clks = uart->istat.rxser_clks = 0;
|
uart->istat.txser_clks = uart->istat.rxser_clks = 0;
|
|
|
uart->istat.thre_int = 0;
|
uart->istat.thre_int = 0;
|
uart->istat.break_set = 0;
|
uart->istat.break_set = 0;
|
uart->istat.timeout_count = 0;
|
uart->istat.timeout_count = 0;
|
|
|
// For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
|
// For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
|
uart->istat.thre_int = (uart->fifo_len == 16);
|
uart->istat.thre_int = (uart->fifo_len == 16);
|
|
|
uart->char_clks = 0;
|
uart->char_clks = 0;
|
uart->slowdown = UART_FGETC_SLOWDOWN;
|
uart->slowdown = UART_FGETC_SLOWDOWN;
|
|
|
uart->iregs.txser = 0;
|
uart->iregs.txser = 0;
|
uart->iregs.rxser = 0;
|
uart->iregs.rxser = 0;
|
uart->iregs.loopback = 0;
|
uart->iregs.loopback = 0;
|
|
|
memset(uart->regs.txbuf, 0, sizeof(uart->regs.txbuf));
|
memset(uart->regs.txbuf, 0, sizeof(uart->regs.txbuf));
|
memset(uart->regs.rxbuf, 0, sizeof(uart->regs.rxbuf));
|
memset(uart->regs.rxbuf, 0, sizeof(uart->regs.rxbuf));
|
|
|
uart->regs.dll = 0;
|
uart->regs.dll = 0;
|
uart->regs.dlh = 0;
|
uart->regs.dlh = 0;
|
uart->regs.ier = 0;
|
uart->regs.ier = 0;
|
uart->regs.iir = 0;
|
uart->regs.iir = 0;
|
uart->regs.fcr = 0;
|
uart->regs.fcr = 0;
|
uart->regs.lcr = UART_LCR_RESET;
|
uart->regs.lcr = UART_LCR_RESET;
|
uart->regs.mcr = 0;
|
uart->regs.mcr = 0;
|
uart->regs.lsr = 0;
|
uart->regs.lsr = 0;
|
uart->regs.msr = 0;
|
uart->regs.msr = 0;
|
uart->regs.scr = 0;
|
uart->regs.scr = 0;
|
|
|
uart->vapi.cur_break = uart->vapi.cur_break_cnt = uart->vapi.next_break = 0;
|
uart->vapi.cur_break = uart->vapi.cur_break_cnt = uart->vapi.next_break = 0;
|
uart->vapi.next_break_cnt = -1;
|
uart->vapi.next_break_cnt = -1;
|
uart->vapi.break_sent = 0;
|
uart->vapi.break_sent = 0;
|
uart->vapi.skew = 0;
|
uart->vapi.skew = 0;
|
uart->vapi.lcr = 0;
|
uart->vapi.lcr = 0;
|
uart->vapi.dll = 0;
|
uart->vapi.dll = 0;
|
uart->vapi.char_clks = 0;
|
uart->vapi.char_clks = 0;
|
|
|
uart->vapi_buf_head_ptr = 0;
|
uart->vapi_buf_head_ptr = 0;
|
uart->vapi_buf_tail_ptr = 0;
|
uart->vapi_buf_tail_ptr = 0;
|
memset(uart->vapi_buf, 0, sizeof(uart->vapi_buf));
|
memset(uart->vapi_buf, 0, sizeof(uart->vapi_buf));
|
|
|
SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
|
SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
|
}
|
}
|
|
|
/* Print register values on stdout. */
|
/* Print register values on stdout. */
|
void uart_status(void *dat)
|
void uart_status(void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
int i;
|
int i;
|
|
|
PRINTF("\nUART visible registers at 0x%"PRIxADDR":\n", uart->baseaddr);
|
PRINTF("\nUART visible registers at 0x%"PRIxADDR":\n", uart->baseaddr);
|
PRINTF("RXBUF: ");
|
PRINTF("RXBUF: ");
|
for (i = uart->istat.rxbuf_head; i != uart->istat.rxbuf_tail; i = (i + 1) % uart->fifo_len)
|
for (i = uart->istat.rxbuf_head; i != uart->istat.rxbuf_tail; i = (i + 1) % uart->fifo_len)
|
PRINTF (" %.2x", uart->regs.rxbuf[i]);
|
PRINTF (" %.2x", uart->regs.rxbuf[i]);
|
PRINTF("TXBUF: ");
|
PRINTF("TXBUF: ");
|
for (i = uart->istat.txbuf_head; i != uart->istat.txbuf_tail; i = (i + 1) % uart->fifo_len)
|
for (i = uart->istat.txbuf_head; i != uart->istat.txbuf_tail; i = (i + 1) % uart->fifo_len)
|
PRINTF (" %.2x", uart->regs.txbuf[i]);
|
PRINTF (" %.2x", uart->regs.txbuf[i]);
|
PRINTF("\n");
|
PRINTF("\n");
|
PRINTF("DLL : %.2x DLH : %.2x\n", uart->regs.dll, uart->regs.dlh);
|
PRINTF("DLL : %.2x DLH : %.2x\n", uart->regs.dll, uart->regs.dlh);
|
PRINTF("IER : %.2x IIR : %.2x\n", uart->regs.ier, uart->regs.iir);
|
PRINTF("IER : %.2x IIR : %.2x\n", uart->regs.ier, uart->regs.iir);
|
PRINTF("LCR : %.2x MCR : %.2x\n", uart->regs.lcr, uart->regs.mcr);
|
PRINTF("LCR : %.2x MCR : %.2x\n", uart->regs.lcr, uart->regs.mcr);
|
PRINTF("LSR : %.2x MSR : %.2x\n", uart->regs.lsr, uart->regs.msr);
|
PRINTF("LSR : %.2x MSR : %.2x\n", uart->regs.lsr, uart->regs.msr);
|
PRINTF("SCR : %.2x\n", uart->regs.scr);
|
PRINTF("SCR : %.2x\n", uart->regs.scr);
|
|
|
PRINTF("\nInternal registers (sim debug):\n");
|
PRINTF("\nInternal registers (sim debug):\n");
|
PRINTF("RXSER: %.2lx TXSER: %.2lx\n", uart->iregs.rxser, uart->iregs.txser);
|
PRINTF("RXSER: %.2lx TXSER: %.2lx\n", uart->iregs.rxser, uart->iregs.txser);
|
|
|
PRINTF("\nInternal status (sim debug):\n");
|
PRINTF("\nInternal status (sim debug):\n");
|
PRINTF("char_clks: %ld\n", uart->char_clks);
|
PRINTF("char_clks: %ld\n", uart->char_clks);
|
PRINTF("rxser_clks: %ld txser_clks: %ld\n", uart->istat.rxser_clks,
|
PRINTF("rxser_clks: %ld txser_clks: %ld\n", uart->istat.rxser_clks,
|
uart->istat.txser_clks);
|
uart->istat.txser_clks);
|
PRINTF("rxser: %d txser: %d\n", uart->istat.rxser_full, uart->istat.txser_full);
|
PRINTF("rxser: %d txser: %d\n", uart->istat.rxser_full, uart->istat.txser_full);
|
PRINTF("rxbuf_full: %d txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
|
PRINTF("rxbuf_full: %d txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
|
PRINTF("Using IRQ%i\n", uart->irq);
|
PRINTF("Using IRQ%i\n", uart->irq);
|
if (uart->vapi_id)
|
if (uart->vapi_id)
|
PRINTF ("Connected to vapi ID=%lx\n\n", uart->vapi_id);
|
PRINTF ("Connected to vapi ID=%lx\n\n", uart->vapi_id);
|
/* TODO: replace by a channel_status
|
/* TODO: replace by a channel_status
|
else
|
else
|
PRINTF("RX fs: %p TX fs: %p\n\n", uart->rxfs, uart->txfs);
|
PRINTF("RX fs: %p TX fs: %p\n\n", uart->rxfs, uart->txfs);
|
*/
|
*/
|
}
|
}
|
|
|
/*---------------------------------------------------[ UART configuration ]---*/
|
/*---------------------------------------------------[ UART configuration ]---*/
|
void uart_baseaddr(union param_val val, void *dat)
|
void uart_baseaddr(union param_val val, void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
uart->baseaddr = val.addr_val;
|
uart->baseaddr = val.addr_val;
|
}
|
}
|
|
|
void uart_jitter(union param_val val, void *dat)
|
void uart_jitter(union param_val val, void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
uart->jitter = val.int_val;
|
uart->jitter = val.int_val;
|
}
|
}
|
|
|
void uart_irq(union param_val val, void *dat)
|
void uart_irq(union param_val val, void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
uart->irq = val.int_val;
|
uart->irq = val.int_val;
|
}
|
}
|
|
|
void uart_16550(union param_val val, void *dat)
|
void uart_16550(union param_val val, void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
uart->uart16550 = val.int_val;
|
uart->uart16550 = val.int_val;
|
}
|
}
|
|
|
void uart_channel(union param_val val, void *dat)
|
void uart_channel(union param_val val, void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
if(!(uart->channel_str = strdup(val.str_val))) {
|
if(!(uart->channel_str = strdup(val.str_val))) {
|
fprintf(stderr, "Peripheral 16450: Run out of memory\n");
|
fprintf(stderr, "Peripheral 16450: Run out of memory\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
}
|
}
|
|
|
void uart_newway(union param_val val, void *dat)
|
void uart_newway(union param_val val, void *dat)
|
{
|
{
|
CONFIG_ERROR(" txfile and rxfile and now obsolete.\n\tUse 'channel = \"file:rxfile,txfile\"' instead.");
|
CONFIG_ERROR(" txfile and rxfile and now obsolete.\n\tUse 'channel = \"file:rxfile,txfile\"' instead.");
|
exit(1);
|
exit(1);
|
}
|
}
|
|
|
void uart_vapi_id(union param_val val, void *dat)
|
void uart_vapi_id(union param_val val, void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
uart->vapi_id = val.int_val;
|
uart->vapi_id = val.int_val;
|
}
|
}
|
|
|
void *uart_sec_start(void)
|
void *uart_sec_start(void)
|
{
|
{
|
struct dev_16450 *new = malloc(sizeof(struct dev_16450));
|
struct dev_16450 *new = malloc(sizeof(struct dev_16450));
|
|
|
if(!new) {
|
if(!new) {
|
fprintf(stderr, "Peripheral 16450: Run out of memory\n");
|
fprintf(stderr, "Peripheral 16450: Run out of memory\n");
|
exit(-1);
|
exit(-1);
|
}
|
}
|
|
|
new->channel_str = NULL;
|
new->channel_str = NULL;
|
new->channel = NULL;
|
new->channel = NULL;
|
new->vapi_id = 0;
|
new->vapi_id = 0;
|
|
|
return new;
|
return new;
|
}
|
}
|
|
|
void uart_sec_end(void *dat)
|
void uart_sec_end(void *dat)
|
{
|
{
|
struct dev_16450 *uart = dat;
|
struct dev_16450 *uart = dat;
|
|
|
register_memoryarea(uart->baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte,
|
register_memoryarea(uart->baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte,
|
uart_write_byte, dat);
|
uart_write_byte, dat);
|
reg_sim_reset(uart_reset, dat);
|
reg_sim_reset(uart_reset, dat);
|
reg_sim_stat(uart_status, dat);
|
reg_sim_stat(uart_status, dat);
|
}
|
}
|
|
|
void reg_uart_sec(void)
|
void reg_uart_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("uart", uart_sec_start,
|
struct config_section *sec = reg_config_sec("uart", uart_sec_start,
|
uart_sec_end);
|
uart_sec_end);
|
|
|
reg_config_param(sec, "baseaddr", paramt_addr, uart_baseaddr);
|
reg_config_param(sec, "baseaddr", paramt_addr, uart_baseaddr);
|
reg_config_param(sec, "irq", paramt_int, uart_irq);
|
reg_config_param(sec, "irq", paramt_int, uart_irq);
|
reg_config_param(sec, "16550", paramt_int, uart_16550);
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reg_config_param(sec, "16550", paramt_int, uart_16550);
|
reg_config_param(sec, "jitter", paramt_int, uart_jitter);
|
reg_config_param(sec, "jitter", paramt_int, uart_jitter);
|
reg_config_param(sec, "channel", paramt_str, uart_channel);
|
reg_config_param(sec, "channel", paramt_str, uart_channel);
|
reg_config_param(sec, "txfile", paramt_str, uart_newway);
|
reg_config_param(sec, "txfile", paramt_str, uart_newway);
|
reg_config_param(sec, "rxfile", paramt_str, uart_newway);
|
reg_config_param(sec, "rxfile", paramt_str, uart_newway);
|
reg_config_param(sec, "vapi_id", paramt_int, uart_vapi_id);
|
reg_config_param(sec, "vapi_id", paramt_int, uart_vapi_id);
|
}
|
}
|
|
|
