/* default.cfg -- Simulator testbench default configuration script file
|
/* default.cfg -- Simulator testbench default configuration script file
|
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
|
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
|
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
|
|
This program is free software; you can redistribute it and/or modify
|
This program is free software; you can redistribute it and/or modify
|
it under the terms of the GNU General Public License as published by
|
it under the terms of the GNU General Public License as published by
|
the Free Software Foundation; either version 2 of the License, or
|
the Free Software Foundation; either version 2 of the License, or
|
(at your option) any later version.
|
(at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
|
|
section memory
|
section memory
|
memory_table_file = "simmem.cfg"
|
memory_table_file = "acv_uartmem.cfg"
|
/*random_seed = 12345
|
/*random_seed = 12345
|
type = random*/
|
type = random*/
|
pattern = 0x00
|
pattern = 0x00
|
type = unknown /* Fastest */
|
type = unknown /* Fastest */
|
end
|
end
|
|
|
section cpu
|
section cpu
|
ver = 0x1200
|
ver = 0x1200
|
rev = 0x0001
|
rev = 0x0001
|
/* upr = */
|
/* upr = */
|
superscalar = 0
|
superscalar = 0
|
hazards = 0
|
hazards = 0
|
history = 0
|
history = 0
|
dependstats = 0
|
dependstats = 0
|
dependency = 0
|
dependency = 0
|
slp = 0
|
slp = 0
|
btic = 0
|
btic = 0
|
bpb = 0
|
bpb = 0
|
end
|
end
|
|
|
section sim
|
section sim
|
debug = 0
|
debug = 0
|
profile = 0
|
profile = 0
|
prof_fn = "sim.profile"
|
prof_fn = "sim.profile"
|
|
|
verbose = 1
|
verbose = 1
|
/* iprompt = 0 */
|
/* iprompt = 0 */
|
exe_log = 0
|
exe_log = 1
|
exe_log_fn = "executed.log"
|
exe_log_fn = "executed.log"
|
end
|
end
|
|
|
section uart
|
section uart
|
enabled = 1
|
enabled = 1
|
nuarts = 1
|
nuarts = 1
|
|
|
device 0
|
device 0
|
baseaddr = 0x9c000000
|
baseaddr = 0x9c000000
|
jitter = -1 /* async behaviour */
|
jitter = -1 /* async behaviour */
|
16550 = 1
|
16550 = 1
|
irq = 4
|
irq = 4
|
vapi_id = 0x100
|
vapi_id = 0x100
|
enddevice
|
enddevice
|
end
|
end
|
|
|
section VAPI
|
section VAPI
|
enabled = 1
|
enabled = 1
|
log_enabled = 1
|
log_enabled = 1
|
vapi_fn = "vapi.log"
|
vapi_fn = "vapi.log"
|
server_port = 9990
|
server_port = 9100
|
end
|
end
|
|
|
