#include "spr_defs.h"
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#include "spr_defs.h"
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#include "board.h"
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#include "board.h"
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#define IC_ENABLE 0
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#define IC_ENABLE 0
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#define DC_ENABLE 0
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#define DC_ENABLE 0
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#define MC_CSR (0x00)
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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.extern _main
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.extern _main
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.global _ic_enable
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.global _ic_enable
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.global _ic_disable
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.global _ic_disable
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.global _dc_enable
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.global _dc_enable
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.global _dc_disable
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.global _dc_disable
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.global _dc_inv
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.global _dc_inv
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.global _ic_inv_test
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.global _ic_inv_test
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.global _dc_inv_test
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.global _dc_inv_test
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.section .stack
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.section .stack
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.space 0x1000
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.space 0x1000
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_stack:
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_stack:
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.section .reset, "ax"
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.section .reset, "ax"
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.org 0x100
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.org 0x100
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_reset_vector:
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_reset_vector:
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l.addi r2,r0,0x0
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l.addi r2,r0,0x0
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l.addi r3,r0,0x0
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l.addi r3,r0,0x0
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l.addi r4,r0,0x0
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l.addi r4,r0,0x0
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l.addi r5,r0,0x0
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l.addi r5,r0,0x0
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l.addi r6,r0,0x0
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l.addi r6,r0,0x0
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l.addi r7,r0,0x0
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l.addi r7,r0,0x0
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l.addi r8,r0,0x0
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l.addi r8,r0,0x0
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l.addi r9,r0,0x0
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l.addi r9,r0,0x0
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l.addi r10,r0,0x0
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l.addi r10,r0,0x0
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l.addi r11,r0,0x0
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l.addi r11,r0,0x0
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l.addi r12,r0,0x0
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l.addi r12,r0,0x0
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l.addi r13,r0,0x0
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l.addi r13,r0,0x0
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l.addi r14,r0,0x0
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l.addi r14,r0,0x0
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l.addi r15,r0,0x0
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l.addi r15,r0,0x0
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l.addi r16,r0,0x0
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l.addi r16,r0,0x0
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l.addi r17,r0,0x0
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l.addi r17,r0,0x0
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l.addi r18,r0,0x0
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l.addi r18,r0,0x0
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l.addi r19,r0,0x0
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l.addi r19,r0,0x0
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l.addi r20,r0,0x0
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l.addi r20,r0,0x0
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l.addi r21,r0,0x0
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l.addi r21,r0,0x0
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l.addi r22,r0,0x0
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l.addi r22,r0,0x0
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l.addi r23,r0,0x0
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l.addi r23,r0,0x0
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l.addi r24,r0,0x0
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l.addi r24,r0,0x0
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l.addi r25,r0,0x0
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l.addi r25,r0,0x0
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l.addi r26,r0,0x0
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l.addi r26,r0,0x0
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l.addi r27,r0,0x0
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l.addi r27,r0,0x0
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l.addi r28,r0,0x0
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l.addi r28,r0,0x0
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l.addi r29,r0,0x0
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l.addi r29,r0,0x0
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l.addi r30,r0,0x0
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l.addi r30,r0,0x0
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l.addi r31,r0,0x0
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l.addi r31,r0,0x0
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l.movhi r3,hi(start)
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l.movhi r3,hi(start)
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l.ori r3,r3,lo(start)
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l.ori r3,r3,lo(start)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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start:
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start:
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l.jal _init_mc
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l.jal _init_mc
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l.nop
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l.nop
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l.movhi r1,hi(_stack)
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l.movhi r1,hi(_stack)
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l.ori r1,r1,lo(_stack)
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l.ori r1,r1,lo(_stack)
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/* Copy data section */
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/* Copy data section */
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l.movhi r3,hi(_src_beg)
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l.movhi r3,hi(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.movhi r4,hi(_dst_beg)
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l.movhi r4,hi(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.movhi r5,hi(_dst_end)
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l.movhi r5,hi(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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l.sub r5,r5,r4
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l.sub r5,r5,r4
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l.sfeqi r5,0
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l.sfeqi r5,0
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l.bf 2f
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l.bf 2f
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l.nop
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l.nop
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1: l.lwz r6,0(r3)
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1: l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.sfgtsi r5,0
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l.bf 1b
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l.bf 1b
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l.nop
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l.nop
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2:
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2:
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l.movhi r2,hi(_main)
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l.movhi r2,hi(_main)
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l.ori r2,r2,lo(_main)
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l.ori r2,r2,lo(_main)
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l.jr r2
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l.jr r2
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l.nop
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l.nop
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_init_mc:
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_init_mc:
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l.movhi r3,hi(MC_BASE_ADDR)
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.addi r4,r3,MC_CSC(0)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0025
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(0)
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_BA_MASK
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSR
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(1)
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSC(1)
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0411
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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.section .text
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.section .text
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_ic_enable:
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_ic_enable:
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/* Disable IC */
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/* Disable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_ICE
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l.xori r11,r11,SPR_SR_ICE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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/* Invalidate IC */
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/* Invalidate IC */
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l.addi r13,r0,0
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l.addi r13,r0,0
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l.addi r11,r0,8192
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l.addi r11,r0,8192
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1:
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1:
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l.mtspr r0,r13,SPR_ICBIR
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l.mtspr r0,r13,SPR_ICBIR
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l.sfne r13,r11
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l.sfne r13,r11
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l.bf 1b
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l.bf 1b
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l.addi r13,r13,16
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l.addi r13,r13,16
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/* Enable IC */
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/* Enable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.ori r13,r13,SPR_SR_ICE
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l.ori r13,r13,SPR_SR_ICE
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l.mtspr r0,r13,SPR_SR
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l.mtspr r0,r13,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_ic_disable:
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_ic_disable:
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/* Disable IC */
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/* Disable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_ICE
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l.xori r11,r11,SPR_SR_ICE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_enable:
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_dc_enable:
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/* Disable DC */
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/* Disable DC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_DCE
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l.xori r11,r11,SPR_SR_DCE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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/* Flush DC */
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/* Flush DC */
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l.addi r13,r0,0
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l.addi r13,r0,0
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l.addi r11,r0,8192
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l.addi r11,r0,8192
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1:
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1:
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l.mtspr r0,r13,SPR_DCBIR
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l.mtspr r0,r13,SPR_DCBIR
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l.sfne r13,r11
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l.sfne r13,r11
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l.bf 1b
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l.bf 1b
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l.addi r13,r13,16
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l.addi r13,r13,16
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/* Enable DC */
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/* Enable DC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.ori r13,r13,SPR_SR_DCE
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l.ori r13,r13,SPR_SR_DCE
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l.mtspr r0,r13,SPR_SR
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l.mtspr r0,r13,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_disable:
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_dc_disable:
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/* Disable DC */
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/* Disable DC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_DCE
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l.xori r11,r11,SPR_SR_DCE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_inv:
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_dc_inv:
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l.mfspr r4,r0,SPR_SR
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l.mfspr r4,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r4,r5
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l.and r5,r4,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r3,SPR_DCBIR
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l.mtspr r0,r3,SPR_DCBIR
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l.mtspr r0,r4,SPR_SR
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l.mtspr r0,r4,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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.align 0x10
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.align 0x10
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_ic_inv_test:
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_ic_inv_test:
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l.movhi r7,hi(_ic_test_1)
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l.movhi r7,hi(_ic_test_1)
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l.ori r7,r7,lo(_ic_test_1)
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l.ori r7,r7,lo(_ic_test_1)
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l.addi r3,r0,0
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l.addi r3,r0,0
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l.addi r4,r0,0
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l.addi r4,r0,0
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l.addi r5,r0,0
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l.addi r5,r0,0
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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_ic_test_1:
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_ic_test_1:
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3: l.addi r3,r3,1
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3: l.addi r3,r3,1
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l.sfeqi r4,0x01
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l.sfeqi r4,0x01
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l.bnf 1f
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l.bnf 1f
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l.nop
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l.nop
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l.mfspr r8,r0,SPR_SR
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l.mfspr r8,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_ICE
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l.xori r11,r11,SPR_SR_ICE
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l.and r11,r8,r11
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l.and r11,r8,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r7,SPR_ICBIR
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l.mtspr r0,r7,SPR_ICBIR
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l.mtspr r0,r8,SPR_SR
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l.mtspr r0,r8,SPR_SR
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l.bf 2f
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l.bf 2f
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l.nop
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l.nop
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1: l.lwz r6,0(r7)
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1: l.lwz r6,0(r7)
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l.addi r6,r6,1
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l.addi r6,r6,1
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l.sw 0(r7),r6
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l.sw 0(r7),r6
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2: l.addi r5,r5,1
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2: l.addi r5,r5,1
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l.sfeqi r5,10
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l.sfeqi r5,10
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l.bnf 3b
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l.bnf 3b
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l.xori r4,r4,0x01
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l.xori r4,r4,0x01
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l.addi r11,r3,0
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l.addi r11,r3,0
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_inv_test:
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_dc_inv_test:
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l.movhi r4,hi(0x08040201)
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l.movhi r4,hi(0x08040201)
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l.ori r4,r4,lo(0x08040201)
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l.ori r4,r4,lo(0x08040201)
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l.sw 0x00(r3),r4
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l.sw 0x00(r3),r4
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l.slli r4,r4,1
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l.slli r4,r4,1
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l.sw 0x14(r3),r4
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l.sw 0x14(r3),r4
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l.slli r4,r4,1
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l.slli r4,r4,1
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l.sw 0x28(r3),r4
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l.sw 0x28(r3),r4
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l.addi r8,r9,0
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l.addi r8,r9,0
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l.jal _dc_enable
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l.jal _dc_enable
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l.nop
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l.nop
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l.addi r9,r8,0
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l.addi r9,r8,0
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l.lbz r4,0x03(r3)
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l.lbz r4,0x03(r3)
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l.lhz r5,0x16(r3)
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l.lhz r5,0x16(r3)
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l.add r4,r4,r5
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l.add r4,r4,r5
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l.lwz r5,0x28(r3)
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l.lwz r5,0x28(r3)
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l.add r4,r4,r5
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l.add r4,r4,r5
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l.mfspr r6,r0,SPR_SR
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l.mfspr r6,r0,SPR_SR
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l.addi r5,r0,-1
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l.addi r5,r0,-1
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l.xori r5,r5,SPR_SR_DCE
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l.xori r5,r5,SPR_SR_DCE
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l.and r5,r6,r5
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l.and r5,r6,r5
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l.mtspr r0,r5,SPR_SR
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l.mtspr r0,r5,SPR_SR
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l.addi r7,r3,0x10
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l.addi r7,r3,0x10
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l.mtspr r0,r7,SPR_DCBIR
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l.mtspr r0,r7,SPR_DCBIR
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l.lwz r5,0(r3)
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l.lwz r5,0(r3)
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l.slli r5,r5,3
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l.slli r5,r5,3
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l.sw 0x00(r3),r5
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l.sw 0x00(r3),r5
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l.slli r5,r5,1
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l.slli r5,r5,1
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l.sw 0x14(r3),r5
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l.sw 0x14(r3),r5
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l.slli r5,r5,1
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l.slli r5,r5,1
|
l.sw 0x28(r3),r5
|
l.sw 0x28(r3),r5
|
|
|
l.mtspr r0,r6,SPR_SR
|
l.mtspr r0,r6,SPR_SR
|
|
|
l.lbz r5,0x03(r3)
|
l.lbz r5,0x03(r3)
|
l.add r4,r4,r5
|
l.add r4,r4,r5
|
l.lhz r5,0x16(r3)
|
l.lhz r5,0x16(r3)
|
l.add r4,r4,r5
|
l.add r4,r4,r5
|
l.lwz r5,0x28(r3)
|
l.lwz r5,0x28(r3)
|
l.add r4,r4,r5
|
l.add r4,r4,r5
|
|
|
l.addi r5,r0,-1
|
l.addi r5,r0,-1
|
l.xori r5,r5,SPR_SR_DCE
|
l.xori r5,r5,SPR_SR_DCE
|
l.and r5,r6,r5
|
l.and r5,r6,r5
|
l.mtspr r0,r5,SPR_SR
|
l.mtspr r0,r5,SPR_SR
|
|
|
l.addi r11,r4,0x0
|
l.addi r11,r4,0x0
|
1:
|
1:
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
