/* default.cfg -- Simulator testbench default configuration script file
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/* default.cfg -- Simulator testbench default configuration script file
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Copyright (C) 2001, Marko Mlinar, markom@opencores.org
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Copyright (C) 2001, Marko Mlinar, markom@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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section memory
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section memory
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/*random_seed = 12345
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/*random_seed = 12345
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type = random*/
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type = random*/
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pattern = 0x00
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pattern = 0x00
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type = unknown /* Fastest */
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type = unknown /* Fastest */
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nmemories = 2
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nmemories = 2
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device 0
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device 0
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name = "RAM"
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name = "RAM"
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ce = 0
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ce = 0
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baseaddr = 0x00000000
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baseaddr = 0x00000000
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size = 0x00200000
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size = 0x00200000
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delayr = 10
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delayr = 10
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delayw = -1
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delayw = -1
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enddevice
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enddevice
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device 1
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device 1
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name = "FLASH"
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name = "FLASH"
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ce = 1
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ce = 1
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baseaddr = 0x40000000
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baseaddr = 0x40000000
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size = 0x00200000
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size = 0x00200000
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delayr = 2
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delayr = 2
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delayw = 4
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delayw = 4
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enddevice
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enddevice
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end
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end
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section cpu
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section cpu
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ver = 0x1200
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ver = 0x1200
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rev = 0x0001
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rev = 0x0001
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/* upr = */
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/* upr = */
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superscalar = 0
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superscalar = 0
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hazards = 0
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hazards = 0
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dependstats = 0
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dependstats = 0
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end
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section bpb
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enabled = 0
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btic = 0
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btic = 0
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bpb = 0
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end
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end
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section debug
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section debug
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/*enabled = 0
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/*enabled = 0
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gdb_enabled = 0*/
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gdb_enabled = 0*/
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server_port = 9999
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server_port = 9999
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end
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end
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section sim
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section sim
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debug = 0
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debug = 0
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profile = 0
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profile = 0
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prof_fn = "sim.profile"
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prof_fn = "sim.profile"
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/* iprompt = 0 */
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/* iprompt = 0 */
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exe_log = 0
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exe_log = 0
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exe_log_fn = "executed.log"
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exe_log_fn = "executed.log"
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end
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end
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section mc
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section mc
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enabled = 0
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enabled = 0
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baseaddr = 0xa0000000
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baseaddr = 0xa0000000
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POC = 0x00000008 /* Power on configuration register */
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POC = 0x00000008 /* Power on configuration register */
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end
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end
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section uart
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section uart
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enabled = 0
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enabled = 0
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nuarts = 1
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nuarts = 1
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device 0
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device 0
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baseaddr = 0x80000000
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baseaddr = 0x80000000
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rxfile = "/tmp/uart0.rx"
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rxfile = "/tmp/uart0.rx"
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txfile = "/tmp/uart0.tx"
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txfile = "/tmp/uart0.tx"
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jitter = -1 /* async behaviour */
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jitter = -1 /* async behaviour */
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enddevice
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enddevice
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end
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end
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section dma
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section dma
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enabled = 0
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enabled = 0
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ndmas = 1
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ndmas = 1
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device 0
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device 0
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baseaddr = 0x90000000
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baseaddr = 0x90000000
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irq = 4
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irq = 4
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enddevice
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enddevice
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end
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end
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section VAPI
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section VAPI
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enabled = 0
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enabled = 0
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server_port = 9998
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server_port = 9998
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end
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end
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section ethernet
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section ethernet
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enabled = 0
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enabled = 0
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end
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end
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section tick
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section tick
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enabled = 1
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enabled = 1
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irq = 3
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irq = 3
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end
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end
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