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/* sim.cfg -- Simulator configuration script file
/* sim.cfg -- Simulator configuration script file
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
This file includes a lot of help about configurations and default one
This file includes a lot of help about configurations and default one
This file is part of OpenRISC 1000 Architectural Simulator.
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
(at your option) any later version.
This program is distributed in the hope that it will be useful,
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* INTRODUCTION
/* INTRODUCTION
   The or1ksim have various parameters, which can be set in configuration
   The or1ksim have various parameters, which can be set in configuration
   files.  Multiple configurations may be used and switched between at
   files.  Multiple configurations may be used and switched between at
   or1ksim startup.
   or1ksim startup.
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
   all parameters are not defined, default configuration is used.
   all parameters are not defined, default configuration is used.
   Users should not rely on default configuration, but rather redefine all
   Users should not rely on default configuration, but rather redefine all
   critical settings, since default configuration may differ in newer
   critical settings, since default configuration may differ in newer
   versions of the or1ksim.
   versions of the or1ksim.
   If multiple configurations are used, user can switch between them by
   If multiple configurations are used, user can switch between them by
   supplying -f  option when starting simulator.
   supplying -f  option when starting simulator.
   This file may contain (standard C) only comments - no // support.
   This file may contain (standard C) only comments - no // support.
   Like normal configuration file, this file is divided in sections,
   Like normal configuration file, this file is divided in sections,
   where each section is described in detail also.
   where each section is described in detail also.
   Some section also have subsections. One example of such subsection is
   Some section also have subsections. One example of such subsection is
   block:
   block:
   device 
   device 
     instance specific parameters...
     instance specific parameters...
   enddevice
   enddevice
   which creates a device instance.
   which creates a device instance.
*/
*/
/* MEMORY SECTION
/* MEMORY SECTION
   This section specifies how is initial memory generated and which blocks
   This section specifies how is initial memory generated and which blocks
   it consist of.
   it consist of.
   type = random/unknown/pattern
   type = random/unknown/pattern
      specifies the initial memory values. 'random' parameter generate
      specifies the initial memory values. 'random' parameter generate
      random memory using seed 'random_seed' parameter. 'pattern' parameter
      random memory using seed 'random_seed' parameter. 'pattern' parameter
      fills memory with 'pattern' parameter and 'unknown' does not specify
      fills memory with 'pattern' parameter and 'unknown' does not specify
      how memory should be generated - the fastest option.
      how memory should be generated - the fastest option.
   random_seed = 
   random_seed = 
      random seed for randomizer, used if type = random
      random seed for randomizer, used if type = random
   pattern = 
   pattern = 
      pattern to fill memory, used if type = pattern
      pattern to fill memory, used if type = pattern
   nmemories = 
   nmemories = 
      number of memory instances connected
      number of memory instances connected
   instance specific:
   instance specific:
     baseaddr = 
     baseaddr = 
        memory start address
        memory start address
     size = 
     size = 
        memory size
        memory size
     name = ""
     name = ""
        memory block name
        memory block name
     ce = 
     ce = 
        chip enable index of the memory instance
        chip enable index of the memory instance
     delayr = 
     delayr = 
        cycles, required for read access, -1 if instance does not support reading
        cycles, required for read access, -1 if instance does not support reading
     delayw = 
     delayw = 
        cycles, required for write access, -1 if instance does not support writing
        cycles, required for write access, -1 if instance does not support writing
     16550 = 0/1
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
        0, if this device is uart 16450 and 1, if it is 16550
     log = ""
     log = ""
        filename, where to log memory accesses to, no log, if log command is not specified
        filename, where to log memory accesses to, no log, if log command is not specified
*/
*/
section memory
section memory
  /*random_seed = 12345
  /*random_seed = 12345
  type = random*/
  type = random*/
  pattern = 0x00
  pattern = 0x00
  type = unknown /* Fastest */
  type = unknown /* Fastest */
  nmemories = 2
  nmemories = 2
  device 0
  device 0
    name = "RAM"
    name = "RAM"
    ce = 0
    ce = 0
    baseaddr = 0x40000000
    baseaddr = 0x40000000
    size = 0x00200000
    size = 0x00200000
    delayr = 1
    delayr = 1
    delayw = 2
    delayw = 2
  enddevice
  enddevice
  device 1
  device 1
    name = "FLASH"
    name = "FLASH"
    ce = 1
    ce = 1
    baseaddr = 0x00000000
    baseaddr = 0x00000000
    size = 0x00200000
    size = 0x00200000
    delayr = 10
    delayr = 10
    delayw = -1
    delayw = -1
  enddevice
  enddevice
end
end
/* IMMU SECTION
/* IMMU SECTION
    This section configures Instruction Memory Menangement Unit
    This section configures Instruction Memory Menangement Unit
    enabled = 0/1
    enabled = 0/1
       whether IMMU is enabled
       whether IMMU is enabled
       (NOTE: UPR bit is set)
       (NOTE: UPR bit is set)
    nsets = 
    nsets = 
       number of ITLB sets; must be power of two
       number of ITLB sets; must be power of two
    nways = 
    nways = 
       number of ITLB ways
       number of ITLB ways
    pagesize = 
    pagesize = 
       instruction page size; must be power of two
       instruction page size; must be power of two
    entrysize = 
    entrysize = 
       instruction entry size in bytes
       instruction entry size in bytes
    ustates = 
    ustates = 
       number of ITLB usage states (2, 3, 4 etc., max is 4)
       number of ITLB usage states (2, 3, 4 etc., max is 4)
*/
*/
section immu
section immu
  enabled = 1
  enabled = 1
  nsets = 32
  nsets = 32
  nways = 1
  nways = 1
  pagesize = 4096
  pagesize = 8192
end
end
/* DMMU SECTION
/* DMMU SECTION
    This section configures Data Memory Menangement Unit
    This section configures Data Memory Menangement Unit
    enabled = 0/1
    enabled = 0/1
       whether DMMU is enabled
       whether DMMU is enabled
       (NOTE: UPR bit is set)
       (NOTE: UPR bit is set)
    nsets = 
    nsets = 
       number of DTLB sets; must be power of two
       number of DTLB sets; must be power of two
    nways = 
    nways = 
       number of DTLB ways
       number of DTLB ways
    pagesize = 
    pagesize = 
       data page size; must be power of two
       data page size; must be power of two
    entrysize = 
    entrysize = 
       data entry size in bytes
       data entry size in bytes
    ustates = 
    ustates = 
       number of DTLB usage states (2, 3, 4 etc., max is 4)
       number of DTLB usage states (2, 3, 4 etc., max is 4)
*/
*/
section dmmu
section dmmu
  enabled = 1
  enabled = 1
  nsets = 32
  nsets = 32
  nways = 1
  nways = 1
  pagesize = 4096
  pagesize = 8192
end
end
/* IC SECTION
/* IC SECTION
    This section configures Instruction Cache
    This section configures Instruction Cache
    enabled = 0/1
    enabled = 0/1
       whether IC is enabled
       whether IC is enabled
       (NOTE: UPR bit is set)
       (NOTE: UPR bit is set)
    nsets = 
    nsets = 
       number of IC sets; must be power of two
       number of IC sets; must be power of two
    nways = 
    nways = 
       number of IC ways
       number of IC ways
    blocksize = 
    blocksize = 
       IC block size in bytes; must be power of two
       IC block size in bytes; must be power of two
    ustates = 
    ustates = 
       number of IC usage states (2, 3, 4 etc., max is 4)
       number of IC usage states (2, 3, 4 etc., max is 4)
*/
*/
section ic
section ic
  enabled = 0
  enabled = 0
  nsets = 512
  nsets = 512
  nways = 1
  nways = 1
  blocksize = 16
  blocksize = 16
end
end
/* DC SECTION
/* DC SECTION
    This section configures Data Cache
    This section configures Data Cache
    enabled = 0/1
    enabled = 0/1
       whether DC is enabled
       whether DC is enabled
       (NOTE: UPR bit is set)
       (NOTE: UPR bit is set)
    nsets = 
    nsets = 
       number of DC sets; must be power of two
       number of DC sets; must be power of two
    nways = 
    nways = 
       number of DC ways
       number of DC ways
    blocksize = 
    blocksize = 
       DC block size in bytes; must be power of two
       DC block size in bytes; must be power of two
    ustates = 
    ustates = 
       number of DC usage states (2, 3, 4 etc., max is 4)
       number of DC usage states (2, 3, 4 etc., max is 4)
*/
*/
section dc
section dc
  enabled = 0
  enabled = 0
  nsets = 512
  nsets = 512
  nways = 1
  nways = 1
  blocksize = 16
  blocksize = 16
end
end
/* SIM SECTION
/* SIM SECTION
  This section specifies how should sim behave.
  This section specifies how should sim behave.
  verbose = 0/1
  verbose = 0/1
      whether to print out extra messages
      whether to print out extra messages
  debug = 0-9
  debug = 0-9
      = 0 disabled debug messages
      = 0 disabled debug messages
      1-9 level of sim debug information, greater the number more verbose is
      1-9 level of sim debug information, greater the number more verbose is
          the output
          the output
  profile = 0/1
  profile = 0/1
      whether to generate profiling file 'sim.profile'
      whether to generate profiling file 'sim.profile'
  prof_fn = ""
  prof_fn = ""
      filename, where to generate profiling info, used
      filename, where to generate profiling info, used
      only if 'profile' is set
      only if 'profile' is set
  history = 0/1
  history = 0/1
      whether instruction execution flow is tracked for
      whether instruction execution flow is tracked for
      display by simulator hist command. Useful for
      display by simulator hist command. Useful for
      back-trace debugging.
      back-trace debugging.
  iprompt = 0/1
  iprompt = 0/1
      whether we strart in interactive prompt
      whether we strart in interactive prompt
  exe_log = 0/1
  exe_log = 0/1
      whether execution log should be generated
      whether execution log should be generated
  exe_log_fn = ""
  exe_log_fn = ""
      where to put execution log in, used only if 'exe_log'
      where to put execution log in, used only if 'exe_log'
      is set
      is set
  clkcycle = [ps|ns|us|ms]
  clkcycle = [ps|ns|us|ms]
      specifies time measurement for one cycle
      specifies time measurement for one cycle
*/
*/
section sim
section sim
  /* verbose = 1 */
  /* verbose = 1 */
  debug = 0
  debug = 0
  profile = 0
  profile = 0
  prof_fn = "sim.profile"
  prof_fn = "sim.profile"
  history = 1
  history = 1
  /* iprompt = 0 */
  /* iprompt = 0 */
  exe_log = 0
  exe_log = 0
  exe_log_fn = "executed.log"
  exe_log_fn = "executed.log"
end
end
/* SECTION VAPI
/* SECTION VAPI
    This section configures Verification API, used for Advanced
    This section configures Verification API, used for Advanced
    Core Verification.
    Core Verification.
    enabled = 0/1
    enabled = 0/1
        whether to start VAPI server
        whether to start VAPI server
    server_port = 
    server_port = 
        TCP/IP port to start VAPI server on
        TCP/IP port to start VAPI server on
    log_enabled = 0/1
    log_enabled = 0/1
       whether logging of VAPI requests is enabled
       whether logging of VAPI requests is enabled
    vapi_fn = 
    vapi_fn = 
       specifies filename where to log into, if log_enabled is selected
       specifies filename where to log into, if log_enabled is selected
*/
*/
section VAPI
section VAPI
  enabled = 0
  enabled = 0
  server_port = 9998
  server_port = 9998
  log_enabled = 0
  log_enabled = 0
  vapi_log_fn = "vapi.log"
  vapi_log_fn = "vapi.log"
end
end
/* CPU SECTION
/* CPU SECTION
   This section specifies various CPU parameters.
   This section specifies various CPU parameters.
   ver = 
   ver = 
   rev = 
   rev = 
      specifies version and revision of the CPU used
      specifies version and revision of the CPU used
   upr = 
   upr = 
      changes the upr register
      changes the upr register
   superscalar = 0/1
   superscalar = 0/1
      whether CPU is scalar or superscalar
      whether CPU is scalar or superscalar
      (modify cpu/or32/execute.c to tune superscalar model)
      (modify cpu/or32/execute.c to tune superscalar model)
   hazards = 0/1
   hazards = 0/1
      whether data hazards are tracked in superscalar CPU
      whether data hazards are tracked in superscalar CPU
      and displayed by the simulator r command
      and displayed by the simulator r command
   dependstats = 0/1
   dependstats = 0/1
      whether inter-instruction dependencies are calculated
      whether inter-instruction dependencies are calculated
      and displayed by simulator stats command.
      and displayed by simulator stats command.
   slp = 0/1
   slp = 0/1
      calculation of subroutine level parallelism. Displayed
      calculation of subroutine level parallelism. Displayed
      by simulator stats command.
      by simulator stats command.
   btic = 0/1
   btic = 0/1
      enable branch target instruction cache model
      enable branch target instruction cache model
   bpb = 0/1
   bpb = 0/1
      enable branch prediction buffer model
      enable branch prediction buffer model
      parameters for CPU analysis
      parameters for CPU analysis
*/
*/
section cpu
section cpu
  ver = 0x1200
  ver = 0x1200
  rev = 0x0001
  rev = 0x0001
  /* upr = */
  /* upr = */
  superscalar = 0
  superscalar = 0
  hazards = 0
  hazards = 0
  dependstats = 0
  dependstats = 0
  slp = 0
  slp = 0
  btic = 0
  btic = 0
  bpb = 0
  bpb = 0
end
end
/* DEBUG SECTION
/* DEBUG SECTION
   This sections specifies how debug unit should behave.
   This sections specifies how debug unit should behave.
   enabled = 0/1
   enabled = 0/1
      whether debug unit is enabled
      whether debug unit is enabled
   gdb_enabled = 0/1
   gdb_enabled = 0/1
      whether to start gdb server at 'server_port' port
      whether to start gdb server at 'server_port' port
   server_port = 
   server_port = 
      TCP/IP port to start gdb server on, used only if gdb_enabled
      TCP/IP port to start gdb server on, used only if gdb_enabled
      is set
      is set
section debug
section debug
  enabled = 0
  enabled = 0
  gdb_enabled = 0
  gdb_enabled = 0
  server_port = 9999
  server_port = 9999
end
end
/* MC SECTION
/* MC SECTION
   This section configures the memory controller
   This section configures the memory controller
   enabled = 0/1
   enabled = 0/1
      whether memory controller is enabled
      whether memory controller is enabled
   baseaddr = 
   baseaddr = 
      address of first MC register
      address of first MC register
   POC = 
   POC = 
      Power On Configuration register
      Power On Configuration register
*/
*/
section mc
section mc
  enabled = 0
  enabled = 0
  baseaddr = 0xa0000000
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
  POC = 0x00000008                 /* Power on configuration register */
end
end
/* UART SECTION
/* UART SECTION
   This section configures UARTs
   This section configures UARTs
   enabled = 0/1
   enabled = 0/1
      whether uarts are enabled
      whether uarts are enabled
   nuarts = 
   nuarts = 
      make specified number of instances, configure each
      make specified number of instances, configure each
      instance within device - enddevice construct.
      instance within device - enddevice construct.
   instance specific:
   instance specific:
     baseaddr = 
     baseaddr = 
        address of first UART register for this device
        address of first UART register for this device
     rx_file = ""
     rx_file = ""
        filename, where to read data from
        filename, where to read data from
     tx_file = ""
     tx_file = ""
        filename, where to write data to
        filename, where to write data to
     irq = 
     irq = 
        irq number for this device
        irq number for this device
     16550 = 0/1
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
        0, if this device is uart 16450 and 1, if it is 16550
     jitter = 
     jitter = 
        in msecs... time to block, -1 to disable it
        in msecs... time to block, -1 to disable it
     vapi_id = 
     vapi_id = 
        VAPI id of this instance
        VAPI id of this instance
*/
*/
section uart
section uart
  enabled = 0
  enabled = 0
  nuarts = 1
  nuarts = 1
  device 0
  device 0
    baseaddr = 0x80000000
    baseaddr = 0x80000000
    irq = 2
    irq = 2
    rxfile = "/tmp/uart0.rx"
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
    jitter = -1                     /* async behaviour */
  enddevice
  enddevice
end
end
/* DMA SECTION
/* DMA SECTION
   This section configures DMAs
   This section configures DMAs
   enabled = 0/1
   enabled = 0/1
      whether DMAs are enabled
      whether DMAs are enabled
   ndmas = 
   ndmas = 
      make specified number of instances, configure each
      make specified number of instances, configure each
      instance within device - enddevice construct.
      instance within device - enddevice construct.
   instance specific:
   instance specific:
     baseaddr = 
     baseaddr = 
        address of first DMA register for this device
        address of first DMA register for this device
     irq = 
     irq = 
        irq number for this device
        irq number for this device
     vapi_id = 
     vapi_id = 
        VAPI id of this instance
        VAPI id of this instance
*/
*/
section dma
section dma
  enabled = 0
  enabled = 0
  ndmas = 1
  ndmas = 1
  device 0
  device 0
    baseaddr = 0x90000000
    baseaddr = 0x90000000
    irq = 4
    irq = 4
  enddevice
  enddevice
end
end
/* ETHERNET SECTION
/* ETHERNET SECTION
   This section configures ethernets
   This section configures ethernets
   enabled = 0/1
   enabled = 0/1
      whether ethernets are enabled
      whether ethernets are enabled
   nethernets = 
   nethernets = 
      make specified number of instances, configure each
      make specified number of instances, configure each
      instance within device - enddevice construct.
      instance within device - enddevice construct.
   instance specific:
   instance specific:
     baseaddr = 
     baseaddr = 
        address of first ethernet register for this device
        address of first ethernet register for this device
     dma = 
     dma = 
        which controller is this ethernet "connected" to
        which controller is this ethernet "connected" to
     rx_channel = 
     rx_channel = 
        DMA channel used for RX
        DMA channel used for RX
     tx_channel = 
     tx_channel = 
        DMA channel used for TX
        DMA channel used for TX
     rx_file = ""
     rx_file = ""
        filename, where to read data from
        filename, where to read data from
     tx_file = ""
     tx_file = ""
        filename, where to write data to
        filename, where to write data to
     vapi_id = 
     vapi_id = 
        VAPI id of this instance
        VAPI id of this instance
*/
*/
section ethernet
section ethernet
  enabled = 0
  enabled = 0
  nethernets = 1
  nethernets = 1
  device 0
  device 0
    baseaddr = 0x88000000
    baseaddr = 0x88000000
    dma = 0
    dma = 0
    tx_channel = 0
    tx_channel = 0
    rx_channel = 1
    rx_channel = 1
    rxfile = "/tmp/eth0.rx"
    rxfile = "/tmp/eth0.rx"
    txfile = "/tmp/eth0.tx"
    txfile = "/tmp/eth0.tx"
  enddevice
  enddevice
end
end
/* TICK TIMER SECTION
/* TICK TIMER SECTION
    This section configures tick timer
    This section configures tick timer
    enabled = 0/1
    enabled = 0/1
      whether tick timer is enabled
      whether tick timer is enabled
    irq = 
    irq = 
      irq number
      irq number
*/
*/
section tick
section tick
  enabled = 0
  enabled = 0
  irq = 3
  irq = 3
end
end
 
 

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