#include "spr_defs.h"
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#include "spr_defs.h"
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#define PAGE_SIZE 8192
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#define PAGE_SIZE 8192
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#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
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#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_UWE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SRE | \
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SPR_DTLBTR_SWE )
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SPR_DTLBTR_SWE )
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#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
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#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
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SPR_ITLBTR_UXE )
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SPR_ITLBTR_UXE )
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.global _lo_dmmu_en
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.global _lo_dmmu_en
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.global _lo_immu_en
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.global _lo_immu_en
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.global _lo_dtlb_ci_test
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.global _lo_dtlb_ci_test
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.global _lo_itlb_ci_test
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.global _lo_itlb_ci_test
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.global _testjump
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.global _testjump
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.global _ic_enable
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.global _ic_enable
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.global _ic_disable
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.global _ic_disable
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.global _dc_enable
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.global _dc_enable
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.global _dc_disable
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.global _dc_disable
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_lo_dmmu_en:
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_lo_dmmu_en:
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l.mfspr r11,r0,SPR_SR
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l.mfspr r11,r0,SPR_SR
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l.ori r11,r11,SPR_SR_DME
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l.ori r11,r11,SPR_SR_DME
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l.mtspr r0,r11,SPR_ESR_BASE
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l.mtspr r0,r11,SPR_ESR_BASE
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l.mtspr r0,r9,SPR_EPCR_BASE
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l.mtspr r0,r9,SPR_EPCR_BASE
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l.rfe
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l.rfe
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l.nop
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l.nop
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_lo_dmmu_dis:
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_lo_dmmu_dis:
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l.addi r13,r0,-1
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l.addi r13,r0,-1
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l.xori r13,r13,SPR_SR_DME
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l.xori r13,r13,SPR_SR_DME
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l.mfspr r11,r0,SPR_SR
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l.mfspr r11,r0,SPR_SR
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l.and r11,r11,r13
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l.and r11,r11,r13
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_lo_immu_en:
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_lo_immu_en:
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l.mfspr r11,r0,SPR_SR
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l.mfspr r11,r0,SPR_SR
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l.ori r11,r11,SPR_SR_IME
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l.ori r11,r11,SPR_SR_IME
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l.mtspr r0,r11,SPR_ESR_BASE
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l.mtspr r0,r11,SPR_ESR_BASE
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l.mtspr r0,r9,SPR_EPCR_BASE
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l.mtspr r0,r9,SPR_EPCR_BASE
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l.rfe
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l.rfe
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l.nop
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l.nop
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_lo_immu_dis:
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_lo_immu_dis:
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l.addi r13,r0,-1
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l.addi r13,r0,-1
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l.xori r13,r13,SPR_SR_IME
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l.xori r13,r13,SPR_SR_IME
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l.mfspr r11,r0,SPR_SR
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l.mfspr r11,r0,SPR_SR
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l.and r11,r11,r13
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l.and r11,r11,r13
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_testjump:
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_testjump:
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l.movhi r5,0x4800
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l.movhi r5,0x4800
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l.ori r5,r5,0x4800
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l.ori r5,r5,0x4800
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l.sw 0x0(r3),r5
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l.sw 0x0(r3),r5
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l.movhi r5,0x1500
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l.movhi r5,0x1500
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l.ori r5,r5,0x0000
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l.ori r5,r5,0x0000
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l.sw 0x4(r3),r5
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l.sw 0x4(r3),r5
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l.or r5,r0,r9
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l.or r5,r0,r9
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l.jalr r4
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l.jalr r4
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l.nop
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l.nop
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l.or r9,r0,r5
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l.or r9,r0,r5
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_ic_enable:
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_ic_enable:
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/* Disable IC */
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/* Disable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_ICE
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l.xori r11,r11,SPR_SR_ICE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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/* Invalidate IC */
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/* Invalidate IC */
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l.addi r13,r0,0
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l.addi r13,r0,0
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l.addi r11,r0,8192
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l.addi r11,r0,8192
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1:
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1:
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l.mtspr r0,r13,SPR_ICBIR
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l.mtspr r0,r13,SPR_ICBIR
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l.sfne r13,r11
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l.sfne r13,r11
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l.bf 1b
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l.bf 1b
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l.addi r13,r13,16
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l.addi r13,r13,16
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/* Enable IC */
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/* Enable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.ori r13,r13,SPR_SR_ICE
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l.ori r13,r13,SPR_SR_ICE
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l.mtspr r0,r13,SPR_SR
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l.mtspr r0,r13,SPR_SR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_ic_disable:
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_ic_disable:
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/* Disable IC */
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/* Disable IC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_ICE
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l.xori r11,r11,SPR_SR_ICE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_enable:
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_dc_enable:
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/* Disable DC */
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/* Disable DC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_DCE
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l.xori r11,r11,SPR_SR_DCE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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/* Flush DC */
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/* Flush DC */
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l.addi r13,r0,0
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l.addi r13,r0,0
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l.addi r11,r0,8192
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l.addi r11,r0,8192
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1:
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1:
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l.mtspr r0,r13,SPR_DCBIR
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l.mtspr r0,r13,SPR_DCBIR
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l.sfne r13,r11
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l.sfne r13,r11
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l.bf 1b
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l.bf 1b
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l.addi r13,r13,16
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l.addi r13,r13,16
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|
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/* Enable DC */
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/* Enable DC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.ori r13,r13,SPR_SR_DCE
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l.ori r13,r13,SPR_SR_DCE
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l.mtspr r0,r13,SPR_SR
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l.mtspr r0,r13,SPR_SR
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|
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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_dc_disable:
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_dc_disable:
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/* Disable DC */
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/* Disable DC */
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l.mfspr r13,r0,SPR_SR
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l.mfspr r13,r0,SPR_SR
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l.addi r11,r0,-1
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l.addi r11,r0,-1
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l.xori r11,r11,SPR_SR_DCE
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l.xori r11,r11,SPR_SR_DCE
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l.and r11,r13,r11
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l.and r11,r13,r11
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l.mtspr r0,r11,SPR_SR
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l.mtspr r0,r11,SPR_SR
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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/* dtlb_ic_test(unsigned long add, unsigned long set) */
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/* dtlb_ic_test(unsigned long add, unsigned long set) */
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_lo_dtlb_ci_test:
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_lo_dtlb_ci_test:
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l.addi r1,r1,-4
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l.addi r1,r1,-4
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l.sw 0(r1),r9
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l.sw 0(r1),r9
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l.addi r8,r0,0
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l.addi r8,r0,0
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l.movhi r5,hi(0x01234567)
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l.movhi r5,hi(0x01234567)
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l.ori r5,r5,lo(0x01234567)
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l.ori r5,r5,lo(0x01234567)
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l.sw 0(r3),r5
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l.sw 0(r3),r5
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l.movhi r5,hi(0x89abcdef)
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l.movhi r5,hi(0x89abcdef)
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l.ori r5,r5,lo(0x89abcdef)
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l.ori r5,r5,lo(0x89abcdef)
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l.sw (PAGE_SIZE - 4)(r3),r5
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l.sw (PAGE_SIZE - 4)(r3),r5
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l.ori r5,r3,SPR_DTLBMR_V
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l.ori r5,r3,SPR_DTLBMR_V
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l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
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l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
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l.ori r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
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l.ori r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
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l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
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l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
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l.addi r5,r3,PAGE_SIZE
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l.addi r5,r3,PAGE_SIZE
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l.ori r5,r5,SPR_DTLBMR_V
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l.ori r5,r5,SPR_DTLBMR_V
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l.addi r6,r4,1
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l.addi r6,r4,1
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l.mtspr r6,r5,SPR_DTLBMR_BASE(0)
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l.mtspr r6,r5,SPR_DTLBMR_BASE(0)
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l.addi r5,r3,PAGE_SIZE
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l.addi r5,r3,PAGE_SIZE
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l.ori r5,r5,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
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l.ori r5,r5,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
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l.addi r6,r4,1
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l.addi r6,r4,1
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l.mtspr r6,r5,SPR_DTLBTR_BASE(0)
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l.mtspr r6,r5,SPR_DTLBTR_BASE(0)
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l.jal _lo_dmmu_en
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l.jal _lo_dmmu_en
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l.nop
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l.nop
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l.jal _dc_enable
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l.jal _dc_enable
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l.nop
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l.nop
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l.movhi r6,hi(0x01234567)
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l.movhi r6,hi(0x01234567)
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l.ori r6,r6,lo(0x01234567)
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l.ori r6,r6,lo(0x01234567)
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l.lwz r5,0(r3)
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l.lwz r5,0(r3)
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l.sfeq r6,r5
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l.sfeq r6,r5
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l.bnf 11f
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l.bnf 11f
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l.nop
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l.nop
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l.movhi r6,hi(0x89abcdef)
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l.movhi r6,hi(0x89abcdef)
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l.ori r6,r6,lo(0x89abcdef)
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l.ori r6,r6,lo(0x89abcdef)
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l.lwz r5,(PAGE_SIZE - 4)(r3)
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l.lwz r5,(PAGE_SIZE - 4)(r3)
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l.sfeq r6,r5
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l.sfeq r6,r5
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l.bnf 12f
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l.bnf 12f
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l.nop
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l.nop
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l.movhi r5,hi(0x76543210)
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l.movhi r5,hi(0x76543210)
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l.ori r5,r5,lo(0x76543210)
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l.ori r5,r5,lo(0x76543210)
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l.sw 0(r3),r5
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l.sw 0(r3),r5
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l.movhi r5,hi(0xfedcba9)
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l.movhi r5,hi(0xfedcba9)
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l.ori r5,r5,lo(0xfedcba9)
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l.ori r5,r5,lo(0xfedcba9)
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l.sw (PAGE_SIZE - 4)(r3),r5
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l.sw (PAGE_SIZE - 4)(r3),r5
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|
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l.jal _lo_dmmu_dis
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l.jal _lo_dmmu_dis
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l.nop
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l.nop
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l.ori r5,r3,(DTLB_PR_NOLIMIT)
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l.ori r5,r3,(DTLB_PR_NOLIMIT)
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l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
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l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
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l.jal _lo_dmmu_en
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l.jal _lo_dmmu_en
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l.nop
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l.nop
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|
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l.movhi r6,hi(0x76543210)
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l.movhi r6,hi(0x76543210)
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l.ori r6,r6,lo(0x76543210)
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l.ori r6,r6,lo(0x76543210)
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l.lwz r5,0(r3)
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l.lwz r5,0(r3)
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l.sfeq r6,r5
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l.sfeq r6,r5
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l.bnf 13f
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l.bnf 13f
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l.nop
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l.nop
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l.movhi r6,hi(0xfedcba9)
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l.movhi r6,hi(0xfedcba9)
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l.ori r6,r6,lo(0xfedcba9)
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l.ori r6,r6,lo(0xfedcba9)
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l.lwz r5,(PAGE_SIZE - 4)(r3)
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l.lwz r5,(PAGE_SIZE - 4)(r3)
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l.sfeq r6,r5
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l.sfeq r6,r5
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l.bnf 14f
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l.bnf 14f
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l.nop
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l.nop
|
|
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l.jal _lo_dmmu_dis
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l.jal _lo_dmmu_dis
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l.nop
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l.nop
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l.ori r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
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l.ori r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
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l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
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l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
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l.jal _lo_dmmu_en
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l.jal _lo_dmmu_en
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l.nop
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l.nop
|
|
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l.movhi r5,hi(0x00112233)
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l.movhi r5,hi(0x00112233)
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l.ori r5,r5,lo(0x00112233)
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l.ori r5,r5,lo(0x00112233)
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l.sw 0(r3),r5
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l.sw 0(r3),r5
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#if 1
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#if 1
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l.movhi r5,hi(0x44556677)
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l.movhi r5,hi(0x44556677)
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l.ori r5,r5,lo(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.sw 4(r3),r5
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l.sw 4(r3),r5
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l.movhi r5,hi(0x8899aabb)
|
l.movhi r5,hi(0x8899aabb)
|
l.ori r5,r5,lo(0x8899aabb)
|
l.ori r5,r5,lo(0x8899aabb)
|
l.sw 8(r3),r5
|
l.sw 8(r3),r5
|
l.movhi r5,hi(0xccddeeff)
|
l.movhi r5,hi(0xccddeeff)
|
l.ori r5,r5,lo(0xccddeeff)
|
l.ori r5,r5,lo(0xccddeeff)
|
l.sw 12(r3),r5
|
l.sw 12(r3),r5
|
#endif
|
#endif
|
l.movhi r5,hi(0x44556677)
|
l.movhi r5,hi(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.sw (PAGE_SIZE - 4)(r3),r5
|
l.sw (PAGE_SIZE - 4)(r3),r5
|
|
|
l.movhi r6,hi(0x00112233)
|
l.movhi r6,hi(0x00112233)
|
l.ori r6,r6,lo(0x00112233)
|
l.ori r6,r6,lo(0x00112233)
|
l.lwz r5,0(r3)
|
l.lwz r5,0(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 15f
|
l.bnf 15f
|
l.nop
|
l.nop
|
l.movhi r6,hi(0x44556677)
|
l.movhi r6,hi(0x44556677)
|
l.ori r6,r6,lo(0x44556677)
|
l.ori r6,r6,lo(0x44556677)
|
l.lwz r5,(PAGE_SIZE - 4)(r3)
|
l.lwz r5,(PAGE_SIZE - 4)(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 16f
|
l.bnf 16f
|
l.nop
|
l.nop
|
|
|
l.jal _lo_dmmu_dis
|
l.jal _lo_dmmu_dis
|
l.nop
|
l.nop
|
l.ori r5,r3,(DTLB_PR_NOLIMIT)
|
l.ori r5,r3,(DTLB_PR_NOLIMIT)
|
l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
|
l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
|
l.jal _lo_dmmu_en
|
l.jal _lo_dmmu_en
|
l.nop
|
l.nop
|
|
|
l.movhi r6,hi(0x76543210)
|
l.movhi r6,hi(0x76543210)
|
l.ori r6,r6,lo(0x76543210)
|
l.ori r6,r6,lo(0x76543210)
|
l.lwz r5,0(r3)
|
l.lwz r5,0(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 17f
|
l.bnf 17f
|
l.nop
|
l.nop
|
|
|
l.movhi r6,hi(0xfedcba9)
|
l.movhi r6,hi(0xfedcba9)
|
l.ori r6,r6,lo(0xfedcba9)
|
l.ori r6,r6,lo(0xfedcba9)
|
l.lwz r5,(PAGE_SIZE - 4)(r3)
|
l.lwz r5,(PAGE_SIZE - 4)(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 18f
|
l.bnf 18f
|
l.nop
|
l.nop
|
|
|
/* Invalidate cache */
|
/* Invalidate cache */
|
l.jal _dc_disable
|
l.jal _dc_disable
|
l.nop
|
l.nop
|
|
|
l.movhi r5,hi(0x00112233)
|
l.movhi r5,hi(0x00112233)
|
l.ori r5,r5,lo(0x00112233)
|
l.ori r5,r5,lo(0x00112233)
|
l.sw 12(r3),r5
|
l.sw 12(r3),r5
|
l.movhi r5,hi(0x44556677)
|
l.movhi r5,hi(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.sw 8(r3),r5
|
l.sw 8(r3),r5
|
l.movhi r5,hi(0x8899aabb)
|
l.movhi r5,hi(0x8899aabb)
|
l.ori r5,r5,lo(0x8899aabb)
|
l.ori r5,r5,lo(0x8899aabb)
|
l.sw 4(r3),r5
|
l.sw 4(r3),r5
|
l.movhi r5,hi(0xccddeeff)
|
l.movhi r5,hi(0xccddeeff)
|
l.ori r5,r5,lo(0xccddeeff)
|
l.ori r5,r5,lo(0xccddeeff)
|
l.sw 0(r3),r5
|
l.sw 0(r3),r5
|
l.movhi r5,hi(0x44556677)
|
l.movhi r5,hi(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.ori r5,r5,lo(0x44556677)
|
l.sw (PAGE_SIZE - 4)(r3),r5
|
l.sw (PAGE_SIZE - 4)(r3),r5
|
|
|
l.jal _dc_enable
|
l.jal _dc_enable
|
l.nop
|
l.nop
|
|
|
/* I want this part to execute as fast as possible */
|
/* I want this part to execute as fast as possible */
|
l.jal _ic_enable
|
l.jal _ic_enable
|
l.nop
|
l.nop
|
|
|
l.addi r5,r3,PAGE_SIZE
|
l.addi r5,r3,PAGE_SIZE
|
|
|
/* This jump is just to be shure that the following
|
/* This jump is just to be shure that the following
|
instructions will get into IC */
|
instructions will get into IC */
|
l.j 1f
|
l.j 1f
|
l.nop
|
l.nop
|
/* This shuld trigger cahe line refill */
|
/* This shuld trigger cahe line refill */
|
2: l.lwz r6,0(r3)
|
2: l.lwz r6,0(r3)
|
l.j 2f
|
l.j 2f
|
/* This load is from non cached area and may cause some problems
|
/* This load is from non cached area and may cause some problems
|
in previuos refill, which is probably still in progress */
|
in previuos refill, which is probably still in progress */
|
l.lwz r6,0(r5)
|
l.lwz r6,0(r5)
|
1: l.j 2b
|
1: l.j 2b
|
l.nop
|
l.nop
|
2:
|
2:
|
/* Check the line that was previosly refilled */
|
/* Check the line that was previosly refilled */
|
l.movhi r6,hi(0x00112233)
|
l.movhi r6,hi(0x00112233)
|
l.ori r6,r6,lo(0x00112233)
|
l.ori r6,r6,lo(0x00112233)
|
l.lwz r5,12(r3)
|
l.lwz r5,12(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 19f
|
l.bnf 19f
|
l.nop
|
l.nop
|
l.movhi r6,hi(0x44556677)
|
l.movhi r6,hi(0x44556677)
|
l.ori r6,r6,lo(0x44556677)
|
l.ori r6,r6,lo(0x44556677)
|
l.lwz r5,8(r3)
|
l.lwz r5,8(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 19f
|
l.bnf 19f
|
l.nop
|
l.nop
|
l.movhi r6,hi(0x8899aabb)
|
l.movhi r6,hi(0x8899aabb)
|
l.ori r6,r6,lo(0x8899aabb)
|
l.ori r6,r6,lo(0x8899aabb)
|
l.lwz r5,4(r3)
|
l.lwz r5,4(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 19f
|
l.bnf 19f
|
l.nop
|
l.nop
|
l.movhi r6,hi(0xccddeeff)
|
l.movhi r6,hi(0xccddeeff)
|
l.ori r6,r6,lo(0xccddeeff)
|
l.ori r6,r6,lo(0xccddeeff)
|
l.lwz r5,0(r3)
|
l.lwz r5,0(r3)
|
l.sfeq r6,r5
|
l.sfeq r6,r5
|
l.bnf 19f
|
l.bnf 19f
|
l.nop
|
l.nop
|
|
|
l.jal _dc_disable
|
l.jal _dc_disable
|
l.nop
|
l.nop
|
|
|
l.jal _lo_dmmu_dis
|
l.jal _lo_dmmu_dis
|
l.nop
|
l.nop
|
|
|
l.j 10f
|
l.j 10f
|
l.nop
|
l.nop
|
|
|
19: l.addi r8,r8,1
|
19: l.addi r8,r8,1
|
18: l.addi r8,r8,1
|
18: l.addi r8,r8,1
|
17: l.addi r8,r8,1
|
17: l.addi r8,r8,1
|
16: l.addi r8,r8,1
|
16: l.addi r8,r8,1
|
15: l.addi r8,r8,1
|
15: l.addi r8,r8,1
|
14: l.addi r8,r8,1
|
14: l.addi r8,r8,1
|
13: l.addi r8,r8,1
|
13: l.addi r8,r8,1
|
12: l.addi r8,r8,1
|
12: l.addi r8,r8,1
|
11: l.addi r8,r8,1
|
11: l.addi r8,r8,1
|
|
|
10: l.jal _dc_disable
|
10: l.jal _dc_disable
|
l.nop
|
l.nop
|
|
|
l.jal _ic_disable
|
l.jal _ic_disable
|
l.nop
|
l.nop
|
|
|
l.jal _lo_dmmu_dis
|
l.jal _lo_dmmu_dis
|
l.nop
|
l.nop
|
|
|
l.addi r11,r8,0
|
l.addi r11,r8,0
|
l.sw 0(r0),r8
|
l.sw 0(r0),r8
|
l.sw 4(r0),r5
|
l.sw 4(r0),r5
|
|
|
l.lwz r9,0(r1)
|
l.lwz r9,0(r1)
|
l.jr r9
|
l.jr r9
|
l.addi r1,r1,4
|
l.addi r1,r1,4
|
|
|
/* itlb_ic_test(unsigned long add, unsigned long set) */
|
/* itlb_ic_test(unsigned long add, unsigned long set) */
|
_lo_itlb_ci_test:
|
_lo_itlb_ci_test:
|
l.addi r1,r1,-4
|
l.addi r1,r1,-4
|
l.sw 0(r1),r9
|
l.sw 0(r1),r9
|
|
|
l.addi r8,r0,0
|
l.addi r8,r0,0
|
|
|
/* Copy the code to the prepeared location */
|
/* Copy the code to the prepeared location */
|
l.addi r7,r0,88
|
l.addi r7,r0,88
|
l.movhi r5,hi(_ci_test)
|
l.movhi r5,hi(_ci_test)
|
l.ori r5,r5,lo(_ci_test)
|
l.ori r5,r5,lo(_ci_test)
|
l.addi r6,r3,0
|
l.addi r6,r3,0
|
1: l.lwz r11,0(r5)
|
1: l.lwz r11,0(r5)
|
l.sw 0(r6),r11
|
l.sw 0(r6),r11
|
l.addi r5,r5,4
|
l.addi r5,r5,4
|
l.addi r6,r6,4
|
l.addi r6,r6,4
|
l.addi r7,r7,-4
|
l.addi r7,r7,-4
|
l.sfeqi r7,0
|
l.sfeqi r7,0
|
l.bnf 1b
|
l.bnf 1b
|
l.nop
|
l.nop
|
|
|
l.ori r5,r3,SPR_ITLBMR_V
|
l.ori r5,r3,SPR_ITLBMR_V
|
l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
|
l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
|
|
|
l.ori r5,r3,ITLB_PR_NOLIMIT
|
l.ori r5,r3,ITLB_PR_NOLIMIT
|
l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
|
l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
|
|
|
l.jal _lo_immu_en
|
l.jal _lo_immu_en
|
l.nop
|
l.nop
|
l.jal _ic_enable
|
l.jal _ic_enable
|
l.nop
|
l.nop
|
|
|
l.addi r5,r0,0
|
l.addi r5,r0,0
|
l.addi r6,r0,0
|
l.addi r6,r0,0
|
l.jalr r3
|
l.jalr r3
|
l.nop
|
l.nop
|
|
|
l.sfeqi r5,5
|
l.sfeqi r5,5
|
l.bnf 11f
|
l.bnf 11f
|
l.nop
|
l.nop
|
|
|
/* Copy the code to the prepeared location */
|
/* Copy the code to the prepeared location */
|
l.addi r7,r0,20
|
l.addi r7,r0,20
|
l.movhi r5,hi(_ic_refill_test)
|
l.movhi r5,hi(_ic_refill_test)
|
l.ori r5,r5,lo(_ic_refill_test)
|
l.ori r5,r5,lo(_ic_refill_test)
|
l.addi r6,r3,12
|
l.addi r6,r3,12
|
1: l.lwz r11,0(r5)
|
1: l.lwz r11,0(r5)
|
l.sw 0(r6),r11
|
l.sw 0(r6),r11
|
l.addi r5,r5,4
|
l.addi r5,r5,4
|
l.addi r6,r6,4
|
l.addi r6,r6,4
|
l.addi r7,r7,-4
|
l.addi r7,r7,-4
|
l.sfeqi r7,0
|
l.sfeqi r7,0
|
l.bnf 1b
|
l.bnf 1b
|
l.nop
|
l.nop
|
|
|
l.jal _ic_disable
|
l.jal _ic_disable
|
l.nop
|
l.nop
|
l.jal _ic_enable
|
l.jal _ic_enable
|
l.nop
|
l.nop
|
|
|
l.addi r5,r0,0
|
l.addi r5,r0,0
|
l.addi r6,r3,12
|
l.addi r6,r3,12
|
l.jalr r6
|
l.jalr r6
|
l.nop
|
l.nop
|
l.addi r6,r3,16
|
l.addi r6,r3,16
|
l.jalr r6
|
l.jalr r6
|
l.nop
|
l.nop
|
|
|
l.sfeqi r5,4
|
l.sfeqi r5,4
|
l.bnf 12f
|
l.bnf 12f
|
l.nop
|
l.nop
|
|
|
l.j 10f
|
l.j 10f
|
l.nop
|
l.nop
|
|
|
12: l.addi r8,r8,1
|
12: l.addi r8,r8,1
|
11: l.addi r8,r8,1
|
11: l.addi r8,r8,1
|
|
|
10: l.jal _ic_disable
|
10: l.jal _ic_disable
|
l.nop
|
l.nop
|
|
|
l.jal _lo_dmmu_dis
|
l.jal _lo_dmmu_dis
|
l.nop
|
l.nop
|
|
|
l.addi r11,r8,0
|
l.addi r11,r8,0
|
l.sw 0(r0),r11
|
l.sw 0(r0),r11
|
l.sw 4(r0),r5
|
l.sw 4(r0),r5
|
|
|
l.lwz r9,0(r1)
|
l.lwz r9,0(r1)
|
l.jr r9
|
l.jr r9
|
l.addi r1,r1,4
|
l.addi r1,r1,4
|
|
|
_ci_test:
|
_ci_test:
|
3: l.addi r5,r5,1
|
3: l.addi r5,r5,1
|
|
|
l.sfeqi r6,0x01
|
l.sfeqi r6,0x01
|
l.bnf 1f
|
l.bnf 1f
|
l.nop
|
l.nop
|
|
|
l.addi r13,r0,-1
|
l.addi r13,r0,-1
|
l.xori r13,r13,SPR_SR_IME
|
l.xori r13,r13,SPR_SR_IME
|
l.mfspr r11,r0,SPR_SR
|
l.mfspr r11,r0,SPR_SR
|
l.and r13,r11,r13
|
l.and r13,r11,r13
|
l.mtspr r0,r13,SPR_SR
|
l.mtspr r0,r13,SPR_SR
|
|
|
l.ori r7,r3,(ITLB_PR_NOLIMIT | SPR_ITLBTR_CI)
|
l.ori r7,r3,(ITLB_PR_NOLIMIT | SPR_ITLBTR_CI)
|
l.mtspr r4,r7,SPR_ITLBTR_BASE(0)
|
l.mtspr r4,r7,SPR_ITLBTR_BASE(0)
|
|
|
l.mtspr r0,r11,SPR_SR
|
l.mtspr r0,r11,SPR_SR
|
|
|
1: l.lwz r7,0(r3)
|
1: l.lwz r7,0(r3)
|
l.addi r7,r7,1
|
l.addi r7,r7,1
|
l.sw 0(r3),r7
|
l.sw 0(r3),r7
|
|
|
2: l.addi r6,r6,1
|
2: l.addi r6,r6,1
|
l.sfeqi r6,3
|
l.sfeqi r6,3
|
l.bnf 3b
|
l.bnf 3b
|
l.nop
|
l.nop
|
|
|
l.jr r9
|
l.jr r9
|
l.nop
|
l.nop
|
|
|
|
|
_ic_refill_test:
|
_ic_refill_test:
|
l.jr r9
|
l.jr r9
|
l.addi r5,r5,1
|
l.addi r5,r5,1
|
l.addi r5,r5,1
|
l.addi r5,r5,1
|
l.jr r9
|
l.jr r9
|
l.addi r5,r5,1
|
l.addi r5,r5,1
|
|
|
