/* This file is part of test microkernel for OpenRISC 1000. */
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/* This file is part of test microkernel for OpenRISC 1000. */
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/* (C) 2000 Damjan Lampret, lampret@opencores.org */
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/* (C) 2000 Damjan Lampret, lampret@opencores.org */
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "../board.h"
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#include "../board.h"
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#define MC_CSR (0x00)
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#define MC_CSR (0x00)
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#define MC_POC (0x04)
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#define MC_POC (0x04)
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#define MC_BA_MASK (0x08)
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#define MC_BA_MASK (0x08)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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/*
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/*
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* Context is saved to area pointed by pointer in R3. Original
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* Context is saved to area pointed by pointer in R3. Original
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* R3 is at memory location 0 and task's PC is at memory location 4.
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* R3 is at memory location 0 and task's PC is at memory location 4.
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*/
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*/
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#define SAVEREGS \
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#define SAVEREGS \
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l.lwz r3,0(r3); \
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l.lwz r3,0(r3); \
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l.sw 4(r3),r1; \
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l.sw 4(r3),r1; \
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l.sw 8(r3),r2; \
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l.sw 8(r3),r2; \
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l.lwz r2,0(r0); /* saving original r3*/ \
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l.lwz r2,0(r0); /* saving original r3*/ \
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l.sw 12(r3),r2; \
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l.sw 12(r3),r2; \
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l.sw 16(r3),r4; \
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l.sw 16(r3),r4; \
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l.sw 20(r3),r5; \
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l.sw 20(r3),r5; \
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l.sw 24(r3),r6; \
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l.sw 24(r3),r6; \
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l.sw 28(r3),r7; \
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l.sw 28(r3),r7; \
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l.sw 32(r3),r8; \
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l.sw 32(r3),r8; \
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l.sw 36(r3),r9; \
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l.sw 36(r3),r9; \
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l.sw 40(r3),r10; \
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l.sw 40(r3),r10; \
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l.sw 44(r3),r11; \
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l.sw 44(r3),r11; \
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l.sw 48(r3),r12; \
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l.sw 48(r3),r12; \
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l.sw 52(r3),r13; \
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l.sw 52(r3),r13; \
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l.sw 56(r3),r14; \
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l.sw 56(r3),r14; \
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l.sw 60(r3),r15; \
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l.sw 60(r3),r15; \
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l.sw 64(r3),r16; \
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l.sw 64(r3),r16; \
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l.sw 68(r3),r17; \
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l.sw 68(r3),r17; \
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l.sw 72(r3),r18; \
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l.sw 72(r3),r18; \
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l.sw 76(r3),r19; \
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l.sw 76(r3),r19; \
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l.sw 80(r3),r20; \
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l.sw 80(r3),r20; \
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l.sw 84(r3),r21; \
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l.sw 84(r3),r21; \
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l.sw 88(r3),r22; \
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l.sw 88(r3),r22; \
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l.sw 92(r3),r23; \
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l.sw 92(r3),r23; \
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l.sw 96(r3),r24; \
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l.sw 96(r3),r24; \
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l.sw 100(r3),r25; \
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l.sw 100(r3),r25; \
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l.sw 104(r3),r26; \
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l.sw 104(r3),r26; \
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l.sw 108(r3),r27; \
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l.sw 108(r3),r27; \
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l.sw 112(r3),r28; \
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l.sw 112(r3),r28; \
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l.sw 116(r3),r29; \
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l.sw 116(r3),r29; \
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l.sw 120(r3),r30; \
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l.sw 120(r3),r30; \
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l.sw 124(r3),r31; \
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l.sw 124(r3),r31; \
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l.lwz r2,4(r0); /* saving original PC*/ \
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l.lwz r2,4(r0); /* saving original PC*/ \
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l.sw 0(r3),r2; \
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l.sw 0(r3),r2; \
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\
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\
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l.mfspr r2,r0,SPR_ESR_BASE; \
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l.mfspr r2,r0,SPR_ESR_BASE; \
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l.sw 128(r3),r2 /* saving SR */
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l.sw 128(r3),r2 /* saving SR */
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/*
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/*
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* Pointer to context is in R3. All registers are loaded and execution is
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* Pointer to context is in R3. All registers are loaded and execution is
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* transfered to the loaded context's task
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* transfered to the loaded context's task
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*/
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*/
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#define LOADREGS_N_GO \
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#define LOADREGS_N_GO \
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l.lwz r3,0(r3); \
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l.lwz r3,0(r3); \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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\
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\
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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\
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\
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l.lwz r1,4(r3); \
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l.lwz r1,4(r3); \
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l.lwz r2,8(r3); \
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l.lwz r2,8(r3); \
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l.lwz r4,16(r3); \
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l.lwz r4,16(r3); \
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l.lwz r5,20(r3); \
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l.lwz r5,20(r3); \
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l.lwz r6,24(r3); \
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l.lwz r6,24(r3); \
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l.lwz r7,28(r3); \
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l.lwz r7,28(r3); \
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l.lwz r8,32(r3); \
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l.lwz r8,32(r3); \
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l.lwz r9,36(r3); \
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l.lwz r9,36(r3); \
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l.lwz r10,40(r3); \
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l.lwz r10,40(r3); \
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l.lwz r11,44(r3); \
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l.lwz r11,44(r3); \
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l.lwz r12,48(r3); \
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l.lwz r12,48(r3); \
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l.lwz r13,52(r3); \
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l.lwz r13,52(r3); \
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l.lwz r14,56(r3); \
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l.lwz r14,56(r3); \
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l.lwz r15,60(r3); \
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l.lwz r15,60(r3); \
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l.lwz r16,64(r3); \
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l.lwz r16,64(r3); \
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l.lwz r17,68(r3); \
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l.lwz r17,68(r3); \
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l.lwz r18,72(r3); \
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l.lwz r18,72(r3); \
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l.lwz r19,76(r3); \
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l.lwz r19,76(r3); \
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l.lwz r20,80(r3); \
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l.lwz r20,80(r3); \
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l.lwz r21,84(r3); \
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l.lwz r21,84(r3); \
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l.lwz r22,88(r3); \
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l.lwz r22,88(r3); \
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l.lwz r23,92(r3); \
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l.lwz r23,92(r3); \
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l.lwz r24,96(r3); \
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l.lwz r24,96(r3); \
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l.lwz r25,100(r3); \
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l.lwz r25,100(r3); \
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l.lwz r26,104(r3); \
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l.lwz r26,104(r3); \
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l.lwz r27,108(r3); \
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l.lwz r27,108(r3); \
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l.lwz r28,112(r3); \
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l.lwz r28,112(r3); \
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l.lwz r29,116(r3); \
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l.lwz r29,116(r3); \
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l.lwz r30,120(r3); \
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l.lwz r30,120(r3); \
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l.lwz r31,124(r3); \
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l.lwz r31,124(r3); \
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\
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\
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l.lwz r3,12(r3); /* prepare r3*/ \
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l.lwz r3,12(r3); /* prepare r3*/ \
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\
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\
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l.rfe; /* Call task */ \
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l.rfe; /* Call task */ \
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l.nop
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l.nop
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/*
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/*
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* All registers are loaded from save area.
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* All registers are loaded from save area.
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*/
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*/
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#define LOADREGS \
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#define LOADREGS \
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l.lwz r3,0(r3); \
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l.lwz r3,0(r3); \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.lwz r2,0(r3); /* prepare PC*/ \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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l.mtspr r0,r2,SPR_EPCR_BASE; \
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\
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\
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.lwz r2,128(r3); /* prepare SR*/ \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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l.mtspr r0,r2,SPR_ESR_BASE; \
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\
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\
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l.lwz r1,4(r3); \
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l.lwz r1,4(r3); \
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l.lwz r2,8(r3); \
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l.lwz r2,8(r3); \
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l.lwz r4,16(r3); \
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l.lwz r4,16(r3); \
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l.lwz r5,20(r3); \
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l.lwz r5,20(r3); \
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l.lwz r6,24(r3); \
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l.lwz r6,24(r3); \
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l.lwz r7,28(r3); \
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l.lwz r7,28(r3); \
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l.lwz r8,32(r3); \
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l.lwz r8,32(r3); \
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l.lwz r9,36(r3); \
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l.lwz r9,36(r3); \
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l.lwz r10,40(r3); \
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l.lwz r10,40(r3); \
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l.lwz r11,44(r3); \
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l.lwz r11,44(r3); \
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l.lwz r12,48(r3); \
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l.lwz r12,48(r3); \
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l.lwz r13,52(r3); \
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l.lwz r13,52(r3); \
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l.lwz r14,56(r3); \
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l.lwz r14,56(r3); \
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l.lwz r15,60(r3); \
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l.lwz r15,60(r3); \
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l.lwz r16,64(r3); \
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l.lwz r16,64(r3); \
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l.lwz r17,68(r3); \
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l.lwz r17,68(r3); \
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l.lwz r18,72(r3); \
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l.lwz r18,72(r3); \
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l.lwz r19,76(r3); \
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l.lwz r19,76(r3); \
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l.lwz r20,80(r3); \
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l.lwz r20,80(r3); \
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l.lwz r21,84(r3); \
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l.lwz r21,84(r3); \
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l.lwz r22,88(r3); \
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l.lwz r22,88(r3); \
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l.lwz r23,92(r3); \
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l.lwz r23,92(r3); \
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l.lwz r24,96(r3); \
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l.lwz r24,96(r3); \
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l.lwz r25,100(r3); \
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l.lwz r25,100(r3); \
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l.lwz r26,104(r3); \
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l.lwz r26,104(r3); \
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l.lwz r27,108(r3); \
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l.lwz r27,108(r3); \
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l.lwz r28,112(r3); \
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l.lwz r28,112(r3); \
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l.lwz r29,116(r3); \
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l.lwz r29,116(r3); \
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l.lwz r30,120(r3); \
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l.lwz r30,120(r3); \
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l.lwz r31,124(r3); \
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l.lwz r31,124(r3); \
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\
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\
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l.lwz r3,12(r3); /* prepare r3*/
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l.lwz r3,12(r3); /* prepare r3*/
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/*
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/*
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* Set new PC in saved context
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* Set new PC in saved context
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*/
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*/
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#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \
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#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \
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l.lwz AREA,0(AREA); \
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l.lwz AREA,0(AREA); \
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l.movhi TMPREG,hi(SUBROUTINE); \
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l.movhi TMPREG,hi(SUBROUTINE); \
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l.addi TMPREG,r0,lo(SUBROUTINE); \
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l.addi TMPREG,r0,lo(SUBROUTINE); \
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l.sw 0(AREA),TMPREG;
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l.sw 0(AREA),TMPREG;
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/*
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/*
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* Printf via or1ksim hook
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* Printf via or1ksim hook
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*/
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*/
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#if KERNEL_OUTPUT
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#if KERNEL_OUTPUT
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#define PRINTF(REG,STR) \
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#define PRINTF(REG,STR) \
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l.movhi REG,hi(STR); \
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l.movhi REG,hi(STR); \
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l.addi REG,r0,lo(STR); \
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l.addi REG,r0,lo(STR); \
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l.nop NOP_PRINTF
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l.nop NOP_PRINTF
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#else
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#else
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#define PRINTF(REG,STR)
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#define PRINTF(REG,STR)
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#endif
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#endif
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/*
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/*
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* Reset Exception handler
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* Reset Exception handler
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*/
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*/
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.org 0x100
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.org 0x100
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_reset_vector:
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_reset_vector:
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l.movhi r3,hi(MC_BASE_ADDR)
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l.movhi r3,hi(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.ori r3,r3,lo(MC_BASE_ADDR)
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l.addi r4,r3,MC_CSC(0)
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l.addi r4,r3,MC_CSC(0)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.movhi r5,hi(FLASH_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0025
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l.ori r5,r5,0x0025
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(0)
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l.addi r4,r3,MC_TMS(0)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.movhi r5,hi(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.ori r5,r5,lo(FLASH_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_BA_MASK
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l.addi r4,r3,MC_BA_MASK
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l.addi r5,r0,MC_MASK_VAL
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l.addi r5,r0,MC_MASK_VAL
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSR
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l.addi r4,r3,MC_CSR
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l.movhi r5,hi(MC_CSR_VAL)
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l.movhi r5,hi(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.ori r5,r5,lo(MC_CSR_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_TMS(1)
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l.addi r4,r3,MC_TMS(1)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.movhi r5,hi(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.ori r5,r5,lo(SDRAM_TMS_VAL)
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.addi r4,r3,MC_CSC(1)
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l.addi r4,r3,MC_CSC(1)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.movhi r5,hi(SDRAM_BASE_ADDR)
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l.srai r5,r5,6
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l.srai r5,r5,6
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l.ori r5,r5,0x0411
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l.ori r5,r5,0x0411
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l.sw 0(r4),r5
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l.sw 0(r4),r5
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l.jr r9
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l.jr r9
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l.nop
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l.nop
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/* Copy data section */
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/* Copy data section */
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l.movhi r3,hi(_src_beg)
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l.movhi r3,hi(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.ori r3,r3,lo(_src_beg)
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l.addi r4,r0,0x200
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l.addi r4,r0,0x200
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l.movhi r5,hi(_except_end)
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l.movhi r5,hi(_except_end)
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l.ori r5,r5,lo(_except_end)
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l.ori r5,r5,lo(_except_end)
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l.movhi r6,hi(_except_beg)
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l.movhi r6,hi(_except_beg)
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l.ori r6,r6,lo(_except_beg)
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l.ori r6,r6,lo(_except_beg)
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l.sub r5,r6,r5
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l.sub r5,r6,r5
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1:
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1:
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l.lwz r6,0(r3)
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l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.sfgtsi r5,0
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l.bf 1b
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l.bf 1b
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l.nop
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l.nop
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l.movhi r4,hi(_dst_beg)
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l.movhi r4,hi(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.ori r4,r4,lo(_dst_beg)
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l.movhi r5,hi(_dst_end)
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l.movhi r5,hi(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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l.ori r5,r5,lo(_dst_end)
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l.sub r5,r5,r4
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l.sub r5,r5,r4
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l.sfeqi r5,0
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l.sfeqi r5,0
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l.bf 2f
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l.bf 2f
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l.nop
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l.nop
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1:
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1:
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l.lwz r6,0(r3)
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l.lwz r6,0(r3)
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l.sw 0(r4),r6
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l.sw 0(r4),r6
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l.addi r3,r3,4
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l.addi r3,r3,4
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l.addi r4,r4,4
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l.addi r4,r4,4
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l.addi r5,r5,-4
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l.addi r5,r5,-4
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l.sfgtsi r5,0
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l.sfgtsi r5,0
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l.bf 1b
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l.bf 1b
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l.nop
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l.nop
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2:
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2:
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l.movhi r2,hi(_reset)
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l.movhi r2,hi(_reset)
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l.ori r2,r2,lo(_reset)
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l.ori r2,r2,lo(_reset)
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l.jr r2
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l.jr r2
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l.nop
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l.nop
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/*
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/*
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* Switch to a new context pointed by _task_context
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* Switch to a new context pointed by _task_context
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*/
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*/
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.global _dispatch
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.global _dispatch
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.align 4
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.align 4
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_dispatch:
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_dispatch:
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/* load user task GPRs and PC */
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/* load user task GPRs and PC */
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l.movhi r3,hi(_task_context)
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l.movhi r3,hi(_task_context)
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l.addi r3,r0,lo(_task_context)
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l.addi r3,r0,lo(_task_context)
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LOADREGS_N_GO
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LOADREGS_N_GO
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.section .except, "ax"
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.section .except, "ax"
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/*
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/*
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* Bus Error Exception handler
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* Bus Error Exception handler
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*/
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*/
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.org 0x0200
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.org 0x0200
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_buserr:
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_buserr:
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l.nop
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l.nop
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l.sw 0(r0),r3 /* Save r3 */
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l.sw 0(r0),r3 /* Save r3 */
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PRINTF(r3, _buserr_str)
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PRINTF(r3, _buserr_str)
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_hang:
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_hang:
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l.j _hang
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l.j _hang
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l.nop
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l.nop
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_buserr_str:
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_buserr_str:
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.ascii "Bus error exception.\n\000"
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.ascii "Bus error exception.\n\000"
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/*
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/*
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* External Interrupt Exception handler
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* External Interrupt Exception handler
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*/
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*/
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.org 0x800
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.org 0x800
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_extint:
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_extint:
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l.nop
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l.nop
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l.sw 0(r0),r3 /* Save r3 */
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l.sw 0(r0),r3 /* Save r3 */
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PRINTF(r3,_extint_str)
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PRINTF(r3,_extint_str)
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l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
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l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
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l.sw 4(r0),r3 /* and save it */
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l.sw 4(r0),r3 /* and save it */
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/* now save user task context */
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/* now save user task context */
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l.movhi r3,hi(_task_context)
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l.movhi r3,hi(_task_context)
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l.addi r3,r0,lo(_task_context)
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l.addi r3,r0,lo(_task_context)
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SAVEREGS
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SAVEREGS
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/* set kernel context's PC to kernel's scheduler */
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/* set kernel context's PC to kernel's scheduler */
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l.movhi r3,hi(_kernel_context)
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l.movhi r3,hi(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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SET_CONTEXTPC(r3,_int_main,r4)
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SET_CONTEXTPC(r3,_int_main,r4)
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/* load kernel context */
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/* load kernel context */
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l.movhi r3,hi(_kernel_context)
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l.movhi r3,hi(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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LOADREGS
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LOADREGS
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l.movhi r3,hi(_int_main)
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l.movhi r3,hi(_int_main)
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l.addi r3,r0,lo(_int_main)
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l.addi r3,r0,lo(_int_main)
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l.jr r3
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l.jr r3
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l.nop
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l.nop
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_extint_str:
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_extint_str:
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.ascii "External interrupt exception.\n\000"
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.ascii "External interrupt exception.\n\000"
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/*
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/*
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* System Call Exception handler
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* System Call Exception handler
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*/
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*/
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.org 0x0c00
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.org 0x0c00
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_syscall:
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_syscall:
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l.nop
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l.nop
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l.sw 0(r0),r3 /* Save r3 */
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l.sw 0(r0),r3 /* Save r3 */
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PRINTF(r3,_syscall_str)
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PRINTF(r3,_syscall_str)
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l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
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l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */
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l.addi r3,r3,4 /* increment because EPCR instruction was already executed */
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l.addi r3,r3,4 /* increment because EPCR instruction was already executed */
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l.sw 4(r0),r3 /* and save it */
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l.sw 4(r0),r3 /* and save it */
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/* now save user task context */
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/* now save user task context */
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l.movhi r3,hi(_task_context)
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l.movhi r3,hi(_task_context)
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l.addi r3,r0,lo(_task_context)
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l.addi r3,r0,lo(_task_context)
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SAVEREGS
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SAVEREGS
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/* set kernel context's PC to kernel's syscall entry */
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/* set kernel context's PC to kernel's syscall entry */
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l.movhi r3,hi(_kernel_context)
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l.movhi r3,hi(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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SET_CONTEXTPC(r3,_kernel_syscall,r4)
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SET_CONTEXTPC(r3,_kernel_syscall,r4)
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/* load kernel context */
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/* load kernel context */
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l.movhi r3,hi(_kernel_context)
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l.movhi r3,hi(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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l.addi r3,r0,lo(_kernel_context)
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LOADREGS_N_GO
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LOADREGS_N_GO
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_syscall_str:
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_syscall_str:
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.ascii "System call exception.\n\000"
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.ascii "System call exception.\n\000"
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