/*
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/*
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atahost.h -- ATA Host code simulation
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atahost.h -- ATA Host code simulation
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator
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This file is part of OpenRISC 1000 Architectural Simulator
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version
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(at your option) any later version
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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/*
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/*
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* User configuration of the OCIDEC ata core
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* User configuration of the OCIDEC ata core
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*/
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*/
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#ifndef __OR1KSIM_ATAC_H
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#ifndef __OR1KSIM_ATAC_H
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#define __OR1KSIM_ATAC_H
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#define __OR1KSIM_ATAC_H
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/* define core (OCIDEC) type */
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/* define core (OCIDEC) type */
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#define DEV_ID 1
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#define DEV_ID 1
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/* define core version */
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/* define core version */
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#define REV 0
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#define REV 0
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/* define timing reset values */
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/* define timing reset values */
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#define PIO_MODE0_T1 6
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#define PIO_MODE0_T1 6
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#define PIO_MODE0_T2 28
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#define PIO_MODE0_T2 28
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#define PIO_MODE0_T4 2
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#define PIO_MODE0_T4 2
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#define PIO_MODE0_TEOC 23
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#define PIO_MODE0_TEOC 23
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TM 4
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TD 21
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#define DMA_MODE0_TEOC 21
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#define DMA_MODE0_TEOC 21
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#endif
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#endif
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