/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This is functional simulation of OpenRISC 1000 architectural
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/* This is functional simulation of OpenRISC 1000 architectural
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programmable interrupt controller.
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programmable interrupt controller.
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*/
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*/
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "pic.h"
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#include "pic.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sched.h"
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#include "sched.h"
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#include "debug.h"
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#include "debug.h"
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extern int cont_run;
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extern int cont_run;
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DEFAULT_DEBUG_CHANNEL(pic);
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DEFAULT_DEBUG_CHANNEL(pic);
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/* Reset. It initializes PIC registers. */
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/* Reset. It initializes PIC registers. */
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void pic_reset()
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void pic_reset()
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{
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{
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PRINTF("Resetting PIC.\n");
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PRINTF("Resetting PIC.\n");
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mtspr(SPR_PICMR, 0);
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mtspr(SPR_PICMR, 0);
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mtspr(SPR_PICPR, 0);
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mtspr(SPR_PICPR, 0);
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mtspr(SPR_PICSR, 0);
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mtspr(SPR_PICSR, 0);
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}
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}
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/* Handles the reporting of an interrupt if it had to be delayed */
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/* Handles the reporting of an interrupt if it had to be delayed */
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void pic_clock(void *dat)
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void pic_clock(void *dat)
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{
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{
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if(testsprbits (SPR_SR, SPR_SR_IEE))
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if(testsprbits (SPR_SR, SPR_SR_IEE))
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except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
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except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
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else
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else
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SCHED_ADD(pic_clock, NULL, 1);
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SCHED_ADD(pic_clock, NULL, 1);
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}
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}
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/* WARNING: Don't eaven try and call this function *during* a simulated
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/* WARNING: Don't eaven try and call this function *during* a simulated
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* instruction!! (as in during a read_mem or write_mem callback). except_handle
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* instruction!! (as in during a read_mem or write_mem callback). except_handle
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* assumes that this is the case, it breaks otherwise. */
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* assumes that this is the case, it breaks otherwise. */
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/* Asserts interrupt to the PIC. */
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/* Asserts interrupt to the PIC. */
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void report_interrupt(int line)
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void report_interrupt(int line)
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{
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{
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setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
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setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
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setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
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setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
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TRACE("Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
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TRACE("Asserting interrupt %d (%s).\n", line, getsprbit(SPR_PICMR, line) ? "Unmasked" : "Masked");
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if (getsprbit(SPR_PICMR, line) || line < 2) {
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if (getsprbit(SPR_PICMR, line) || line < 2) {
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setsprbit(SPR_PICSR, line, 1);
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setsprbit(SPR_PICSR, line, 1);
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/* Don't do anything if interrupts not currently enabled */
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/* Don't do anything if interrupts not currently enabled */
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if (testsprbits (SPR_SR, SPR_SR_IEE)) {
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if (testsprbits (SPR_SR, SPR_SR_IEE)) {
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except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
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except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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} else
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} else
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/* Interrupts not currently enabled, retry next clock cycle */
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/* Interrupts not currently enabled, retry next clock cycle */
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SCHED_ADD(pic_clock, NULL, 1);
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SCHED_ADD(pic_clock, NULL, 1);
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}
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}
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}
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}
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