/* dumpverilog.c -- Dumps memory region as Verilog representation
|
/* dumpverilog.c -- Dumps memory region as Verilog representation
|
or as hex code
|
or as hex code
|
Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
|
Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
|
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
|
|
This program is free software; you can redistribute it and/or modify
|
This program is free software; you can redistribute it and/or modify
|
it under the terms of the GNU General Public License as published by
|
it under the terms of the GNU General Public License as published by
|
the Free Software Foundation; either version 2 of the License, or
|
the Free Software Foundation; either version 2 of the License, or
|
(at your option) any later version.
|
(at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
|
|
/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */
|
/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */
|
|
|
#include <stdio.h>
|
#include <stdio.h>
|
#include <ctype.h>
|
#include <ctype.h>
|
#include <string.h>
|
#include <string.h>
|
|
|
#include "config.h"
|
#include "config.h"
|
#include "sim-config.h"
|
#include "sim-config.h"
|
|
|
#include "parse.h"
|
#include "parse.h"
|
#include "abstract.h"
|
#include "abstract.h"
|
#include "arch.h"
|
#include "arch.h"
|
#include "trace.h"
|
#include "trace.h"
|
#include "execute.h"
|
#include "execute.h"
|
#include "sprs.h"
|
#include "sprs.h"
|
#include "stats.h"
|
#include "stats.h"
|
#include "except.h"
|
#include "except.h"
|
#include "dumpverilog.h"
|
#include "dumpverilog.h"
|
#include "or32.h"
|
#include "opcode/or32.h"
|
|
|
extern struct mem_entry mem[MEMORY_LEN];
|
extern struct mem_entry mem[MEMORY_LEN];
|
extern char rcsrev[];
|
extern char rcsrev[];
|
|
extern char *disassembled;
|
|
|
void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to)
|
void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to)
|
{
|
{
|
unsigned int i, done = 0;
|
unsigned int i, done = 0;
|
struct label_entry *tmp;
|
struct label_entry *tmp;
|
char dis[DISWIDTH + 100];
|
char dis[DISWIDTH + 100];
|
int breakpoint = 0;
|
int breakpoint = 0;
|
|
|
printf("// This file was generated by or1ksim %s\n", rcsrev);
|
printf("// This file was generated by or1ksim %s\n", rcsrev);
|
printf(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ, (DISWIDTH*8)));
|
printf(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ, (DISWIDTH*8)));
|
|
|
for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++) {
|
for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++)
|
if (mem[i].insn->insn_index >= 0) {
|
{
|
|
int bp;
|
|
unsigned int _insn = evalsim_mem32 (i, &bp);
|
|
int index = insn_decode(_insn);
|
|
if (index >= 0)
|
|
{
|
tmp = mem[i].label;
|
tmp = mem[i].label;
|
for(; tmp; tmp = tmp->next)
|
for(; tmp; tmp = tmp->next)
|
printf("\n//\t%s%s", tmp->name, LABELEND_CHAR);
|
printf("\n//\t%s%s", tmp->name, LABELEND_CHAR);
|
|
|
printf("\n\tmem['h%x] = %d'h%.2x%.2x", i/DWQ, DW, mem[i].data, mem[i+1].data);
|
printf("\n\tmem['h%x] = %d'h%.2x%.2x", i/DWQ, DW, mem[i].data, mem[i+1].data);
|
printf("%.2x%.2x;", mem[i+2].data, mem[i+3].data);
|
printf("%.2x%.2x;", mem[i+2].data, mem[i+3].data);
|
if (mem[i].insn)
|
|
sprintf(dis, "%s %s", insn_name(mem[i].insn->insn_index), mem[i].insn->op1);
|
disassemble_insn (_insn);
|
if (strlen(mem[i].insn->op2))
|
strcpy (dis, disassembled);
|
sprintf(dis, "%s%s%s", dis, OPERAND_DELIM, mem[i].insn->op2);
|
|
if (strlen(mem[i].insn->op3))
|
|
sprintf(dis, "%s%s%s", dis, OPERAND_DELIM, mem[i].insn->op3);
|
|
if (strlen(mem[i].insn->op4))
|
|
sprintf(dis, "%s%s%s", dis, OPERAND_DELIM, mem[i].insn->op4);
|
|
if (strlen(dis) < DISWIDTH)
|
if (strlen(dis) < DISWIDTH)
|
memset(dis + strlen(dis), ' ', DISWIDTH);
|
memset(dis + strlen(dis), ' ', DISWIDTH);
|
dis[DISWIDTH] = '\0';
|
dis[DISWIDTH] = '\0';
|
printf("\n\tdis['h%x] = {\"%s\"};", i/DWQ, dis);
|
printf("\n\tdis['h%x] = {\"%s\"};", i/DWQ, dis);
|
dis[0] = '\0';
|
dis[0] = '\0';
|
i += (insn_len(mem[i].insn->insn_index) - 1);
|
i += insn_len(index) - 1;
|
} else
|
}
|
|
else
|
{
|
{
|
if (i % 64 == 0)
|
if (i % 64 == 0)
|
printf("\n");
|
printf("\n");
|
|
|
printf("\n\tmem['h%x] = 'h%.2x;", i/DWQ, (unsigned char)mem[i].data);
|
printf("\n\tmem['h%x] = 'h%.2x;", i/DWQ, (unsigned char)mem[i].data);
|
}
|
}
|
done = 1;
|
done = 1;
|
}
|
}
|
|
|
if (done) {
|
if (done)
|
|
{
|
printf(OR1K_MEM_VERILOG_FOOTER);
|
printf(OR1K_MEM_VERILOG_FOOTER);
|
return;
|
return;
|
}
|
}
|
|
|
/* this needs to be fixed */
|
/* this needs to be fixed */
|
|
|
for(i = from; i < to; i++) {
|
for(i = from; i < to; i++)
|
|
{
|
if (i % 8 == 0)
|
if (i % 8 == 0)
|
printf("\n%.8x: ", i);
|
printf("\n%.8x: ", i);
|
|
|
/* don't print ascii chars below 0x20. */
|
/* don't print ascii chars below 0x20. */
|
if (evalsim_mem32(i,&breakpoint) < 0x20)
|
if (evalsim_mem32(i,&breakpoint) < 0x20)
|
printf("0x%.2x ", (unsigned char)evalsim_mem32(i,&breakpoint));
|
printf("0x%.2x ", (unsigned char)evalsim_mem32(i,&breakpoint));
|
else
|
else
|
printf("0x%.2x'%c' ", (unsigned char)evalsim_mem32(i,&breakpoint), (unsigned char)evalsim_mem32(i,&breakpoint));
|
printf("0x%.2x'%c' ", (unsigned char)evalsim_mem32(i,&breakpoint), (unsigned char)evalsim_mem32(i,&breakpoint));
|
|
|
}
|
}
|
printf(OR1K_MEM_VERILOG_FOOTER);
|
printf(OR1K_MEM_VERILOG_FOOTER);
|
}
|
}
|
|
|
|
|
void dumphex(unsigned int from, unsigned int to)
|
void dumphex(unsigned int from, unsigned int to)
|
{
|
{
|
unsigned int i, done = 0;
|
unsigned int i, done = 0;
|
int breakpoint = 0;
|
int breakpoint = 0;
|
|
|
for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++) {
|
for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++) {
|
if (mem[i].insn) {
|
unsigned int _insn = evalsim_mem32 (i, &breakpoint);
|
|
int index = insn_decode(_insn);
|
|
if (index >= 0)
|
|
{
|
printf("%.2x%.2x", mem[i].data, mem[i+1].data);
|
printf("%.2x%.2x", mem[i].data, mem[i+1].data);
|
printf("%.2x%.2x\n", mem[i+2].data, mem[i+3].data);
|
printf("%.2x%.2x\n", mem[i+2].data, mem[i+3].data);
|
i += (insn_len(mem[i].insn->insn_index) - 1);
|
i += insn_len(index) - 1;
|
} else
|
|
{
|
|
printf("%.2x\n", (unsigned char)mem[i].data);
|
|
}
|
|
done = 1;
|
|
}
|
|
|
|
if (done) {
|
|
return;
|
|
}
|
}
|
|
else
|
/* this needs to be fixed */
|
printf("%.2x\n", (unsigned char)mem[i].data);
|
|
|
for(i = from; i < to; i++) {
|
|
printf("%.2x", (unsigned char)evalsim_mem32(i,&breakpoint));
|
|
}
|
}
|
}
|
}
|
|
|
