/* dumpverilog.c -- Dumps memory region as Verilog representation
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/* dumpverilog.c -- Dumps memory region as Verilog representation
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or as hex code
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or as hex code
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Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */
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/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */
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#include <stdio.h>
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#include <stdio.h>
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#include <ctype.h>
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#include <ctype.h>
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#include <string.h>
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#include <string.h>
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "parse.h"
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#include "parse.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "labels.h"
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#include "labels.h"
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#include "execute.h"
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#include "execute.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "stats.h"
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#include "stats.h"
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#include "except.h"
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#include "except.h"
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#include "dumpverilog.h"
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#include "dumpverilog.h"
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extern char rcsrev[];
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extern char rcsrev[];
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extern char *disassembled;
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extern char *disassembled;
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void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to)
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void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to)
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{
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{
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unsigned int i, done = 0;
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unsigned int i, done = 0;
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struct label_entry *tmp;
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struct label_entry *tmp;
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char dis[DISWIDTH + 100];
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char dis[DISWIDTH + 100];
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PRINTF("// This file was generated by or1ksim %s\n", rcsrev);
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PRINTF("// This file was generated by or1ksim %s\n", rcsrev);
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PRINTF(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ, (DISWIDTH*8)));
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PRINTF(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ, (DISWIDTH*8)));
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for(i = from; i < to; i++)
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for(i = from; i < to; i++)
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{
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{
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unsigned int _insn = evalsim_mem32 (i);
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unsigned int _insn = evalsim_mem32 (i);
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int index = insn_decode(_insn);
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int index = insn_decode(_insn);
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if (index >= 0)
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if (index >= 0)
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{
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{
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if (verify_memoryarea(i) && (tmp = get_label(i)))
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if (verify_memoryarea(i) && (tmp = get_label(i)))
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if (tmp)
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if (tmp)
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PRINTF("\n//\t%s%s", tmp->name, LABELEND_CHAR);
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PRINTF("\n//\t%s%s", tmp->name, LABELEND_CHAR);
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PRINTF("\n\tmem['h%x] = %d'h%.8"PRIx32";", i/DWQ, DW, evalsim_mem32(i));
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PRINTF("\n\tmem['h%x] = %d'h%.8"PRIx32";", i/DWQ, DW, evalsim_mem32(i));
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disassemble_insn (_insn);
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disassemble_insn (_insn);
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strcpy (dis, disassembled);
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strcpy (dis, disassembled);
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if (strlen(dis) < DISWIDTH)
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if (strlen(dis) < DISWIDTH)
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memset(dis + strlen(dis), ' ', DISWIDTH);
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memset(dis + strlen(dis), ' ', DISWIDTH);
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dis[DISWIDTH] = '\0';
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dis[DISWIDTH] = '\0';
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PRINTF("\n\tdis['h%x] = {\"%s\"};", i/DWQ, dis);
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PRINTF("\n\tdis['h%x] = {\"%s\"};", i/DWQ, dis);
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dis[0] = '\0';
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dis[0] = '\0';
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i += insn_len(index) - 1;
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i += insn_len(index) - 1;
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} else {
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} else {
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if (i % 64 == 0)
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if (i % 64 == 0)
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PRINTF("\n");
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PRINTF("\n");
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PRINTF("\n\tmem['h%x] = 'h%.2x;", i/DWQ, evalsim_mem8(i));
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PRINTF("\n\tmem['h%x] = 'h%.2x;", i/DWQ, evalsim_mem8(i));
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}
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}
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done = 1;
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done = 1;
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}
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}
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if (done)
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if (done)
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{
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{
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PRINTF(OR1K_MEM_VERILOG_FOOTER);
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PRINTF(OR1K_MEM_VERILOG_FOOTER);
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return;
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return;
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}
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}
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/* this needs to be fixed */
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/* this needs to be fixed */
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for(i = from; i < to; i++)
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for(i = from; i < to; i++)
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{
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{
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if (i % 8 == 0)
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if (i % 8 == 0)
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PRINTF("\n%.8x: ", i);
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PRINTF("\n%.8x: ", i);
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/* don't print ascii chars below 0x20. */
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/* don't print ascii chars below 0x20. */
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if (evalsim_mem32(i) < 0x20)
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if (evalsim_mem32(i) < 0x20)
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PRINTF("0x%.2x ", (unsigned char)evalsim_mem32(i));
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PRINTF("0x%.2x ", (unsigned char)evalsim_mem32(i));
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else
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else
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PRINTF("0x%.2x'%c' ", (unsigned char)evalsim_mem32(i), (unsigned char)evalsim_mem32(i));
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PRINTF("0x%.2x'%c' ", (unsigned char)evalsim_mem32(i), (unsigned char)evalsim_mem32(i));
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}
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}
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PRINTF(OR1K_MEM_VERILOG_FOOTER);
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PRINTF(OR1K_MEM_VERILOG_FOOTER);
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}
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}
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void dumphex(unsigned int from, unsigned int to)
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void dumphex(unsigned int from, unsigned int to)
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{
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{
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unsigned int i;
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unsigned int i;
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for(i = from; i < to; i++) {
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for(i = from; i < to; i++) {
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unsigned int _insn = evalsim_mem32 (i);
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unsigned int _insn = evalsim_mem32 (i);
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int index = insn_decode(_insn);
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int index = insn_decode(_insn);
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if (index >= 0)
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if (index >= 0)
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{
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{
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PRINTF("%.8"PRIx32"\n", evalsim_mem32(i));
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PRINTF("%.8"PRIx32"\n", evalsim_mem32(i));
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i += insn_len(index) - 1;
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i += insn_len(index) - 1;
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}
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}
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else
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else
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PRINTF("%.2x\n", evalsim_mem8(i));
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PRINTF("%.2x\n", evalsim_mem8(i));
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}
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}
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}
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}
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